JPH0528114A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To attain a multiprocessor system having the high program execution efficiency in regard of the interruption processing by reducing the overhead of a processor required for searching processor that performs the interruption processing. CONSTITUTION:In a multiprocessor system where plural processor modules 1-n are connected together with a bus B, each of these modules is provided with a flag register 1b which holds the interruption permission-/inhibition state in the processor module, an interruption handler 1c which decides whether an external interruption request should be sent to its own processor or the next processor module, an interruption requester 1d which sends the interruption request decided by the handler 1c to the next processor module. Then the interruption request line of an interruption control bus is formed in a daisy chain.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system having a plurality of processors, and more particularly to improving interrupt handling of the multiprocessor system.

[0002]

2. Description of the Related Art In a multiprocessor system having a plurality of processors, when an interrupt from an input device occurs, it is necessary to select a processor for executing the interrupt process.

Conventionally, a processor dedicated to accepting an interrupt from an input device is arranged in the system in order to select a processor for performing an interrupt process, and the state of each processor is checked after the processor receives the interrupt. The mainstream method is that the processor that executes the interrupt is determined.

[0004]

In the above case, in order to perform the processing for determining the processor to perform the interrupt processing, it is necessary to temporarily suspend the processing that a certain processor has been performing until then.

As described above, the processing on the processor side is required every time an interrupt occurs, and the program execution efficiency is reduced. The present invention has been made in view of the above-mentioned problems of the prior art. An object of the present invention is to reduce the overhead on the processor side for searching for a processor that performs interrupt processing and to improve program execution efficiency. It is to realize a multiprocessor system.

[0006]

Means for Solving the Problems In a multiprocessor system in which a plurality of processor modules are coupled by a bus, each processor module is configured to enable / disable an interrupt in the processor module. A flag register that holds the disabled state,
An interrupt handler that decides whether to send an externally supplied interrupt request to its own processor or to a subsequent processor module, and an interrupt requester that sends the interrupt request determined by the interrupt handler to the subsequent processor module. And the interrupt request line of the interrupt control bus is composed of a daisy chain.

[0007]

According to the present invention, whether or not a program is a priority program that may be interrupted when the program starts on the processor is enabled / disabled by the interrupt enable / disable held in the interrupt flag register.
Judge according to the prohibition flag. If a processor module has interrupts disabled, it is sent to the subsequent processor module via the interrupt request line of the daisy chain. In this way, the processor that performs interrupt processing is selected. Therefore, when an I / O interrupt occurs, the processing on the processor module side for determining which processor module executes the processing becomes unnecessary.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a configuration diagram showing a first embodiment of the present invention. In this figure, a plurality (N) of processor modules 1 to n and an I / O subsystem 11 are connected to a bus B. And the interrupt control bus is
The interrupt request signal forms a daisy chain between the processor modules.

The processor module 1 is composed of a processor 1a, an interrupt flag register 1b, an interrupt handler 1c, and an interrupt requester 1d. The other processor modules have the same configuration.

The I / O subsystem 11 is
It is composed of an I / O device 11a and an interrupt requester 11b. In the processor module,
The interrupt flag register holds a flag indicating whether a processor in the processor module is ready to accept an interrupt. If the processor is ready to accept an interrupt, it asserts an interrupt signal for the processor. If the interrupt cannot be accepted, the interrupt signal to the processor is not asserted, and the interrupt handler requests the interrupt requester to interrupt another processor module.

The interrupt requester receives a request from the interrupt handler and sends an interrupt request signal to the processor module at the subsequent stage. The operation of the apparatus of this embodiment configured as described above will be described with reference to the flowcharts of FIGS. In these figures, the processor module is abbreviated as PM.

In the initial state, the interrupt requester 10a is set so as to suppress the occurrence of interrupts from the I / O subsystem 10 (step 1 in FIG. 2). Further, the processor modules 1 to n are in a state where interrupts can be accepted (step 2 in FIG. 2). Here, the acceptance level, which is the interrupt threshold, is set (see FIG. 2).
Step 3).

Then, a signal for making the I / O subsystem 10 ready for interrupt generation is sent from the processor module side to the I / O subsystem 10 (step 4 in FIG. 2).

In this state, if an interrupt occurs, I /
The O subsystem 10 sends an interrupt to the processor module 1 (step 5 in Figure 2). The processor 1a in the processor module 1 refers to the flag register 1b to detect whether an interrupt is possible (step 6 in FIG. 2).

If the processor module 1 is in the interrupt-acceptable state, the interrupt is accepted and processing is started (step 7 in FIG. 2). Then, the interrupt level and the acceptance level are compared, and if the interrupt level> the acceptance level, the interrupt acceptance state is set, and the interrupt level <
If it is the acceptance level, the interrupt acceptance refusal state is set (steps 9 and 10 in FIG. 3). And interrupt approval I
Return to the / O subsystem (step 11 in Figure 3),
The assigned process is executed (step 12 in FIG. 3).
Then, the interrupt acceptance is set (step 13 in FIG. 3). Here, the interrupt level indicates the level of the generated I / O interrupt.

On the other hand, the I / O subsystem 10 receives the interrupt approval (step 14 in FIG. 3) and returns to the interrupt generation wait state. When the processor module 1 is in the interrupt unacceptable state, the interrupt signal to the processor 1a is not asserted, and the interrupt handler 1c
Requests the interrupt requester 1d to interrupt the subsequent processor module. The interrupt requester 1d receives the request from the interrupt handler 1c and sends an interrupt request signal to the processor module 2 in the subsequent stage.

Here, the processor 2a in the processor module 2 refers to the flag register 1b to detect whether an interrupt is possible (step 6 in FIG. 2). If the processor module 2 is ready to accept an interrupt, the interrupt is accepted and processing is started. Then, the interrupt level and the acceptance level are compared, and if the interrupt level> the acceptance level, the interrupt acceptance state is set, and if the interrupt level <the acceptance level, the interrupt acceptance refusal state is set. Furthermore, I / O for interrupt approval
It returns to the subsystem and executes the assigned processing (step 17 in FIG. 3). That is, the processes of steps 7 to 12 are similarly executed.

When the processor module 2 is in the interrupt unacceptable state, the interrupt signal for the processor 2a is not asserted, and the interrupt handler 2
c requests the interrupt requester 2d to interrupt the processor module 3 in the subsequent stage.
That is, the interrupt requester 2d receives a request from the interrupt handler 2c and sends an interrupt request signal to the processor module 3 in the subsequent stage. Then, in the same manner, the processing within the processor module or the transfer of the interrupt is executed (steps 19, 20, and 21 in FIG. 3).

As described above, since the entire sequence for determining the interrupt destination processor is configured by hardware, the processor module that handles the interrupt is automatically selected by the hardware. That is,
By determining whether or not the program has a priority that may be interrupted when the program starts on the processor and setting the interrupt enable / disable in the interrupt flag register, the processor for interrupt processing can be selected. ..

Therefore, when an I / O interrupt occurs, the processing on the processor module side for deciding which processor module executes the processing becomes unnecessary. In addition, since the processor module that causes the smallest performance degradation when performing an interrupt handles the interrupt, the execution efficiency of the user program is improved.

By the way, in recent years, a processor having a cache memory has been widely used. Under such an environment, the program is loaded and executed on the cache memory that can be accessed at higher speed.

However, in the conventional method, when an interrupt occurs in a certain processor (master / CPU), a processor (slave / CPU) that causes the interrupt processing to be performed.
When the program (INTPROG) for determining the above is executed on the master CPU, loading INTPROG on the cache memory of the master CPU causes the program on the existing cache to be overridden. When the slave CPU is decided and the original program is to be executed again, the original program needs to be loaded again into the cache memory of the master CPU. The larger the overhead of reloading the program, the more remarkable the effect of this embodiment. The same can be said for the slave CPU as well for the overhead in which the program that executes the interrupt process ejects the program that is already executing in the cache memory and loads the program that executes the interrupt process.

However, in this embodiment, since the enable / disable of the interrupt is determined by the program, the response speed of the interrupt process is influenced by the frequency with which the program is executed.
That is, if a program for determining enable / disable of interrupt is incorporated in the program of the scheduler, the scheduler scheduled cycle becomes the maximum interrupt cycle. If the program is executed for each function call, the function call cycle (which depends on the program, but can be adjusted by the scheduler) becomes the maximum interrupt cycle.

As described above, according to this embodiment, the performance can be improved by reducing the load / store of the cache of the processor as much as possible.

[0025]

As described above in detail with the embodiments, since the entire sequence for determining the processor of the interrupt destination is configured by hardware, the processor module that processes the interrupt is automatically selected by the hardware. That is, it is determined whether or not the program has a priority that may be interrupted when the program starts on the processor, and interrupts are enabled / disabled.
By setting disable to the interrupt flag register,
A processor that performs interrupt processing can be selected. Therefore, when an I / O interrupt occurs, the processing on the processor module side for determining which processor module executes the processing becomes unnecessary. In addition, since the processor module that causes the smallest performance degradation when performing an interrupt handles the interrupt, the execution efficiency of the user program is improved.

Therefore, with respect to interrupt processing, it is possible to reduce the overhead on the processor side for searching for a processor that performs interrupt processing, and to realize a multiprocessor system with good program execution efficiency.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing an operating state of an embodiment of the present invention.

FIG. 3 is a flowchart showing an operation state of one embodiment of the present invention.

[Explanation of symbols]

 1 Processor Module 2 Processor Module 3 Processor Module N Processor Module B Bus 10 I / O Subsystem

Claims (1)

Claim: What is claimed is: 1. In a multiprocessor system in which a plurality of processor modules are coupled by a bus, each processor module holds a flag that holds a state of enabling / disabling an interrupt in the processor module. -Registers, an interrupt handler that determines whether to send an externally-requested interrupt request to its own processor or a post-stage processor module, and the interrupt request determined by the interrupt handler to the post-stage processor module A multiprocessor system characterized in that it has an interrupt requester for sending out, and the interrupt request line of the interrupt control bus is composed of a daisy chain.