JPS60147845A - System for controlling load of circulating pipeline type data flow computer - Google Patents

Abstract

PURPOSE:To avoid the deadlock of a system caused by the overflow of a cue, by appropriately delaying the executing time of a function wake-up instruction depending upon the number of data staying at the cue. CONSTITUTION:Execution of a function wake-up instruction CALL is started when a new function identifier is obtained. In this case, the load of a data flow computer DFM is first checked from a threshold deciding circuit 10 and, when no overload exists, the function identifier is put in a cue 4 as an arithmetic result. In the case of an overload, the function identifier is put in a function wake-up instruction cue 11. Reopening of the interrupted CALL instruction is made at the time up of a timer 12. Even at the reopening of the interrupted CALL instruction, the load of the computer DFM is checked by means of the threshold deciding circuit 10 and, when an overload exists, the executing of the CALL instruction is again interrupted. When no overload exists, the CALL instruction at the leading head of the cue 11 and its accompanying function identifier are fetched and the function identifier is put in the cue 4 as the arithmetic result.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a system for dynamically controlling the execution timing of a function activation instruction in a linked pipeline data flow computer.

[Prior art]

FIG. 1 shows a schematic configuration of a linked pipeline data flow computer. In FIG. 1, 1 is an instruction memory, 2 is a data memory, 3 is an arithmetic unit, and 4 is a queue or buffer storage device, which are coupled in a ring. The instruction memory 1 is a memory that stores a data flow program defined by a functional language, and the data memory 2 is a memory that stores data flowing on the data flow program.

The arithmetic unit 3 is a unit that executes arithmetic operations on the data in the data memory 2, and data resulting from the arithmetic operations is passed to the instruction memory 1 via a queue 4. The role of the queue or buffer storage device 4 is to absorb disturbances in data flow caused by unbalanced processing speeds in the instruction memory 1, data memory 2, and arithmetic unit 3.

Here, a case where data stays in the queue 4 and the queue length increases will be described below.

Figure 2 is an example of a data flow program, and the black circles above the □- marks (arrows) represent data. Now assume that the moment when the operation of the operation node OP1 is performed and the result is obtained. At this point, it is assumed that the data of the other party of OP2゜○P310P4 has already arrived. If the output data of OP is distributed to OP2 to OP4, those operations can be executed at any time.

Now, for the sake of simplicity, it is assumed that the data memory 2 and the arithmetic unit 3 process data in one unit time.

Further, it is assumed that the instruction memory 1 processes data allocation to one operation node in one unit time. Therefore, in the example of FIG. 2, the instruction memory requires three
It takes unit time. Assuming that the pipeline is flowing without disturbance, instruction memory 1 transfers the output data of OP to op2.
~OP.

At the point when the distribution is finished, two pieces of data will have been added to queue 4. The situation is shown in Figure 3. In FIG. 3, circles indicate data that is being processed.

In Figure 3(a), queue 4 is the output data of OP1 (black circle)
The state immediately after sending is shown. The instruction memory 1 receives the output data of this OP, and distributes it to OP2 to OP4. FIG. 3(b) shows a state in which the instruction memory 1 sends data of OP to, for example, the second operand of OP2. Figure 3 (
C) shows a state in which the instruction memory 1 sends data of ○P to, for example, the first operand of OP3, and at this time, the data memory 2 arranges the data of OP2 and sends it to the arithmetic unit 3.

In FIG. 3(d), the instruction memory 1 sends data of 6P to the first operand of, for example, OP, and at this time, the data memory 2 arranges the data of ○P and sends it to the arithmetic unit 3.
The calculation device 3 shows a state in which OP2 is executed. Figure 3 (
e), instruction memory 1 is OP, data from OP2 to oP4
When the distribution to 3- is completed, there is 3-, and at this time, the data memory 2 arranges the data of OP and sends it to the arithmetic unit 3, and the arithmetic unit 3 executes OP3.

As described above, when arithmetic units are distributed to a plurality of operation nodes, the amount of data remaining in the queue generally increases.

On the other hand, as a qualitative characteristic of a program (function), in the first half of the program (function), the operation result is often distributed to multiple operation nodes, and conversely, in the second half, the operation result is distributed to one operation node. There are many things. The higher the parallelism of the program, the higher the probability, and this tendency is strong.

Therefore, when function activation instructions were executed successively in a conventional connected pipeline data flow computer, there was a risk that the queue length would rapidly increase.

Furthermore, if the queue becomes full and the data being executed in the instruction memory at that time is data that needs to be distributed to multiple operation nodes, this system has the disadvantage of deadlock.

4- [Object of the Invention] An object of the present invention is to provide a load control method that avoids system deadlock due to J-queue overflow in a linked pipeline data flow computer.

[Embodiments of the invention]

FIG. 4 is a block diagram of an embodiment of the present invention. Here, the functions of the instruction memo 1 negative J data memory 2, arithmetic unit 3 and queue 4 are as explained in FIG. 1. Reference numeral 10 denotes a threshold value determination circuit, which determines whether the number of data currently staying in the queue 4 exceeds a preset threshold value.

Reference numeral 11 denotes a face number activation instruction queue, which has a configuration capable of holding a plurality of function activation instructions. 12 is a timer, which is used to trigger the execution of a function activation instruction. A control circuit 13 controls the execution of function activation instructions.

Note that when the data flow computer is implemented using a microprogram control method, the control circuit 13 is absorbed into the microprogram.

Execution of a function activation instruction will be described below. Other instructions operate in the same manner as in a conventional linked pipeline type data flow computer, so their explanation will be omitted.

First, the function activation mechanism will be explained using a program that calculates a factorial as an example. A program to calculate the factorial.

f (n)=if n=o then 1 else
It is given by n * f (n −1). Here, f is a function that calculates the factorial. f is a recursive function that calls itself within itself. The data flow graph of this program is shown in FIG. The large box with the label f at the top left represents the above function. The outside describes only the environment in which f is called.

Program f is executed using the function activation command CAL outside the box.
It is started by the execution of L. CALL is an instruction to obtain a new function identifier. In the present invention, when executing CALL, the data flow calculator (DEM
), and if the load is overloaded, execution is interrupted, otherwise execution is completed. The details will be described later. After execution of CALL, parameters necessary for execution of f (n and rz Ru * "R" is the return address) are passed to f (LINK and RLINK), and execution of f is started. Since f is a recursive function, it calls itself in the middle of the box, again using the activation mechanism just described.

How the function activation instruction CALL of FIG. 5 works in FIG. 4 will be explained below.

The arithmetic unit 3 manages function identifiers.

Currently unused function identifiers can be provided on request. CALL is executed as follows under the control of the control circuit 13.

■ Obtain a new function identifier.

-'/- ■ Check the DFM load. This is done by the control circuit 13 receiving the determination result of the threshold determination circuit 10.

Then, if it is overloaded, go to ■, otherwise go to ■.

■ Output the function identifier obtained in ■ as the operation result (put it in the queue). This completes the CALL execution.

(2) Put the CALL command and the function identifier obtained in (2) into the function activation command queue 11 (CALL command interruption).

The interrupted CALL command is restarted when the timer 12 times up. Here, time-up detection may be performed by either an interrupt or polling, but the restart process will be described below assuming an interrupt.

■ Detect interrupt from timer 12. Start the CALL restart process and execute ①.

■ Check the DFM load. This is the same as ■.

This is performed by the control circuit 13 receiving the determination result of the threshold determination circuit 10. Then, if it is overloaded, it is interrupted again, and if not, it goes to ■.

8-(1) If the function activation command queue 11 is empty, the process ends; if not, the CALL command at the head of the queue and the accompanying function identifier are taken out, and the function identifier is output as the result of the operation (placed in the queue 4). This completes the interrupt processing.

As described above, since the function activation is executed, the number of data remaining in the queue 4 is controlled to be less than the threshold value, making it possible to avoid queue overflow.

Note that as a modification of the above method, a method may be considered in which the CALL instruction is executed only when time-up occurs.

That is, at step (2), the process goes to step (2) regardless of the magnitude of the load. This purpose is to
When LL instructions arrive at the arithmetic unit in succession, their execution is delayed by an amount equivalent to the timer interval, and the effect is that an excessive increase in the number of data remaining in the queue 4 can be suppressed.

Furthermore, the load control method of the present invention is also effective in a dataflow type multiprocessor system having a DFM as an element processor (PE). In other words, in a system that dynamically allocates functions between PEs, P with the lightest load
The strategy is to execute the function with E. In this case, function activation may be temporarily concentrated on one PE (with the least load). At this time, the load control method of the present invention functions effectively.

〔Effect of the invention〕

As explained above, according to the present invention, the timing of execution of a function activation instruction can be appropriately delayed and the system load can be controlled so as not to become excessively heavy. This has the advantage of avoiding system deadlock due to queue overflow.

[Brief explanation of the drawing]

Fig. 1 is a schematic configuration diagram of a patrol pipeline type data flow computer, Fig. 2 is a diagram showing an example of a data flow program, Fig. 3 is a diagram showing the data flow in Fig. 1, and Fig. 4 is a diagram of the present invention. FIG. 5 is a block diagram of one embodiment of the present invention, and FIG. 5 is a diagram showing an example of a data flow graph for explaining the operation of FIG. ■...Instruction memory, 2...Data memory, 3...
Arithmetic unit, 4... Buffer storage device, 10... Threshold value determination circuit, 11... Function activation command queue, 12...
Timer, 13...control circuit. Figure 1 Figure 3 (Q,)'('b) Figure 4 [f

Claims (1)

[Claims] (1) An instruction memory that stores a data flow program defined by a functional language, a data memory that stores data flowing on the data flow program, an arithmetic device that executes operations on the data, and the instruction memory i
In a linked pipeline data flow computer, data memory and a buffer storage device that absorbs disturbances in data flow caused by unbalanced processing speeds of arithmetic units are connected in a circular manner. and determining means for determining whether the number of data remaining in the buffer memory device exceeds a predetermined threshold, and determining whether the number of data remaining in the buffer memory device is less than the threshold value when the function is activated. For example, when the function activation instruction is executed and the number of data exceeds a threshold value, the function activation instruction is held in the queue means, and restarted when the number of data in the buffer storage device becomes less than or equal to the threshold value. A load control method that uses