JPH08161195A - Address trace storing device and method for generating address trace - Google Patents

Abstract

PURPOSE: To provide an address trace storing device capable of storing an address trace for a long period by the use of smaller capacity. CONSTITUTION: In an address trace generating device for storing execution addresses for a central processing unit (CPU) 101 of a computer in a trace memory 104, an address supplying means 102 receives the information of an execution address 105 from the CPU 101 and supplies the received address to a control means 103. The means 103 receives the sort 106 of an address instruction from the CPU 101 and commands the memory 104 to selectively store an address in accordance with the sort 106 of the instruction. Since an address trace for a long period is stored in the trace memory 104 whose capacity is limited, an exclusive trace memory is made unnecessary.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer processor, and more particularly to an address trace storage device and an address trace generation method for use in program debugging in a central processing unit.

[0002]

2. Description of the Related Art A first conventional address trace storage device.
In this method, a dedicated trace memory is installed for analysis when a failure occurs in the processing in the central processing unit, and the operation history of the central processing unit, specifically, the execution address is recorded in the trace memory for each instruction execution. It was something to do.

The second method is Japanese Patent Laid-Open No. 4-42331.
As described in Japanese Patent Publication, only the execution address is observed, and when the execution address is discontinuous, the recording instruction is given to the trace memory, and when the execution is continuously performed, the address recording is not performed, which is relatively small. The capacity of the trace memory enables the trace to be stored for a long period of time.

The third method is for the purpose of the debugger to store the address trace in the main memory in a computer that does not have a dedicated trace memory and to realize the function trace. Only the arrival at the entry point is traced to the main memory. Specifically, as described in JP-A-4-42331, a breakpoint setting, that is, a trap instruction is embedded at the entry point of the function, the debugger captures the trap, and the address of the interruption point is stored in the main storage device. The function address trace is realized by.

Note that the first and second methods are superior to the third method, and by using a high-speed trace memory, it is possible to perform address tracing while operating the program to be debugged in real time. This is a point, and the first, second, and third methods are currently widely used.

[0006]

However, the problems with the first and second methods are that the execution instruction address is traced every clock or every non-sequential occurrence of the execution address, so that it takes a very long period of time. It has a problem that the trace cannot be stored. Alternatively, there is a problem in that it is necessary to provide an extremely large-capacity trace memory to store the trace for a long period of time.

Another problem with the first and second methods is that in the initial testing of program testing, detailed trace information at the instruction level is required. Although it is necessary to perform tracing in function units to perform the test, there is a problem that a large-capacity trace memory is required because address tracing is performed every time an instruction is executed or each execution address is discontinuously generated. .

SUMMARY OF THE INVENTION Therefore, in view of the above problems, an object of the present invention is to provide an address trace storage device having a smaller capacity and capable of storing an address trace for a long period of time.

In the third method, the function trace is realized to prevent the address other than the entry point address of the function from being stored. However, the debugger must always hold the entry point address over all the functions of the program to be debugged, which causes a problem of squeezing the main memory.

Therefore, the present invention provides an address trace storage device that makes it unnecessary for the debugger to hold the entry point address of the program to be debugged in advance.

[0011]

In order to achieve the above object, the address trace storage device of the present invention selectively controls the timing for storing the address trace, and reduces the storage of the address trace. .

Specifically, the solution means taken by the invention of claim 1 temporarily stores the execution address of the computer central processing unit,
Address supply means for supplying an address to the storage means,
A control means is provided for selectively storing and instructing the address supplied from the address supply means to the trace memory according to the type of instruction.

The invention of claim 2 is, specifically, claim 1
In addition to the configuration of the invention described above, the control means adds a configuration having a control means for selecting only a branch destination address of a CALL instruction and instructing storage.

The invention of claim 3 is, specifically, claim 1
In addition to the configuration of the invention described above, the storage means has a configuration including a cache memory in which addresses are stored in a cache-off mode.

Further, specifically, the solving means devised by the invention of claim 4 sets the processor status register so as to break at every function call of the program to be debugged, and the debugger traces an address to the main memory device at each break. Is configured to be stored.

[0016]

According to the structure of the first aspect of the present invention, the address trace generated in the address trace storage device is not performed for all instruction executions, and the storage capacity is reduced.

According to the configuration of the second aspect of the present invention, the address trace is performed only when the CALL instruction is executed, and the storage capacity is reduced.

According to the third aspect of the present invention, the address trace generated in the address trace storage device is performed on the cache memory in the cache off mode, and the dedicated trace memory is unnecessary.

According to the invention of claim 4, it is not necessary to place a trap instruction for a break for each entry point address, and therefore the code area of the debugger for this purpose and the area for the entry point address table are reduced. Will be possible.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An address trace storage device according to an embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of an address trace storage device in a first embodiment of the present invention. The address trace storage device of the present embodiment uses a dedicated trace memory to perform selective address trace according to the instruction type.

Reference numeral 101 denotes a central processing unit that notifies the address supply means 102 of the execution address 105. 1
Reference numeral 02 denotes an address supply means, which outputs the execution address 107. Reference numeral 104 denotes a trace memory which inputs the execution address 108 and sequentially stores it up to the capacity limit. When the capacity limit is reached, the trace memory returns to the beginning and is stored. Reference numerals 109 and 111 are address buses, and 110 and 112 are data buses.

The above components are configured by a well-known technique. The features of the present invention will be described below.

Reference numeral 103 is a control means for receiving the instruction address notification 106 from the execution address 107 and the central processing unit and outputting the execution address 108 according to the instruction type.
A branch instruction or a CALL instruction is specifically targeted as the instruction type.

The operation of the address trace storage device configured as described above will be described below with reference to FIGS. 1 and 4.

FIG. 4A shows an example of a program to be debugged for collecting a trace, and includes load instruction (LD), branch instruction (B), CALL instruction, NOP instruction, and SAVE, RESTORE, RET instructions. It is shown that (8 instructions in total) are included. FIG.
4B is a diagram showing the result of tracing only the branch destination address of the branch instruction in the instruction sequence of FIG. FIG.
(C) is a diagram showing the result of tracing only the branch destination address in the CALL instruction. Here, the execution locus of the program can be traced even if the address of only the branch instruction is collected. In this case, the number of executed instructions is 8 and the address trace is only 3 entries.

The address collection of only the CALL instruction is performed for the purpose of realizing the function address trace.
In this case, one address trace is sufficient.

As described above, according to this embodiment, the amount of address traces stored in the trace memory can be reduced.

(Second Embodiment) FIG. 2 is a block diagram of an address trace storage device according to a second embodiment of the present invention. The address trace generation device of the present embodiment uses a cache memory in the cache-off mode instead of a dedicated trace memory to perform selective address trace depending on the instruction type. The difference from FIG. 1 is that the cache memory 204 is used instead of the dedicated trace memory. Those having the same functions as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

As is well known, the cache memory 204 is a small-capacity high-speed memory that is placed between the central processing unit 101 and the main memory (not shown). However, in the cache-off mode, the memory cells of the cache memory are normally high-speed. It is equivalent to a memory and can be operated as a trace memory by a control circuit.

(Third Embodiment) FIG. 3 is a block diagram showing the arrangement of an address trace storage device according to the third embodiment of the present invention. The address trace generation device of this embodiment performs a function address trace using a main memory device and a debugger.

An external storage device 301 stores a load module 306 including an entry point address table 304 of the program to be debugged and a function group 305.

Reference numeral 302 denotes a main storage device, which is a debugger 30.
Copy of function group body 307 downloaded by 3
A load module 310 consisting of A function 308 is a function in the function group main body 307, and the start address is indicated by the entry point address table 304.

The debugger 303 activates the load module 310 on the main memory 302 and collects a trace.
When the execution is interrupted (the interrupting method will be described later), the interrupt point address is sequentially stored in the main memory in the debugger. The breakpoint address is, for example, SPAR
With the C architecture, the contents are automatically stored in the% r15 register. Further, in the case of Intel 8086 architecture, the contents are automatically stored in the stack.
The debugger stores the content as an interruption point address, sequentially repeats restart and interruption, and accumulates the interruption point address, thereby realizing the function of the address trace.

Now, a method of controlling the processor state to generate interruption will be described. Processor (not shown)
Generally fetches and executes each instruction of the function 308 in the load module. The fetched instruction is CAL
In the case of L instruction, it branches to the function address indicated by the operand of the instruction. The function entry code 309 includes a formal code string usually called a prologue code. Although the method differs depending on the processor, for example, in a processor of the SPARC architecture, the SAVE instruction is always included in it. Then, by setting the WIM register (status register), a trap can be generated when the SAVE instruction is executed. Thus, instead of the conventional method of embedding a trap instruction at every entry point of a function, it becomes possible to generate a trap at the entry point of a function by setting the state register of the processor.

The operation of the address trace storage device configured as described above will be described below with reference to FIGS. 3 and 5.

FIG. 5A is a flow chart showing the processing of the debugger. As shown in FIG. 5A, first, the function group 305 is extracted from the load module 306 stored in the external storage device 301, and the main storage Function group body 3 on device 302
08 is created (step S1).

Next, as described above, the processor state is set so as to break at the prologue code (entry code) of the function (step S2). Then, the program to be debugged is activated (restarting from the interruption point in the second and subsequent loops) (step S3).

The program to be debugged breaks at the entry point of each function for setting in step S2 and returns to the debugger. When returning to the debugger, the debugger stores, for example, the interrupt point address stored in the% r15 register or the stack in the main memory device in the debugger (step S4). Next, it is judged whether or not the trace is to be ended (step 5). If NO, the process returns to step S2, and YE
If S, end.

In FIG. 5 (b), the program to be debugged used for the explanation calls the function (steps S6, S6).
7) including any processing step including 7).

FIG. 5C shows that each function breaks (interrupts) at the entry point, returns to the debugger, and restarts from the next address because of the setting in step 2.

As described above, the function trace can be realized by using the debugger 303 and the main memory 302 as in the present embodiment, and at this time, it is necessary to place the trap instruction for the break at each entry point address. This reduces the debugger code area for this.

Further, in the present embodiment, the entry point address table, which was required in advance for embedding the trap instruction at the entry of each function, is unnecessary, so that the capacity of the trace memory can be further increased.

[0044]

As described above, according to the address trace storage device of the first and second aspects of the present invention, the amount of address traces stored in the storage means can be small, and the address traces can be stored for a longer period of time. be able to.

According to the address trace storage device of the third aspect of the present invention, a dedicated trace memory can be dispensed with, and the amount of address traces stored in the cache memory can be small, so that the address can be stored for a longer period of time. Traces can be stored.

Further, according to the address trace generating method of the present invention, it is not necessary to provide a trap instruction for a break for each entry point address. Therefore, the code area of the debugger and the entry point address table for this purpose are set. Area can be reduced, and the capacity of the trace memory can be increased.

As described above, according to the present invention, a long-term address trace can be stored in the trace memory, cache memory, or main memory having a limited capacity, and the effect is great.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an address trace storage device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing an address trace storage device according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram showing a device configuration of an address tracing method according to a third embodiment of the present invention.

FIG. 4A is a diagram showing an example of a program to be debugged for trace collection. FIGS. 4B and 4C are diagrams showing trace results.

5A is a flowchart showing processing of a debugger by an address trace storage device, FIG. 5B is a flowchart showing processing of a debugged program activated by the debugger, and FIG. 5C is a flowchart of each function called in the debugged program. Flow chart showing processing

[Explanation of symbols]

 101 central processing unit 102 address supply means 103 control means 104 trace memory 105, 107, 108 execution address 106 control signal 109, 111 address bus 110, 112 data bus 204 cache memory 301 external storage device 302 main storage device 303 debugger 304 entry point Address table 305,307 Function group 306,310 Load module

Claims (4)

[Claims] 1. An address trace storage device having a storage means for recording an execution address of a computer central processing unit over a fixed period, and temporarily storing an execution address for each instruction execution of the computer central processing device. Address supply means for supplying an address to the storage means, and control for selecting and storing only a specific instruction by monitoring the instruction type when instructing the storage means to store the address supplied from the address supply means. An address trace storage device comprising: 2. The address trace storage device according to claim 1, wherein said control means controls so as to select only a branch destination address of the CALL instruction and issue a storage instruction. 3. The address trace storage device according to claim 1, wherein said storage means is composed of a cache memory and stores the address trace in a cache off mode. 4. An address trace generation method comprising a computer central processing unit, a main memory unit and a debugger, wherein the address trace generation processing by the debugger sets a processor state so that a break can be made at each function call of a program to be debugged. An address trace generation method comprising: a step of activating or resuming a program to be debugged; and a step of a debugger storing an address trace in a main memory for each break.