JP2010015364A - Multiprocessor system and information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiprocessor system and an information processor for making it unnecessary to add any exclusive hardware device, or to change to the software of a processor in which a target program operates, and for making it possible to recognize and analyze the operation of the target program. <P>SOLUTION: This multiprocessor system includes: CPUs 1 and 2 as a plurality of processors connected to a common bus 13 as a common system bus; an exception notification part 20 as an exception notification means for notifying a CPU 2 as a second processor of occurrence of an exception in the CPU 1 as a first processor between the plurality of processors; and an exception information storage part 30 as an exception information holding means for holding information related to the state of the first processor when the exception occurs in the first processor. The second processor acquires information stored in the exception information storage means according to the notification by the exception notification means. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a multiprocessor system and an information processing apparatus, and more particularly to a multiprocessor system including a plurality of processors connected to a common system bus.

  Exception processing is processing for interrupting execution of an instruction sequence of a program during execution of the program and executing a different instruction sequence, and is performed inside the processor system. Exception processing is triggered when an error occurs due to instruction execution, for example, when a trap instruction is executed for a system call that calls a function of the operating system, or when a page fault occurs for operating the memory management mechanism. is there. When an exception occurs in the processor, the program being executed by the processor is interrupted, and information on the state of the processor at the time of the exception occurrence, such as a program counter and a status register, is saved in the processor system. In addition, a different exception handler is executed for each cause of the exception that has occurred. The exception handling handler is a program in which exception handling is described, and is generally implemented as a part of the operating system. When the exception processing is completed, the processor state is recovered based on the saved information, and the execution of the program when an exception occurs is resumed.

  Conventionally, a technique of a debugging support apparatus that debugs a program executed in a multiprocessor system has been proposed (see, for example, Patent Document 1). In the technique proposed in Patent Document 1, when a debug exception occurs in a certain processor, another processor is stopped and used for debugging a multiprocessor system. The debugging support apparatus is composed of an online debugger and PC software. The online debugger is software that supports the discovery and correction of program bugs targeting a processor.

JP 2007-188147 A

  As means for grasping and analyzing the operation of the program, for example, there are a method of adding a hardware device such as ICE (In-Circuit Emulator) and a method of realizing by software like the technique proposed in Patent Document 1. is there. When a hardware device is added, it is necessary to prepare a dedicated device for grasping and analyzing the operation of the program, so that it is difficult to reduce the cost. Further, in the method realized by software, it is necessary to change the program such as adding a tracing instruction to the target program. In addition to changing the program itself, a method of using the function of the operating system on which the program operates can be used. In this case, the processing for grasping the operation of the program causes the execution timing to be different from the original operation of the program.

  The present invention has been made to solve these problems, and does not require the addition of a dedicated hardware device or a change to the software of the processor on which the target program operates, so that the target program can be changed. It is an object of the present invention to provide a multiprocessor system and an information processing apparatus capable of grasping and analyzing operations.

  In order to solve the above-described problems and achieve the object, the present invention relates to a plurality of processors connected to a common system bus and occurrence of an exception in a first processor among the plurality of processors. Exception notification means for notifying to a second processor which is at least one processor other than the first processor, and exception information for holding information on the state of the first processor when an exception occurs in the first processor And holding means, wherein the second processor acquires information held in the exception information holding means in response to a notification from the exception notifying means.

  According to the present invention, there is an effect that it is possible to grasp and analyze the operation of the target program without adding a dedicated hardware device or changing the software of the processor on which the target program operates. .

  Embodiments of a multiprocessor system according to the present invention will be described below in detail with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 shows a block configuration of an information processing apparatus including a multiprocessor system according to Embodiment 1 of the present invention. The multiprocessor system according to the present embodiment includes two CPUs (Central Processing Units) 1 and 2, a main storage device 10, an interrupt controller 11, an IO device 12, a common bus 13, an exception notification unit 20, and an exception information holding unit. 30. The CPU 1 functioning as a first processor and the CPU 2 functioning as a second processor are connected to a common bus 13 that is a common system bus. In addition to the two CPUs 1 and 2, the main storage device 10, the IO device 12, the exception notification unit 20, and the exception information holding unit 30 are connected to the common bus 13. The main storage device 10 is configured such that addresses are assigned to the memory spaces of the CPUs 1 and 2 and the entire area can be accessed from the CPUs 1 and 2.

  When switching the processing of a program that is being executed, the multiprocessor system interrupts, for example, in task switching, notification of processing end of the IO device 12, and the like. The interrupt controller 11 functions as an interrupt control unit that controls interrupts to the CPUs 1 and 2. The interrupt controller 11 generates an interrupt to the CPU 1 or the CPU 2 by receiving interrupt requests from the inside and outside of the CPUs 1 and 2.

  The interrupt controller 11 can be set to generate an interrupt to any CPU 1 or 2 for each factor that generates an interrupt. For example, the interrupt controller 11 is configured to generate an interrupt to the CPU 1 in response to an interrupt request from the IO device 12 and to generate an interrupt to the CPU 2 in response to an interrupt request from the exception notification unit 20. The Such setting is normally performed in the initialization process at the time of system startup.

  The exception notification unit 20 functions as an exception notification unit that notifies the CPU 2 that is the second processor of the occurrence of an exception in the CPU 1 that is the first processor. The exception notification unit 20 sends an interrupt request to the interrupt controller 11 when an exception occurs in the CPU 1. In response to the occurrence of an exception in the CPU 1, the exception notification unit 20 sends an interrupt request having a single number. Alternatively, the exception notification unit 20 may send out interrupt requests with different numbers depending on the cause of the exception that has occurred in the CPU 1. The exception information holding unit 30 functions as an exception information holding unit that holds information about the state of the CPU 1 when an exception occurs in the CPU 1 that is the first processor.

  FIG. 2 illustrates the configuration of the exception information holding unit 30. The exception information holding unit 30 includes an exception factor holding unit 31, an exception instruction address holding unit 32, and an exception status holding unit 33. The exception factor holding unit 31, the exception instruction address holding unit 32, and the exception status holding unit 33 are all connected to the common bus 13. The exception factor holding unit 31 functions as an exception factor holding unit that holds information regarding the cause of the exception that has occurred in the CPU 1. The exception instruction address holding unit 32 functions as an exception instruction address holding unit that holds an address of an instruction in which an exception has occurred in the CPU 1.

  The exception status holding unit 33 functions as an exception status holding unit that holds information regarding the status of an exception that has occurred in the CPU 1. For example, when an exception due to an address error in a memory read instruction occurs, the exception status holding unit 33 holds an address where an error has occurred due to access to the memory. When an exception occurs due to the execution of the trap instruction, the exception status holding unit 33 holds a number that is an operand of the trap instruction.

  The exception information holding unit 30 may be either one that holds only information about one exception or one that holds information about a plurality of exceptions. When only the information about one exception is held, the exception factor holding unit 31, the exception instruction address holding unit 32, and the exception status holding unit 33 rewrite information held every time an exception occurs in the CPU 1. In the case of holding information about a plurality of exceptions, the exception factor holding unit 31, the exception instruction address holding unit 32, and the exception status holding unit 33 have, for example, a first in first out (FIFO) configuration.

  If an exception, for example, a page fault, an overflow, an address error, or the like occurs during execution of a program on the CPU 1, the processing in the CPU 1 is switched to exception processing. When an exception occurs, the CPU 1 reads the instruction at the memory address indicated by the exception processing vector and executes the exception processing handler corresponding to the generated exception.

  The exception notification unit 20 sends an interrupt request to the interrupt controller 11 when an exception occurs in the CPU 1. The interrupt controller 11 generates an interrupt to the CPU 2 by receiving an interrupt request from the exception notification unit 20. Upon receiving the interrupt, the CPU 2 reads the instruction at the memory address indicated by the interrupt vector, and executes an interrupt handler corresponding to the interrupt request sent from the exception notification unit 20. In this manner, the exception notification unit 20 notifies the CPU 2 of the occurrence of an exception in the CPU 1 by sending an interrupt request to the CPU 2 via the interrupt controller 11.

  FIG. 3 is a flowchart for explaining processing of the interrupt handler in the CPU 2 as the second processor. In the CPU 2, an interrupt handler corresponding to the interrupt request from the exception notification unit 20 is executed. When the execution of the interrupt handler in the CPU 2 is started, the CPU 2 acquires information on the exception factor held in the exception factor holding unit 31 in step S11. The CPU 2 reads information held in the exception factor holding unit 31 via the common bus 13.

  In step S <b> 12, the CPU 2 acquires the address held in the exception instruction address holding unit 32. The CPU 2 reads the information held in the exception instruction address holding unit 32 via the common bus 13. In step S <b> 13, the CPU 2 acquires information regarding the exception status held in the exception status holding unit 33. The CPU 2 reads out the information held in the exception status holding unit 33 via the common bus 13. As described above, the CPU 2 that is the second processor acquires the information held in the exception information holding unit 30 in response to the notification from the exception notification unit 20. Note that steps S11, S12, and S13 do not have to be in particular order, and are not limited to such order.

  Next, in step S <b> 14, the CPU 2 stores the information regarding the cause of the exception acquired in step S <b> 11, the address acquired in step S <b> 12, and the information regarding the exception status acquired in step S <b> 13 in an area on the main storage device 10. In step S <b> 15, the CPU 2 notifies the exception notification unit 20 that acquisition of information related to the state of the CPU 1 when an exception has occurred is completed. Such notification is made via the common bus 13.

  The exception notification unit 20 cancels the interrupt request to the interrupt controller 11 by receiving a notification from the CPU 2 that information acquisition has been completed. The CPU 2 ends the execution of the interrupt handler when the exception notification unit 20 cancels the interrupt request. When the execution of the exception handling handler is completed, the CPU 1 reads out information on the state when the exception has occurred from the main storage device 10. Based on the information read from the main storage device 10, the CPU 1 resumes the program that was being executed when the exception occurred.

  The exception notification unit 20 notifies the CPU 2 of the occurrence of an exception, and the CPU 2 acquires the information held in the exception information holding unit 30, thereby grasping and analyzing the operation of the program executed by the CPU 1, Handle exceptions that occur in CPU1. This eliminates the need for adding a dedicated hardware device or changing the program, and has an effect of grasping and analyzing the operation of the target program. Further, since no change is made to the software of the CPU 1 in which the target program operates, the operation of the target program can be grasped and analyzed without changing the operation timing of the original program.

  The multiprocessor system is not limited to a configuration having two processors, and may have a configuration having three or more processors. In the multiprocessor system, when an exception occurs in the first processor among the plurality of processors, the second processor, which is a processor other than the first processor, can acquire information on the state of the first processor. I just need it.

Embodiment 2. FIG.
FIG. 4 shows a block configuration of an information processing apparatus including a multiprocessor system according to Embodiment 2 of the present invention. The multiprocessor system according to the present embodiment has an exception notification selection unit 40. The multiprocessor system according to the present embodiment has the same configuration as that of the multiprocessor system according to the first embodiment except that the multiprocessor system includes the exception notification selection unit 40. The same parts as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

  The exception notification selection unit 40 is connected to the common bus 13. The exception notification selection unit 40 functions as an exception notification selection unit that selects an interrupt request transmitted from the exception notification unit 20 in accordance with the cause of the exception that has occurred in the CPU 1 that is the first processor. When an exception occurs in the CPU 1, the exception notification unit 20 refers to the exception notification selection unit 40 and sends out the interrupt request selected by the exception notification selection unit 40 according to the cause of the exception.

  FIG. 5 illustrates an example in which the interrupt notification selection unit 40 selects an interrupt request. When an exception with exception factor number 1 or an exception with exception factor number 3 occurs in CPU 1, exception notification selection unit 40 selects interrupt request number 5. When an exception with the exception factor number 2 occurs in the CPU 1, the exception notification selection unit 40 selects the interrupt request number 6. When an exception with the exception factor number 4 occurs in the CPU 1, the exception notification selection unit 40 selects the interrupt request number 7.

  The interrupt controller 11 is set to generate an interrupt to the CPU 2 for all interrupt requests used as exception notification in the initialization process at the time of system startup. In the case of the example shown in FIG. 5, the interrupt request number 5, the interrupt request number 6, and the interrupt request number 7 are all interrupts to the CPU 2.

  FIG. 6 is a flowchart for explaining the processing of the interrupt handler corresponding to the interrupt request number 7. Here, it is assumed that the exception factor number 4 for which the exception notification selection unit 40 selects the interrupt request number 7 is an instruction address exception. In the case of an instruction address exception, it is assumed that the state of the CPU 1 can be grasped by using information on the cause of the exception and the address of the instruction in which the exception has occurred, and information on the status of the exception is unnecessary.

  When execution of the interrupt handler corresponding to the interrupt request number 7 is started in the CPU 2, the CPU 2 acquires information on the cause of the exception held in the exception factor holding unit 31 in step S 21. In step S <b> 22, the CPU 2 acquires the address held in the exception instruction address holding unit 32. Here, access to the exception status holding unit 33 is omitted.

  Next, in step S <b> 23, the CPU 2 stores information on the cause of the exception acquired in step S <b> 21 and the address acquired in step S <b> 22 in an area on the main storage device 10. In step S <b> 24, the CPU 2 notifies the exception notification unit 20 that acquisition of information related to the state of the CPU 1 when an exception has occurred is completed. The exception notification unit 20 cancels the interrupt request to the interrupt controller 11 by receiving a notification from the CPU 2 that information acquisition has been completed.

  For exception factor numbers 1 to 3, it is assumed that information regarding the cause of the exception, the address of the instruction in which the exception has occurred, and information regarding the status of the exception are used to grasp the state of the CPU 1. For the interrupt request number 5 selected by the exception factor number 1 or 3, and the interrupt request number 6 selected by the exception factor number 2, the processing of the interrupt handler is the same as that in the first embodiment shown in FIG. .

  By selecting an interrupt request to be used as an exception notification in accordance with the cause of the exception that has occurred in the CPU 1, the CPU 2 that is the second processor differs depending on the cause of the exception that has occurred in the CPU 1 that is the first processor. The interrupt handler is executed. As a result, it is possible to efficiently acquire information related to the state of the CPU 1 when an exception occurs.

  When the configuration includes three or more CPUs, the interrupt controller 11 may be configured to generate an interrupt to a different CPU for each interrupt request selected by the exception notification selection unit 40. As a result, the information of the CPU that is the first processor when an exception occurs can be acquired by the plurality of CPUs that are the second processor. The second processor may be at least one processor other than the first processor among the plurality of processors, and may be a plurality.

Embodiment 3 FIG.
FIG. 7 shows a block configuration of an information processing apparatus including a multiprocessor system according to Embodiment 3 of the present invention. The multiprocessor system according to the present embodiment has an exception factor designating unit 50. The multiprocessor system according to the present embodiment has the same configuration as that of the multiprocessor system according to the first embodiment except that the multiprocessor system includes an exception factor specifying unit 50. The same parts as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

  The exception factor specifying unit 50 is connected to the common bus 13. The exception factor designation unit 50 functions as an exception factor designation unit that designates an exception factor. The exception notification unit 20 notifies the CPU 2 of the occurrence of an exception only when the cause of the exception that has occurred in the CPU 1 is designated by the exception factor designation unit 50.

  FIG. 8 illustrates an example in which an exception factor is specified by the exception factor specifying unit 50. For example, the exception factor specifying unit 50 is configured to notify an exception for exception factor number 1 and not to notify the exception factor numbers 2, 3, and 4. In the example shown in FIG. 8, the exception factor designating unit 50 designates only the exception factor number 1 among the exception factor numbers 1 to 4 as a factor for notifying the CPU 2 of the exception by the exception notifying unit 20. Such setting is performed, for example, by the exception factor designation program operating on the CPU 2 for the exception factor designation unit 50.

  In the example illustrated in FIG. 8, the exception notification unit 20 notifies the exception by sending an interrupt request when the cause of the exception that has occurred in the CPU 1 is the exception factor number 1. In the case of exception factor numbers 2 to 4, the exception notification unit 20 does not send an interrupt request and does not notify an exception. The interrupt controller 11 generates an interrupt to the CPU 2 by receiving an exception notification from the exception notification unit 20. Upon receiving the interrupt, the CPU 2 executes an interrupt handler corresponding to the interrupt request from the exception notification unit 20.

  FIG. 9 is a flowchart for explaining interrupt handler processing in the CPU 2 as the second processor. When the CPU 2 starts executing the interrupt handler, in step S31, the CPU 2 acquires information on the cause of the exception held in the exception factor holding unit 31. In step S <b> 32, the CPU 2 determines whether or not the exception factor acquired in step S <b> 31 matches the factor specified in the exception factor specifying unit 50 as a factor for notifying the exception. The CPU 2 reads the information held in the exception factor specifying unit 50 through the common bus 13.

  When the exception information holding unit 30 holds information about a plurality of exceptions, refer to information about previously generated exceptions that are not specified by the exception factor specifying unit 50 there's a possibility that. In step S <b> 32, it is checked whether or not the exception factor held in the exception factor holding unit 31 is specified by the exception factor specifying unit 50. If it is determined in step S32 that they do not match, in step S37, the CPU 2 refers to information on the next exception held in the exception information holding unit 30. Further, the process returns to step S31, and information on the exception factor held in the exception factor holding unit 31 is acquired. If it is not necessary to check whether or not the exception factor held in the exception factor holding unit 31 is specified by the exception factor specifying unit 50, for example, the exception information holding unit 30 sets a single exception. If only information is retained, step S32 may be omitted.

  If the CPU 2 determines in step S32 that the exception factor acquired in step S31 matches the factor specified in the exception factor specifying unit 50 as a factor for notifying the exception, the CPU 2 determines in step S33 the exception instruction address holding unit. The address held in 32 is acquired. In step S <b> 34, the CPU 2 acquires information related to the exception status held in the exception status holding unit 33.

  Next, in step S <b> 35, the CPU 2 stores information on the exception factor acquired in step S <b> 31, the address acquired in step S <b> 33, and information on the exception status acquired in step S <b> 34 in an area on the main storage device 10. In step S <b> 36, the CPU 2 notifies the exception notification unit 20 that acquisition of information related to the state of the CPU 1 when an exception has occurred is completed. The exception notification unit 20 cancels the interrupt request to the interrupt controller 11 by receiving a notification from the CPU 2 that information acquisition has been completed.

  By making an exception notification to the CPU 2 only when the cause of the exception that has occurred in the CPU 1 is specified in the exception factor designating unit 50, it is possible to set whether or not to interrupt the CPU 2 for each cause of the exception that has occurred in the CPU 1. As a result, it is possible to efficiently acquire information related to the state of the CPU 1 when an exception occurs. Note that the multiprocessor system according to the present embodiment may further include the exception notification selection unit described in the second embodiment.

  As described above, the multiprocessor system according to the present invention is suitable for use in an information processing apparatus.

1 is a diagram illustrating a block configuration of an information processing apparatus including a multiprocessor system according to Embodiment 1. FIG. It is a figure explaining the structure of an exception information holding part. It is a flowchart explaining the process of the interrupt handler in a 2nd processor. FIG. 6 is a diagram illustrating a block configuration of an information processing apparatus including a multiprocessor system according to a second embodiment. It is a figure explaining the example which selects an interrupt request in an exception notification selection part. It is a flowchart explaining the process of the interrupt handler corresponding to the interrupt request number 7. FIG. 10 is a diagram illustrating a block configuration of an information processing apparatus including a multiprocessor system according to a third embodiment. It is a figure explaining the example which designates the factor of an exception in the exception factor designation | designated part. It is a flowchart explaining the process of the interrupt handler in a 2nd processor.

Explanation of symbols

1, 2 CPU
DESCRIPTION OF SYMBOLS 11 Interrupt controller 20 Exception notification part 30 Exception information holding part 40 Exception notification selection part 50 Exception factor designation part

Claims (6)

Multiple processors connected to a common system bus;
Exception notifying means for notifying the occurrence of an exception in the first processor of the plurality of processors to a second processor that is at least one processor other than the first processor among the plurality of processors;
An exception information holding unit that holds information about a state of the first processor when an exception occurs in the first processor;
The multi-processor system according to claim 2, wherein the second processor acquires information held in the exception information holding unit in response to a notification from the exception notification unit. The exception information holding means is
Exception factor holding means for holding information about the cause of the exception that occurred in the first processor;
Exception instruction address holding means for holding an address of an instruction in which an exception has occurred in the first processor;
2. The multiprocessor system according to claim 1, further comprising exception status holding means for holding information on the status of an exception that has occurred in the first processor. Interrupt control means for controlling interrupts to the plurality of processors;
The exception notifying unit notifies the second processor of the occurrence of an exception in the first processor by sending an interrupt request to the second processor via the interrupt control unit. The multiprocessor system according to claim 1 or 2.   4. The multiprocessor system according to claim 3, further comprising exception notification selection means for selecting the interrupt request sent from the exception notification means in accordance with a cause of an exception that has occurred in the first processor. An exception factor specifying means for specifying an exception factor;
The exception notification means notifies the second processor of the occurrence of an exception in the first processor only when the cause of the exception that has occurred in the first processor is designated by the exception factor designation means. The multiprocessor system according to claim 1, wherein the multiprocessor system is a multi-processor system. Multiple processors connected to a common system bus;
Exception notifying means for notifying the occurrence of an exception in the first processor of the plurality of processors to a second processor that is at least one processor other than the first processor among the plurality of processors;
An exception information holding unit that holds information about a state of the first processor when an exception occurs in the first processor;
The information processing apparatus, wherein the second processor acquires information held in the exception information holding unit in response to a notification from the exception notification unit.

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