JP2008077388A - Multiprocessor control system, method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To guarantee fail-soft operation without adding hardware. <P>SOLUTION: A multiprocessor control system has an OS 131 that allocates processors 11, 12 to an active system or a standby system. When the system is started, the OS 131 grants the right to execute an application to the first of the processors 11, 12 to execute processor execution right gaining process programs 132, 133, so that the processor granted the execution right is allocated to the active system, while the remaining processor not granted the right is allocated to the standby system. If an exception indication indicating that an operation failure due to the execution of the application has occurred is received from the processor of the active system after the execution of the application, the execution right is released; the execution right released is then granted to the processor of the standby system. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a control switching system in a multiprocessor environment.

  In a system in which processing based on firmware is executed under the control environment of a single processor, a failure that causes the program to stop if a problem such as a program exception of unknown cause or a TLB (Translation Look-aside buffer) exception occurs. was there. Stopping the system causes great trouble for the user.

  As a countermeasure against a program exception or a program stop failure due to TLB, there is a method of reinitializing the entire system by embedding program restart or CPU or system reset processing in the exception handler. There is also a method in which the hardware detects a program stop signal as a CPU alarm and notifies the upper management system of the alarm. However, these methods can achieve fail-safe systems (methods that minimize the degradation of processing functions and maintain overall system safety even if a failure occurs). System (a system in which basic functions continue to work even if a failure occurs and processing functions are reduced) cannot be realized.

Thus, an information processing system including a multiprocessor has been proposed (see Patent Document 1). In this information processing system, at least one processor is operated as the system support processor SSP, and the remaining processors are operated as the instruction processor IP. When an SSP failure occurs, an interrupt is generated for at least one OS operating on the IP. When the interrupt occurs, the OS detects a failure, and the IP takes over the SSP function.
Japanese Patent Laid-Open No. 9-251443

  However, in the information processing system described in Patent Document 1, since it is necessary to define the role of SSP and IP, it is difficult to apply it to an existing multiprocessor system as it is. In addition, when an SSP failure occurs, a switching means (hardware) is required to allow the SSP function to be taken over by the IP. For this reason, in order to apply to an existing multiprocessor system, it is necessary to prepare switching means (hardware), which increases the cost.

  An object of the present invention is to provide a multiprocessor control system that can guarantee fail-soft operation even when a failure such as a program exception or a TLB exception occurs without adding new hardware.

  In order to achieve the above object, a multiprocessor control system of the present invention includes a plurality of processors capable of executing an application and a memory commonly used by the plurality of processors, and the memory includes the plurality of processors. A plurality of processor execution right acquisition processing programs that are individually executed by each of the processors, and an operating system that allocates an active system and a standby system to the plurality of processors, and the operating system starts up the system Sometimes, the predetermined number of processors of the plurality of processors are made to acquire the execution right of the application in the order of execution of the processor execution right acquisition processing program, and the predetermined number of processors that have acquired the execution right are currently used The remaining programs for which execution rights were not acquired An exception indicating that an operation abnormality associated with the execution of the application has occurred from one of the active processors after the execution of the application by allocating a sessa as a standby system and causing the active processor to execute the application. When the instruction is received, the execution right acquired by the processor that sent the exception instruction is released, and the released execution right is acquired by the standby processor.

  According to the above configuration, the operating system allocates the active processor and the standby processor when the system starts, and releases the execution right of the active processor that has failed when the active processor fails. Let the standby processor acquire the execution right. When the standby processor acquires the execution right, it operates as an active processor. As described above, since the operating system switches between the active system and the standby system, it is possible to guarantee a fail-safe operation even when a program exception or a TLB exception that is difficult to analyze occurs.

  In addition, the present invention can be applied to an existing multiprocessor system only by updating / adding software such as an operating system and a processor execution right acquisition processing program, and does not require addition of new hardware.

  According to the present invention, there is an effect that a fail-soft multiprocessor control system can be constructed at low cost without changing hardware.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a multiprocessor control system according to an embodiment of the present invention. Referring to FIG. 1, a multiprocessor control system 1 is a system that supports SMP (Symmetric Mult-Processor), and includes processors 11 and 12 that execute programs, and a memory 13 that is commonly used by these processors 11 and 12. It consists of.

  The memory 13 stores programs and data. The memory 13 stores an OS (Operating system) 131 that operates on the processors 11 and 12 and processor execution right acquisition processing programs 132 and 133. The processor execution right acquisition processing program 132 is a program describing a process for the processor 11 to acquire an execution right. The processor execution right acquisition processing program 133 is a program describing a process for the processor 12 to acquire an execution right.

  The OS 131 includes an execution right counter 1311, an execution right counter semaphore 1312, exception handlers 1313 and 1314, an execution right acquisition function 1315, and an execution right release function 1316.

  The execution right counter 1311 is a counter used in the execution right acquisition process of the processor, and the initial value is a value of “number of processors−1”. Since the number of processors is two here, the initial value is “1”.

  The execution right counter semaphore 1312 is provided to prevent the execution right acquisition processing by the processor execution right acquisition processing program 132 and the execution right acquisition processing by the processor execution right acquisition processing program 133 from being executed simultaneously. Thus, either a value indicating an executable state (here “0”) or a value indicating an unexecutable state (here “1”) is set. When acquiring the execution right, the processor execution right acquisition processing programs 132 and 133 need to call the execution right acquisition function 1315 to acquire the execution right counter semaphore 1312. If the semaphore value is “0”, the semaphore can be acquired. If the semaphore value is “1”, acquisition of the semaphore fails. When the semaphore value is set to “1”, the state is maintained until the semaphore is released, and the semaphore value is set to “0” when the semaphore is released. By performing an operation using such a semaphore, it is possible to perform exclusive control on execution right acquisition processing by each processor execution right acquisition processing program.

  The execution right acquisition function 1315 is a function for performing a series of operations using the execution right counter semaphore 1312 (such as control related to acquisition and release of the semaphore and updating of the counter value of the execution right counter 1311).

  The exception handler 1313 processes a program exception or a TLB exception of the processor 11, and releases the execution right acquired by calling the execution right release function 1316 in response to an exception instruction from the processor 11. The exception handler 1314 processes a program exception and a TLB exception of the processor 12, and releases an execution right acquired by calling an execution right release function 1316 according to an exception instruction from the processor 12. The execution right release function 1316 is a function for performing a series of operations for the exception handlers 1313 and 1314 to release the execution right (such as control related to acquisition and release of the semaphore and updating of the counter value of the execution right counter 1311). is there.

  Next, the operation of the multiprocessor control system 1 of this embodiment will be described in detail.

(1) Execution Right Acquisition Process FIG. 2 shows the procedure of the processor execution right acquisition process, and FIG. 3 shows the procedure of the semaphore acquisition process performed when acquiring the execution right. The processor execution right acquisition processing by the processor execution right acquisition processing programs 132 and 133 is performed according to the procedure shown in FIG. 2, and the semaphore acquisition processing by the execution right acquisition function at that time is performed according to the procedure shown in FIG. Hereinafter, the execution right acquisition process will be described in detail with reference to FIGS. 1 to 3.

  When the system is started (power is turned on or the processor is reset), the processor execution right acquisition processing programs 132 and 133 are executed by the processors 11 and 12, respectively. Each of the processor execution right acquisition processing programs 132 and 133 calls the execution right acquisition function 1315 (step 201 in FIG. 2) and spin-locks until the execution right can be acquired (step 202 in FIG. 2).

  After the spin lock, execution right acquisition processing by the execution right acquisition function 1315 called by each of the processor execution right acquisition processing programs 132 and 133 is executed individually. Each execution right acquisition process is performed according to the following procedure shown in FIG.

  The execution right acquisition function 1315 tries to acquire the execution right counter semaphore 1312 (step 301 in FIG. 3). If acquisition of the execution right counter semaphore 1312 fails, a return value of execution right acquisition failure is set (step 307 in FIG. 3), and the process returns to the caller (transition to step 201 in FIG. 2). If acquisition of the execution right counter semaphore 1312 is successful, the value of the execution right counter 1311 is subsequently determined (step 302 in FIG. 3).

  If it is determined in step 302 that the execution right counter 1311 is greater than 0, the execution right counter 1311 is decremented by “1” (step 303 in FIG. 3), and the execution right counter semaphore 1312 is released (step in FIG. 3). 304). Thereafter, a return value indicating successful acquisition is set (step 305 in FIG. 3), and the process returns to the caller (transition to step 201 in FIG. 2). If it is determined in step 302 that the execution right counter 1311 is 0 or less, the execution right counter semaphore is released (step 306 in FIG. 3), and a return value for execution right acquisition failure is set (step 307 in FIG. 3). ), Return to the caller (transition to step 201 in FIG. 2).

  According to the semaphore acquisition process (exclusive control) by the execution right acquisition function 1315 described above, the processor 11 or 12 executes the processor execution right acquisition processing program as soon as possible to call the execution right acquisition function 1315. You can get the right.

  The processor that has successfully acquired the execution right calls the OS scheduler (step 203 in FIG. 2), and ends the execution right acquisition processing by the processor execution right acquisition processing program. Thereafter, the processor that has acquired the execution right starts the operation of the user application as the active processor. The processor that cannot acquire the execution right and is in the spin lock state (step 202 in FIG. 2) becomes a standby processor.

(2) Operation when an exception occurs After the processors 11 and 12 are assigned to the active system and the standby system, the execution right is released when an abnormality occurs in the active system processor such as a program exception or a TLB exception. Then, processing for giving the execution right to the standby processor is performed.

  FIG. 4 shows the procedure of the processor execution right release process, and FIG. 5 shows the procedure of the semaphore acquisition process performed at the time of execution right release. Among the exception handlers 1313 and 1314, the exception handler that receives an exception instruction from the active processor executes the processor execution right release process shown in FIG. 4, and the semaphore acquisition process by the execution right release function at that time is shown in FIG. It is performed according to the procedure shown in.

  In the following, the execution right releasing process when an exception occurs will be described in detail with reference to FIGS. Here, the operation when a program exception or a TLB exception occurs in the processor 11 while the system is operating with the processor 11 being the active processor and the processor 12 being the standby processor will be described.

  When a program exception or a TLB exception occurs in the processor 11, an exception handler 1313 is activated. The exception handler 1313 calls the execution right release function 1316 (step 401 in FIG. 4) and spin-locks until the execution right can be released (step 402 in FIG. 4).

  The execution right release function 1316 attempts to acquire the execution right counter semaphore 1312 (step 501 in FIG. 5). If acquisition of the execution right counter semaphore 1312 fails, a return value of execution right release failure is set (step 507 in FIG. 5), and the process returns to the caller (transition to step 401 in FIG. 4). If acquisition of the execution right counter semaphore 1312 is successful, the value of the execution right counter 1311 is determined (step 502 in FIG. 5).

  If it is determined in step 502 that the execution right counter 1311 is equal to or less than the value of [(number of processors) −2], the execution right counter 1311 is incremented by “1” (step 503 in FIG. 5), and the execution right counter is counted. The semaphore 1312 is released (step 504 in FIG. 5). Then, a return value indicating successful release is set (step 505 in FIG. 5), and the process returns to the caller (transition to step 401 in FIG. 4).

  If it is determined in step 502 that the execution right counter 1311 is larger than the value of [(number of processors) −2], the execution right counter semaphore is released (step 506 in FIG. 5). Then, a return value of execution right release failure is set (step 507 in FIG. 5), and the process returns to the caller (transition to step 401 in FIG. 4).

  The exception handler 1313 that has been able to release the execution right calls the processor execution right acquisition process 132 (step 403 in FIG. 4), and ends the execution right release process.

  At the end of the execution right releasing process, the processor 12 as the standby processor is in the spin lock state (step 202 in FIG. 2). Since the execution right counter 1311 becomes a value larger than 0 (= 1) by the execution right release process due to the occurrence of an exception, the processor 12 can acquire the execution right. The processor 12 that has acquired the execution right becomes the active processor and starts the operation of the user application. On the other hand, the processor 11 executes the processor execution right acquisition processing program 132 in step 403 in FIG. 4, but enters the spin lock state in step 202 in FIG. For this reason, the processor 11 operating as the active processor becomes a standby processor after the exception occurs.

  According to the multiprocessor control system 1 of the present embodiment described above, the OS 131 allocates processors to the active system and the standby system in the order in which the execution rights are acquired when the system is started, and program exceptions and TLBs that are difficult to analyze in the active system. When a failure such as an exception occurs, the execution right of the active system in which the failure has occurred is released and assigned to the standby system. Thereby, it is possible to guarantee a fail-safe operation.

  In addition, the present invention can be applied to an existing multiprocessor system only by updating / adding software such as an OS and a processor execution right acquisition processing program, and it is not necessary to add new hardware.

  In the multiprocessor control system of the present embodiment, the number of processors is not limited. It can be applied in a multi-configuration with three or more processors. When applied to three or more multi-configurations, an execution right acquisition processing program and an exception handler are provided for each processor.

(Other embodiments)
FIG. 6 is a book diagram showing a configuration of a multiprocessor control system according to another embodiment of the present invention.

  Referring to FIG. 6, the multiprocessor control system 2 includes three processors 21 to 23 and a memory 24 commonly used by these processors. The memory 24 has an OS 241, initialization tasks 242 to 244, and user tasks 245 to 248. The initialization task 242 has a processor execution right acquisition processing program 2421 executed by the processor 21. The initialization task 243 has a processor execution right acquisition processing program 2431 executed by the processor 22. The initialization task 244 has a processor execution right acquisition processing program 2441 executed by the processor 23.

  The OS 241 includes an execution right counter 2411, an execution right counter semaphore 2412, exception handlers 2413 to 2415, an execution right acquisition function 2416, and an execution right release function 2417. Each of the exception handlers 2413, 2414, and 2415 processes a program exception or a TLB exception in response to an exception instruction from the processor 21, 22, or 23, and acquires the execution right acquired by calling the execution right release function 1316. To release.

  6, processor execution right acquisition processing programs 2421, 2431, and 2441, an execution right counter 2411, an execution right counter semaphore 2412, exception handlers 2413 to 2415, an execution right acquisition function 2416, and an execution right release function 2417 are shown in FIG. It corresponds to the processor execution right acquisition processing program, execution right counter, execution right counter semaphore, exception handler, execution right acquisition function and execution right release function shown. Since the number of processors is 3, the initial value of the execution right counter 2411 is “2”. The initialization tasks 242, 243, 244 and user tasks 245, 246, 247, 248 operate under the management of the OS 241.

  In the multiprocessor control system 2 of the present embodiment, the processors 21, 22, and 23 execute initialization tasks 242, 243, and 244, respectively, when the system is activated. The initialization tasks 242, 243, and 244 call processor execution right acquisition processes 2421, 2431, and 2441, respectively. The processor execution right acquisition processing 2421, 2431, 2441 calls the execution right acquisition function 2416 (step 201 in FIG. 2) and spin-locks until the execution right can be acquired (step 202 in FIG. 2).

  Here, it is assumed that the execution right acquisition function 2416 is called in the order of the processor 21, the processor 22, and the processor 23.

  The execution right acquisition function 2416 called by the processor execution right acquisition processing program 2421 attempts to acquire the execution right counter semaphore 2412 (step 301 in FIG. 3). If acquisition of the semaphore is successful, the execution right acquisition function 2416 determines the value of the execution right counter 2411 (step 302 in FIG. 3). At this time, since the value of the execution right counter 2411 is “2”, the execution right acquisition function 2416 decrements the value of the execution right counter 2411 by “1” (step 303 in FIG. 3). The counter semaphore 2412 is released (step 304 in FIG. 3), a return value indicating successful acquisition is set (step 305 in FIG. 3), and the process returns to the processor execution right acquisition process.

  The execution right acquisition function 2416 called by the processor execution right acquisition processing program 2431 attempts to acquire the execution right counter semaphore 2412 (step 301 in FIG. 3). If acquisition of the semaphore is successful, the execution right acquisition function 2416 determines the value of the execution right counter 2411 (step 302 in FIG. 3). At this time, since the value of the execution right counter 2411 is “1”, the execution right acquisition function 2416 decrements the execution right counter 2411 by “1” (step 303 in FIG. 3), and executes the execution right counter semaphore. 2412 is released (step 304 in FIG. 3), a return value indicating successful acquisition is set (step 305 in FIG. 3), and the process returns to the processor execution right acquisition process.

  The execution right acquisition function 2416 called by the processor execution right acquisition process 2441 attempts to acquire the execution right counter semaphore 2412 (step 301 in FIG. 3). If acquisition of the semaphore is successful, the execution right acquisition function 2416 determines the value of the execution right counter 2411 (step 302 in FIG. 3). At this time, since the execution right counter 2411 is “0”, the execution right acquisition function 2416 releases the execution right counter semaphore 2412 (step 306 in FIG. 3) and sets a return value of execution right acquisition failure. (Step 307 in FIG. 3), the process returns to the processor execution right acquisition process.

  Through the above series of operations, the processor 21 and the processor 22 can acquire the execution right. The processors 21 and 22 that have successfully acquired the execution right call the scheduler of the OS 241 (step 203 in FIG. 2), and end the execution right acquisition process. The processors 21 and 22 that have acquired the execution right start the operation of the user task as the active processor. The processor 23 in a spin-locked state (step 202 in FIG. 2) that cannot acquire the execution right becomes a standby processor.

  Next, the operation when an exception occurs will be described.

  When the processors 21 and 22 are used as active systems and the processor 23 is used as a standby system, if an abnormality occurs in the active system processor such as a program exception or a TLB exception, the execution right is released, Processing for giving execution rights to the standby processor is performed. Here, it is assumed that the OS 241 assigns execution of the user task 245 and user task 246 to the processor 21 and assigns execution of the user task 247 and user task 248 to the processor 22. The operation when it occurs will be described.

  If a program exception or a TLB exception occurs during execution of the user task 245 in the processor 21, an exception handler 2413 is activated. The exception handler 2413 calls the execution right release function 2417 (step 401 in FIG. 4) and spin-locks until the execution right can be released (step 402 in FIG. 4).

  The execution right release function 2417 attempts to acquire the execution right counter semaphore 2412 (step 501 in FIG. 5). When acquisition of the semaphore is successful, the execution right release function 2417 determines the value of the execution right counter 2411 (step 502 in FIG. 5). At this time, since the value of the execution right counter 2411 is “0”, the condition equal to or smaller than the value of [number of processors−2] (= 1) is satisfied. Accordingly, the execution right release function 2417 increments the execution right counter 2411 by “1” (step 503 in FIG. 5), releases the execution right counter semaphore 2412 (step 504 in FIG. 5), and returns the return value of successful release. The setting is made (step 505 in FIG. 5), and the process returns to the exception processing (step 401 in FIG. 4).

  The exception handler 2413 that has been able to release the execution right calls the initialization task 242 (step 403 in FIG. 4), and ends the execution right release process.

  At the end of the execution right releasing process, the processor 23 as the standby processor is in the spin lock state (step 202 in FIG. 2). Since the execution right counter 1311 becomes a value larger than 0 (= 1) by the execution right release process due to the occurrence of an exception, the processor 23 can acquire the execution right. The processor 23 that has acquired the execution right becomes the active processor and resumes the operations of the user tasks 245 and 246. On the other hand, the processor 21 executes the processor execution right acquisition processing program 2421 in step 403 in FIG. 4, but enters the spin lock state in step 202 in FIG. For this reason, the processor 21 operating as the active processor becomes a standby processor after the exception occurs.

It is a block diagram which shows the structure of the multiprocessor control system which is one Embodiment of this invention. It is a flowchart which shows the procedure of a processor execution right acquisition process. It is a flowchart which shows the procedure of the semaphore acquisition process performed at the time of execution right acquisition. It is a flowchart which shows the procedure of a processor execution right release process. It is a flowchart which shows the procedure of the semaphore acquisition process performed at the time of execution right release. It is a book figure which shows the structure of the multiprocessor control system which is other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Multiprocessor control system 11, 12 Processor 13 Memory 131 Operating system 132, 133 Processor execution right acquisition processing program 1311 Execution right counter 1312 Execution right counter semaphore 1313, 1314 Exception handler 1315 Execution right acquisition function 1316 Execution right release function

Claims (5)

Multiple processors capable of running applications,
A memory used in common by the plurality of processors,
The memory is
A plurality of processor execution right acquisition processing programs executed individually by each of the plurality of processors;
An operating system that allocates a working system and a standby system to the plurality of processors;
The operating system is
The predetermined number of processors that have acquired the execution right to the predetermined number of processors among the plurality of processors in the order in which the processor execution right acquisition processing program has been executed and acquired the right to execute the application. Is assigned to the active system, the remaining processors for which execution rights have not been acquired are allocated as the standby system, and the active system processor executes the application.
After execution of the application, upon receiving an exception instruction from one of the active processors indicating that an abnormal operation has occurred, the execution right acquired by the processor that sent the exception instruction is released. A multiprocessor control system characterized in that the released execution right is acquired by the standby processor. The operating system is
An execution right acquisition function for acquiring the execution right of the application;
An execution right counter in which a value obtained by subtracting 1 from the number of the plurality of processors is set as an initial value;
An execution right counter semaphore that is in a semaphore acquisition disabled state during execution of the execution right acquisition process by the execution right acquisition function, and is in a semaphore acquisition enabled state except during the execution of the acquisition process,
Each of the plurality of processor execution right acquisition processing programs executes the process for acquiring the execution right by calling the execution right acquisition function,
The called execution right acquisition function corresponds to the fact that the execution right has been acquired only when the state of the execution right counter semaphore is in the semaphore acquisition enabled state and the value of the execution right counter is greater than zero. The multiprocessor control system according to claim 1, wherein the multiprocessor control system transmits to the processor and decrements the value of the execution right counter by one. The operating system is
An execution right release function for releasing the acquired execution right;
A plurality of exception handlers individually used by each of the plurality of processors;
Each of the plurality of exception handlers, upon receiving the exception instruction from a corresponding processor, calls the execution right release function to execute a process for releasing the acquired execution right,
The called execution right release function is used when the state of the execution right counter semaphore is in the semaphore acquisition enabled state and the value of the execution right counter is equal to or less than a value obtained by subtracting 2 from the number of the plurality of processors. 3. The multiprocessor control system according to claim 2, wherein only when the acquired execution right is released to the corresponding processor, the value of the execution right counter is incremented by one. A multiprocessor control method performed in a system having a plurality of processors capable of executing an application and a memory commonly used by the plurality of processors,
Each of the plurality of processors individually executing a processor execution right acquisition processing program;
The operating system acquires the execution right of the application in the order in which the processor execution right acquisition processing program is executed with respect to a predetermined number of processors among the plurality of processors at the time of system startup, and acquires the execution right. Allocating a predetermined number of processors as the active system, allocating the remaining processors for which execution rights have not been acquired as a standby system, and causing the active processor to execute the application; and
After the execution of the application, when the operating system receives an exception instruction from the active processor indicating that an operation abnormality has occurred due to the execution of the application, the processor that sent the exception instruction acquires Releasing the execution right, and causing the spare processor to acquire the released execution right. A program used in a computer system having a plurality of processors capable of executing an application and a memory commonly used by the plurality of processors,
When starting up the system, each of the plurality of processors individually executes a processor execution right acquisition process,
The execution right of the application is acquired in the order in which processor execution right acquisition processing is executed for a predetermined number of processors of the plurality of processors,
The predetermined number of processors that have acquired the execution right are used as active systems, the remaining processors for which execution rights have not been acquired are allocated as standby systems, and the active system processors execute the application,
After execution of the application, upon receiving an exception instruction from one of the active processors indicating that an operation abnormality has occurred due to execution of the application, the execution right acquired by the processor that sent the exception instruction is released. A program for causing the reserve processor to acquire the released execution right.

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