JPH08149049A - Synchronous circuit - Google Patents

Abstract

PURPOSE: To establish the synchronization of spectrum diffusion signals in a short period for a synchronous circuit of a receiving device that applies a spectrum diffusion modulation system. CONSTITUTION: A maximum value detecting circuit 4 detects the maximum value in a cycle of the correlation output of a correlation detector 2. Then a synchronization control circuit 7 generates an operation command signal 108 if the synchronization is secured after a cycle. The phase information 104, i.e., the time information obtained when the maximum value is detected is set as the initial load value of a counter of a PN phase control circuit 6 in response to the signal 108. Then a diffusion signal generator 5 generates the initial value of a local diffusion signal 106, i.e., a PN pattern based on the initial load value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit, and more particularly to a synchronizing circuit of a demodulation section used in a spread spectrum multiple access type receiver in the field of wireless communication.

[0002]

2. Description of the Related Art Conventionally, an example of this type of synchronizing circuit is disclosed in Japanese Patent Application Laid-Open No. 3-192837, and its configuration is shown in FIG.

As shown in FIG. 3, the conventional circuit has a correlation detector 2 for detecting a correlation between a spread spectrum signal 101 which is an input signal of an input terminal 1 and a local spread signal 106.
And a spread signal generator 5 for generating a local spread signal 106.
, A clock generator 8 for supplying a clock to the spread signal generator 5, and a clock generator 8 for receiving the output of the correlation detector 2.
A maximum value detection circuit 4 that detects the maximum correlation value in one cycle of the spread signal by controlling the phase of the spread signal; a synchronization determination circuit 3 that receives the signal from the correlation detector 2 and performs synchronization determination in the maximum correlation value; The synchronization control circuit 7 receives the synchronization determination signal 107 from the determination circuit 3 and controls the maximum value detection circuit 4 to detect the maximum correlation value again only once.

Next, the operation will be described with reference to FIG. The spread spectrum input signal 101 becomes the output 102 of the correlation detector 2. In FIG. 4, a section M1 is a period during which the maximum value is detected, and an input signal comes in from φ1 in the middle. In this case, the phase at the maximum correlation value is φ
The synchronization determination is performed with max1. As a result of the synchronization determination, when the synchronization determination circuit 3 determines the synchronization state, the synchronization determination signal 107
Is output, the synchronous control circuit 7 outputs the operation command signal 108 to detect the maximum value again, and operates the maximum value detection circuit 4 only once. The section M2 in FIG. 4 is the portion where the maximum value is detected, and since the input signal is input from the beginning, the phase φmax2 of the maximum correlation value obtained here can obtain a correct synchronization state.

[0005]

In the conventional circuit,
The maximum correlation value φma in the section M2 of FIG.
Assuming that the signal starts just after φmax3 (point A) of the section M1 that responds to x2, the maximum correlation value φ of the repetition cycle M of FIG. The synchronization determination is performed over a total of about D + redetection cycles, which is about two cycles.

An object of the present invention is to provide a synchronization circuit capable of reliably performing PN (Pseudo Noise) synchronization as an initial operation in one cycle of the spread code.

[0007]

A synchronizing circuit according to the present invention comprises a spread signal generating means for generating a local spread signal and a correlation detecting means for receiving the input spread spectrum signal and detecting a correlation value with the local spread signal. A maximum value detecting means for detecting a maximum value of the correlation value in a period equal to one cycle of the local spread signal, a synchronization determining means for determining a synchronization of the maximum value detection output, and a maximum receiving the synchronization determination output. A synchronization control means for controlling the value detection cycle; and a phase control means for receiving the phase information when the maximum value is detected by the maximum value detection means and controlling the generation phase of the local spread signal of the spread signal generation means. I am trying.

[0008]

The synchronization judgment is made at the timing when the maximum value of the correlation value between the local spread signal and the input spread spectrum signal is detected, and the phase information corresponding to this maximum correlation value is used as the initial load signal in the counter in the PN phase control circuit. The initial value of the PN pattern, which is a locally spread signal, is determined.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a position embodiment of the present invention, and the same parts as those in FIG. 3 are designated by the same reference numerals.

The synchronous circuit of this embodiment comprises a correlation detector 2 for detecting the correlation value between the spread spectrum signal input from the input terminal 1 and the output of the spread signal generator 5, and the output of the correlation detector 2. A maximum value detection circuit 4 for detecting the maximum value of
Synchronization determination circuit 3 for determining the synchronization of the output of the maximum value detection circuit 4
A synchronization control circuit 7 that receives the output of the synchronization determination circuit 3 and determines a maximum value detection cycle; and a PN phase control circuit 6 that receives phase information from the maximum value detection circuit 4 and controls the spread signal generator 5. Have

The spread signal generator 5 is, for example, a ROM (read only memory) in which a PN pattern is stored in advance, and P
The N-phase control circuit 6 has a counter for determining the address of this ROM. This counter is the maximum value detection circuit 4
The phase information corresponding to the timing when the maximum correlation value is detected is acquired as an initial load value, and the PN cycle is counted while counting up or down in 1-bit units from this initial load value.

FIG. 2 is a diagram showing the operation of the block shown in FIG. 1, and the threshold value shown in FIG. 2 is a level indicating the discrimination between the correlation output of only noise and the correlation output when there is a spread spectrum signal. The operation will be described below.

Spread spectrum signal 01 from input terminal 1
Is input and the local spread signal 10 from the spread signal generator 5 is input.
6 becomes an input to the correlation detector 2, and the correlation value of these two inputs becomes an output 102. This output 102 is input to the maximum value detection circuit 4 to obtain the maximum correlation value. When a slight correlation appears in the output 102 of the correlation detector 2, the maximum value detection circuit 4 gives the PN phase control circuit 6 a spreading cycle start trigger and P
The N phase control circuit 6 starts counting the PN cycle T. P
The N phase control circuit 6 sends an address 105, which is the count information of the PN cycle, to the spread signal generator 5 and shifts the phase for each bit, and after one cycle elapses, the maximum value detection circuit 4 synchronizes the detected maximum value signal 103. It is sent to the judgment circuit 3.

In the conventional circuit of FIG. 3, the synchronization determination controls the clock generator 8 and the spread signal generator 5 so that the phase φmax2 at the time when the maximum correlation value is detected is obtained, and the output of the correlation detector 2 is controlled. However, in the present invention, the maximum value signal 103 which is the output of the maximum value detection circuit 4 is used in order to simplify the configuration.

The synchronization determination circuit 3 determines whether or not the maximum value signal 103 has established synchronization, and if it is determined that synchronization has been established, the synchronization determination signal 1
07 is "synchronous". At this time, the synchronization control circuit 7 counts the time corresponding to one cycle T from the time t1.
The operation command signal 108 is generated at the time t2 immediately after the synchronization determination signal 107 becomes "synchronous", and the maximum value detection cycle of the maximum value detection circuit 4 is determined to be one cycle T. There is.

When the end t2 of this one cycle T is reached and the operation command signal 108 is generated, the maximum value detection circuit 4 instructs the PN phase control circuit 6 to bring the maximum correlation phase φmax to PN.
Phase information (φmax), which is time information when the maximum correlation value is detected, is sent from the phase control circuit 6 to the spread signal generator 5 as the address signal 105, and synchronization is established.

If the input is started at t1 on the time axis, 1
When the maximum correlation phase φmax is obtained during the period T, the time t2
Then, the correlation detection is completed, and the PN phase is synchronized after t2. Here, the maximum value that does not exceed the reference value for PN synchronization is rejected and the maximum value detection starts again.

If the synchronization determination signal 107 indicates "not synchronized" under the condition that the C / N is bad, the synchronization control circuit 7 is operated and the operation command signal 108 is used to detect the correlation for one cycle again.

[0020]

As described above, according to the present invention, there is an effect that the received spread spectrum signal is reliably PN-synchronized as an initial operation in one cycle of the spread code.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a diagram illustrating an operation of a block in FIG.

FIG. 3 is a block diagram of a conventional synchronizing circuit.

FIG. 4 is a diagram for explaining the operation of the conventional circuit of FIG.

FIG. 5 is a diagram showing an output example of a correlation detector.

[Explanation of symbols]

 2 Correlation detector 3 Synchronization determination circuit 4 Maximum value detection circuit 5 Spreading signal generator 6 PN phase control circuit 7 Synchronization control circuit

Claims (3)

[Claims] 1. A spread signal generating means for generating a local spread signal, a correlation detecting means for receiving a correlation value between the input spread spectrum signal and the local spread signal, and one of the local spread signals having the correlation value. A maximum value detection means for detecting a maximum value in a period equal to the cycle, a synchronization determination means for performing a synchronization determination of the maximum value detection output, a synchronization control means for receiving the synchronization determination output and controlling the maximum value detection cycle, And a phase control means for receiving the phase information when the maximum value is detected by the maximum value detecting means and controlling the generation phase of the local spread signal of the spread signal generating means. 2. The spread signal generating means is a read-only memory, and the phase control means sets an initial address of the read-only memory according to phase control information when the maximum value is detected by the maximum value detecting means. The synchronizing circuit according to claim 1, wherein the synchronizing circuit is configured as follows. 3. The synchronizing circuit according to claim 2, wherein the phase control means is composed of a counter which is loaded with an initial address according to the phase control information.