JPH08148992A - Counter test method and its device - Google Patents

Abstract

PURPOSE: To reduce number of test pins in the case of testing plural counters by discriminating the coincidence of all common bit outputs of the plural counters and configuring discrimination of even/odd number of 1s in a most frequent bit output in the plural counters. CONSTITUTION: The device is provided with a selector 107 selecting an input clock for plural counters 108-111 or a test clock, a circuit 116 discriminating the coincidence of all common bit outputs of the counters 108-111, and a circuit 118 discriminating the odd/even parity of number of 1s in an output of the most frequent bit counter 11 among the counters 108-111. Through the constitution above, the coincidence of all common bit outputs of the counters 108-111 is discriminated by an output 117 of the test pin and the even odd parity of number of 1s in the output of the most frequent bits in the counters 108-111 is discriminated by an output 119 of the test pin. Thus, the outputs 17, 119 of the two points are detected to detect whether or not the counters 108-111 are in normal operation.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to testing counters.

[0002]

2. Description of the Related Art Due to recent advances in LSI manufacturing technology, LSI
It has become possible to mount circuits with many functions inside. On the other hand, in order to detect whether the internal circuit is operating normally during the test, many terminals (hereinafter, test pins) for extracting the detection result to the outside are required. One of the circuits having many functions inside the LSI has a counter, and a plurality of test pins are necessary to detect whether the plurality of counters are operating normally.

A conventional method of testing a plurality of counters will be described below. In FIG. 3, 306 is a reset signal, 308 and 309 are 3-bit counters, 310 is a 4-bit counter, and 311 is a 5-bit counter. 307 is a selector, 304 is a select signal, and 305 is a test clock. 300 is a counter 30
8 is an input clock during normal operation. Similarly, 301,
302 and 303 are counters 309, 310 and 3, respectively.
11 is an input clock during normal operation of 300,
03a are input clocks of the counters 308 to 311 selected by the selector 307, respectively. 312-31
Reference numeral 5 is the most significant bit output of the counters 308 to 311 which is the output of the test pin.

The operation will be described below. First,
In the test, the selector 307 switches the input clocks 300 to 303 of the counters 308 to 311 in the normal operation to the test clock 305 by the select signal 304.
The input clocks 300a to 303a of the counter become the test clock 305. Next, the reset signal 306 is used to clear all bits of the counters 308 to 311 to 0, and the test clock 305 is input with a clock of 2 to the 5th power. If the counters 308 to 311 are operating normally, the counters 308 and 309 are the fourth, twelfth, twentieth, and twenty-eighth test clocks 305 from the time of resetting until the end of inputting the test clock 305. , 1 is output to the test pin outputs 312 and 313 as the most significant bit output, and the test clock 305 is the 8th, 16th, and 24th clocks.
On the 32nd and the 32nd shots, the test pin outputs 312 and 313 are 0
Return to The test clock 305 of the counter 310 is 8
The 1st is output to the output 314 of the test pin as the most significant bit output at the 24th and the 24th, and the output 314 of the test pin returns to 0 at the 16th and the 32nd of the test clock 305. The counter 311 outputs the test pin 3 at the 16th generation of the test clock 305 and outputs the most significant bit of the counter 311.
1 is output to 15, and the test pin output 315 returns to 0 at the 32nd time of the test clock 305. If one bit of the counters 308 to 311 is faulty, the test pin outputs 312 to 3 are the most significant bit outputs of the counters 308 to 311 with respect to the test clock 305.
The value in the normal operation described above is not output to 15 and a failure of the counter is detected.

[0005]

However, in the above-described conventional configuration, one test pin is required for one counter, and therefore, in order to detect whether a plurality of counters are operating normally, There is a problem that the test pins for the number are required.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a test method for reducing the number of test pins when testing a plurality of counters.

[0007]

In order to achieve this object, a counter test method of the present invention has a plurality of counters as a first means and a selector for selecting an input clock and a test clock. The configuration is such that the coincidence of all common bit outputs of the individual counters is determined, and the evenness of the number of 1s of the highest bit output among the plurality of counters is determined.

Next, as a second means, a configuration is provided which has a plurality of counters and a selector for selecting an input clock and a test clock, and determines the evenness of the number 1 of the outputs of the plurality of counters. Have

[0009]

With the configuration of the first means, if the input clock is selected as the test clock and the clocks are input to the counter with the most bits by the multiplication of 2 bits, all the common bits of the plurality of counters can be obtained. The output of the circuit that determines whether the outputs are in agreement detects whether the counter is operating normally, and the output of the circuit that determines the evenness of the number of 1s in the most bits output is It can detect whether the upper bits of the counter are operating normally.
Further, the circuit for judging the coincidence cannot detect the output of the circuit for judging the coincidence because the failure can be detected even when the outputs of the plurality of counters are fixed to 1 or 0. It is possible to detect whether or not a plurality of counters are operating normally by using two test pins of the output of the circuit for determining the evenness of the number of 1 of the most bit output.

Next, with the configuration of the second means, if the input clock is selected as the test clock and the clock is input to the counter having the most bits by the multiplication of 2 bits, the outputs of the plurality of counters are output. It is possible to detect whether or not a plurality of counters are operating normally with one test pin of the output of the circuit for determining the evenness of the number 1.

[0011]

【Example】

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 106 is a reset signal, 1
Reference numerals 08 and 109 are 3-bit counters, 110 is a 4-bit counter, and 111 is a 5-bit counter. 10
7 is a selector, 104 is a select signal, and 105 is a test clock. Reference numeral 100 is an input clock during normal operation of the counter 108. Similarly, 101, 102,
Reference numeral 103 is an input clock at the time of normal operation of the counters 109, 110 and 111, respectively, and is 100a to 103a.
Are the counters 108 selected by the respective sectors 107.
~ 111 input clocks. Reference numerals 112 to 115 are outputs of the lower 3 bits of the counters 108 to 111, respectively. Further, 114b is the most significant bit output of the counter 110, and 115b and 115c are the four bits of the counter 111, respectively.
It is the output of the bit and the most significant bit. Reference numeral 116 denotes a circuit that determines whether all common bit outputs of the counters 108 to 111 match, when the lower 3 bits of the outputs 112 to 115 of the counters 108 to 111 match and the fourth bit of each of the counters 110 and 111. Output 11
The output 117 of the test pin becomes 1 at the output of the circuit 116 only when 4b and 115b match. Reference numeral 118 denotes a circuit for determining whether the number of 1s having the highest number of bits is even or odd.
When the number of 1's of 11 outputs is odd, the output of the circuit 118 becomes 1 as the output of the test pin 119.

The operation of the first embodiment will be described below. First, the selector 1 is selected by the select signal 104 during the test.
07, the input clocks 100 to 103 in the normal operation of the counters 108 to 111 are changed to the test clock 1
05, the input clock 100a ~ 1 of the counter
03a is the test clock 105. Next, the reset signal 106 clears all the bits of the counters 108 to 111 to 0, and the test clock 105 is input with a clock of 2 to the 5th power. If the counters 108 to 111 are operating normally, the circuit 116 always outputs 1 from the time of resetting until the input of the test clock 105 is completed, and 1 is output to the output 117 of the test pin. Also, the output of the circuit 118 from the time of resetting until the end of inputting the test clock 105 is the outputs 115, 115b, 11 of the counter 111 at the positions shown in (Table 1) with respect to the test clock 105.
The number of 1s in 5c becomes an odd number, and 1 is output to the output 119 of the test pin. If one bit of the counters 108 to 111 is faulty, a fault other than the most significant bit of the counter 111 is detected because the output of the circuit 116 is 0 and the output 117 of the test pin is 0, and the fault of the counter 111 is detected. When the higher-order bit has failed, the output of the circuit 118 is output from the counter 118 until the input of the test clock 105 is finished, the outputs 115, 115b of the counter 111 at the positions shown in (Table 1) with respect to the test clock 105, 115c
The number of 1's in the test pin is not an odd number and 0 is output to the output 119 of the test pin.
Is output and the failure is detected. In the case of a failure in which the counter outputs of 108 to 111 are fixed to 1 or 0, the circuit 11
The output of 6 is 1 and the output 117 of the test pin becomes 1 and no fault is detected.
Until the end of inputting, the output of the determination circuit 118 does not become an odd number of 1s of the output of the counter 111 with respect to the test clock 105 at the position shown in (Table 1), and 0 is output to the output 119 of the test pin. Output and failure detected.

Table 1 shows the output of the counter 111 with respect to the test clock 105 according to the first embodiment and the position where 1 is output to the output 119.

[0015]

[Table 1]

As described above, according to the first embodiment, the selector 107 for selecting the input clock and the test clock of the plurality of counters, and the circuit 116 for judging the coincidence of all common bit outputs of the plurality of counters. Of the plurality of counters, by providing the circuit 118 for determining the evenness of the number 1 of the most-bit counter output, whether or not the counters 108 to 111 are operating normally by detecting two test pins. Can be detected.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, 2
Reference numeral 06 is a reset signal, 208 and 209 are 3-bit counters, 210 is a 4-bit counter, and 211 is a 5-bit counter. 207 is a selector,
Reference numeral 204 is a select signal and 205 is a test clock. Reference numeral 200 is an input clock during normal operation of the counter 208. Similarly, 201, 202, and 203 are input clocks during normal operation of the counters 209, 210, and 211, respectively, and 200a to 203a are input clocks of the counters 208 to 211 selected by the selector 207, respectively. 212 to 215 are counters 208
~ 211 outputs. 216 is a counter 208 to 21
In the circuit for determining the evenness of the number of 1s of the output of 1, the output of the circuit 216 is the output of the test pin 217 when the number of the outputs 212 to 215 of the counters 208 to 211 is odd.
Is output to 1.

The operation of the second embodiment will be described below. First, the selector 2 is selected by the select signal 204 during the test.
07, the input clocks 200 to 203 in the normal operation of the counters 208 to 211 are changed to the test clock 2 respectively.
05, the input clock 200a ~ 2 of the counter
03a is the test clock 205. Next, the reset signal 213 resets all bits of the counters 208 to 211 to 0.
Then, the test clock 205 is input with a clock of 2 to the 5th power. If the counters 208 to 211 are operating normally, from the time of resetting until the end of inputting the test clock 205, the test clock 205 (Table 2)
At the position indicated by, the number of 1s of the outputs of the counters 208 to 211 becomes an odd number, and the output of the circuit 216 outputs 1 to the output 217 of the test pin. For example, the counters 208 to 211
If even one bit is faulty in the counter, the output of the circuit 216 with respect to the test clock 205 from the time of resetting until the end of inputting the test clock 205 of the counters 208 to 211 at the position shown in (Table 2). The number of 1s in the output does not become an odd number, and 0 is output to the output 217 of the test pin to detect the failure.

The outputs of the counters 208 to 211 and the output 217 are 1 for the test clock 205 according to the second embodiment.
The position at which is output is shown in (Table 2).

[0020]

[Table 2]

As described above, according to the second embodiment, the selector 207 for selecting the input clock and the test clock of the plurality of counters, and the circuit for determining the evenness of the number 1 of the outputs of the plurality of counters. By providing 216, 1
Counter 208 to 21 by detecting one test pin
It is possible to detect whether 1 is operating normally.

[0022]

As described above, according to the present invention, it is possible to detect a failure of a plurality of counters with one or two test pins at the time of test, and it is possible to reduce the number of terminals for taking out the detection result to the outside.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a first embodiment of a counter test method of the present invention.

FIG. 2 is a diagram for explaining a second embodiment of the counter test method of the present invention.

FIG. 3 is a diagram for explaining a conventional counter test method.

[Explanation of symbols]

100 Input signal during normal operation 100a Output signal of 107 (selected counter 10
8 input clock) 101 input clock during normal operation 101a 107 output signal (selected counter 10
9 input clock) 102 input signal during normal operation 102a 107 output signal (selected counter 11
0 input clock) 103 input clock during normal operation 103a 107 output signal (selected counter 11
1 input clock) 104 select signal 105 test clock 106 reset signal 107 selector 108 3-bit counter 109 3-bit counter 110 4-bit counter 111 5-bit counter 112 output signal of counter 108 (3 bits) 113 output signal of counter 109 (3 114) Output signal of counter 110 (lower 3 bits) 114b Output signal of counter 110 (most significant bit) 115 Output signal of counter 111 (lower 3 bits) 115b Output signal of counter 111 (lower 4th bit) 115c Counter 111 Output signal (most significant bit) 116 circuit for judging output match 117 output signal of circuit 116 (test pin output) 118 circuit for judging odd / even number of 1 119 output signal of circuit 118 (test Down Output) 200 output signal during normal operation of the input clock 200a 207 (selected counter 20
8 input clock) 201 input clock 201a 207 output signal during normal operation (selected counter 20
9 input clock) 202 input clock during normal operation 202a 207 output signal (selected counter 21
0 input clock) 203 input clock during normal operation 203a 207 output signal (selected counter 21
1 input clock) 204 select signal 205 test clock 206 reset signal 207 selector 208 3-bit counter 209 3-bit counter 210 4-bit counter 211 5-bit counter 212 counter 208 output signal (3 bits) 213 counter 209 output signal (3 214) Output signal of the counter 210 (4 bits) 215 Output signal of the counter 211 (5 bits) 216 Circuit for determining whether the number of 1's is even or odd 217 Output signal of the circuit 216 (test pin output) 300 Input during normal operation Output signal of clock 300a 307 (selected counter 30
8 input clock) 301 input clock during normal operation 301a 307 output signal (selected counter 30
9 input clock) 302 input clock during normal operation 302a 307 output signal (selected counter 31
0 input clock) 303 input clock during normal operation 303a 307 output signal (selected counter 31
1 input clock) 304 select signal 305 test clock 306 reset signal 307 selector 308 3 bit counter 309 3 bit counter 310 4 bit counter 311 5 bit counter 312 the most significant bit output signal of counter 308 (test pin output) 313 of counter 309 Most significant bit output signal (test pin output) 314 Most significant bit output signal of counter 310 (test pin output) 315 Most significant bit output signal of counter 311 (test pin output)

Claims (4)

[Claims] 1. A plurality of counters, and a selector for selecting an input clock and a test clock of the plurality of counters, determining whether all common bit outputs of the plurality of counters match, Of the counters
A counter test method characterized by determining whether the number of 1s in the output of the most bit counter is even or odd. 2. A method comprising: a plurality of counters; and a selector for selecting an input clock and a test clock of the plurality of counters, and determining the evenness of the number 1 of the outputs of the plurality of counters. Counter test method characterized by. 3. A plurality of counters, a selector for selecting an input clock and a test clock of the plurality of counters, a circuit for judging the coincidence of all common bit outputs of the plurality of counters, and the plurality of counters. A counter test apparatus having a circuit for determining whether the number of 1's of the most-bit counter output is even or odd. 4. A plurality of counters, a selector for selecting an input clock and a test clock of the plurality of counters, and a circuit for judging whether the number of outputs of the plurality of counters is even or odd. Counter test equipment characterized by.