JPH08148518A - Semiconductor device and production thereof - Google Patents
Semiconductor device and production thereofInfo
- Publication number
- JPH08148518A JPH08148518A JP7214833A JP21483395A JPH08148518A JP H08148518 A JPH08148518 A JP H08148518A JP 7214833 A JP7214833 A JP 7214833A JP 21483395 A JP21483395 A JP 21483395A JP H08148518 A JPH08148518 A JP H08148518A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor pellet
- lead
- film
- adhesive layer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
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- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に、半導体ペレットの主面上に一端側が配置されたイン
ナーリードと、前記半導体ペレットの一辺の外側に一端
側が配置されたインナーリードとを有する樹脂封止型半
導体装置に適用して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an inner lead whose one end is arranged on the main surface of a semiconductor pellet and an inner lead whose one end is arranged outside one side of the semiconductor pellet. The present invention relates to a technique effectively applied to a resin-encapsulated semiconductor device having the same.
【０００２】[0002]
【従来の技術】回路システム(例えばＤＲＡＭ：Ｄynami
c Ｒandom Ａccess Ｍemory)を構成する半導体ペレット
を樹脂封止体で封止する半導体装置として、例えば樹脂
封止体の一辺に沿って複数本のアウターリードをジグザ
グに配置したＺＩＰ（ＺigzagＩn-ｌine Ｐackage）構
造の半導体装置がある。このＺＩＰ構造の半導体装置は
メモリモジュールの高密度実装に適している。BACKGROUND OF THE INVENTION circuit system (for example DRAM: D ynami
c R andom A ccess M emory) a semiconductor pellet constituting a semiconductor device is sealed with a resin sealing body, for example, ZIP a plurality of outer leads along one side of the resin sealing member was placed in a zigzag (Z igzag there are semiconductor devices of I n-line P ackage) structure. The semiconductor device having this ZIP structure is suitable for high-density mounting of memory modules.
【０００３】ところで半導体メモリの大容量化に伴い、
そのパッケージ技術は、リードフレームのタイパッド
(タブ)を省略して大型チップにも対応可能なＣＯＬ（Ｃ
hip Ｏn Ｌead)構造、またはＬＯＣ(Ｌead Ｏn Ｃhip）
構造が採用されている。By the way, with the increase in capacity of semiconductor memories,
The packaging technology is the lead frame tie pad
The COL ( C
hip O n L ead) structure or LOC, (L ead O n C hip)
The structure is adopted.
【０００４】ＣＯＬ構造は、例えば、電子情報通信学会
技術研究報告(集積回路)１９８９年３月、論文番号ＩＣ
Ｄ８９−１０３に開示されている。特に、この文献は、
ＺＩＰにＣＯＬ構造を採用した技術を明らかにしてい
る。The COL structure is described in, for example, the Institute of Electronics, Information and Communication Engineers Technical Report (Integrated Circuit), March 1989, Article No. IC.
It is disclosed in D89-103. In particular, this document
The technology that uses the COL structure for ZIP has been clarified.
【０００５】一方、ＬＯＣ構造は、例えば特開平６−９
７３６０号公報（１９９４年４月８日公開）に開示され
ている。On the other hand, the LOC structure is disclosed in, for example, Japanese Patent Laid-Open No. 6-9.
No. 7360 (published April 8, 1994).
【０００６】本発明者等によって開発されたＺＩＰ構造
の半導体装置は、図８（樹脂封止体の一部を除去した状
態を示す要部平面図）に示すように、半導体ペレット１
の表面上に一端側が配置された複数本のインナーリード
２と、半導体ペレット１の一辺(長辺)１ａの外側に一端
側が配置された複数本のインナーリード３と、半導体ペ
レット１の一辺１ａと対向するその他辺(長辺)１ｂの外
側に一端側が配置された複数本のインナーリード４とを
有する。つまり、本発明者等によって開発されたＺＩＰ
構造の半導体装置は、ＬＯＣ構造で構成される。このイ
ンナーリード２、インナーリード３及びインナーリード
４の夫々の一端側は、ボンディングワイヤ５を介して半
導体ペレット１の外部端子(ボンディングパッド)ＰＢに
電気的に接続されている。A semiconductor device having a ZIP structure developed by the present inventors has a semiconductor pellet 1 as shown in FIG. 8 (a plan view of a main part showing a state in which a part of a resin sealing body is removed).
A plurality of inner leads 2 whose one end side is arranged on the surface of, a plurality of inner leads 3 whose one end side is arranged outside one side (long side) 1a of the semiconductor pellet 1, and one side 1a of the semiconductor pellet 1. It has a plurality of inner leads 4 whose one end side is arranged on the outside of the other side (long side) 1b facing each other. That is, the ZIP developed by the present inventors
The semiconductor device having a structure has a LOC structure. One end side of each of the inner lead 2, the inner lead 3 and the inner lead 4 is electrically connected to an external terminal (bonding pad) PB of the semiconductor pellet 1 via a bonding wire 5.
【０００７】前記インナーリード２の一端側は、半導体
ペレット１の表面上に、絶縁性フィルム７の表面に設け
られた接着層を介在して接着固定される。さらに、前記
インナーリード３の一端側は、その絶縁性フィルム７の
表面に設けられた接着層を介在して接着固定される。つ
まり、絶縁性フィルム７は半導体ペレット１の表面から
半導体ペレット１の一辺１ａの外側に延在している。One end side of the inner lead 2 is adhesively fixed onto the surface of the semiconductor pellet 1 with an adhesive layer provided on the surface of the insulating film 7 interposed. Further, one end of the inner lead 3 is adhesively fixed via an adhesive layer provided on the surface of the insulating film 7. That is, the insulating film 7 extends from the surface of the semiconductor pellet 1 to the outside of the side 1 a of the semiconductor pellet 1.
【０００８】前記半導体ペレット１、インナーリード
２、インナーリード３、インナーリード４、ボンディン
グワイヤ５等は、トランスファモールド法に基づいて成
形された樹脂封止体９で封止される。The semiconductor pellet 1, the inner lead 2, the inner lead 3, the inner lead 4, the bonding wire 5 and the like are sealed with a resin sealing body 9 molded by a transfer molding method.
【０００９】前記インナーリード２、インナーリード
３、インナーリード４の夫々の他端側は、半導体ペレッ
ト１の一辺と対向するその他辺に向かい合う樹脂封止体
９の一辺に沿ってジグザグに配置された複数本のアウタ
ーリード１０の夫々に一体化されている。The other ends of the inner leads 2, the inner leads 3, and the inner leads 4 are arranged in a zigzag pattern along one side of the resin sealing body 9 facing the other side facing the one side of the semiconductor pellet 1. It is integrated with each of the plurality of outer leads 10.
【００１０】このように構成されたＺＩＰ構造の半導体
装置は、製品完成後の環境試験である温度サイクル試験
が施された後、製品として出荷され、その後、実装基板
に実装される。The thus structured semiconductor device having the ZIP structure is subjected to a temperature cycle test, which is an environmental test after the product is completed, and then shipped as a product, and then mounted on a mounting board.
【００１１】[0011]
【発明が解決しようとする課題】本発明者等は、前述の
ＺＩＰ構造の半導体装置について、以下の問題点を見出
した。The present inventors have found the following problems with the above-mentioned semiconductor device having the ZIP structure.
【００１２】前記半導体装置において、図８に示すよう
に、表面に接着層を有する絶縁性フィルム７は、半導体
ペレット１の一辺１ａから、その半導体ペレット１の外
周に位置したインナーリード３に向って延びている。こ
の接着層は、半導体ペレット(シリコン基板)１に比べて
熱膨張係数が大きいポリイミド系樹脂が用いられる。こ
のため、製品完成後の環境試験である温度サイクルや実
装時の温度変化による接着層の膨張、収縮で半導体ペレ
ット１の一辺１ａに応力が集中し、半導体ペレット１の
一辺１ａから内部に向って亀裂が生じるという問題があ
った。この問題点について、本発明者等は原因究明を行
った結果、その理由は以下のとおりであることが明らか
にされた。In the semiconductor device, as shown in FIG. 8, an insulating film 7 having an adhesive layer on its surface extends from one side 1a of the semiconductor pellet 1 toward the inner lead 3 located on the outer periphery of the semiconductor pellet 1. It is extended. For this adhesive layer, a polyimide resin having a thermal expansion coefficient larger than that of the semiconductor pellet (silicon substrate) 1 is used. For this reason, stress is concentrated on one side 1a of the semiconductor pellet 1 due to expansion and contraction of the adhesive layer due to a temperature cycle that is an environmental test after product completion and a temperature change at the time of mounting, and the stress is concentrated from one side 1a of the semiconductor pellet 1 toward the inside. There was a problem of cracking. As a result of investigating the cause of this problem, the inventors have found that the reason is as follows.
【００１３】図９に示すように、ペレットステージ２０
Ｂに載せられた半導体ペレット１と、絶縁性フィルム７
が接着固定されたリードフレームとをペレット取付用ツ
ール２０Ａによって熱圧着する工程において、前記絶縁
性フィルム７の接着層６の一部(６ａ)が、加熱と加圧に
よりはみ出し、直接、半導体ペレット１の端部表面１Ｂ
に接触する。この接着層と半導体ペレット表面との接触
が半導体ペレット１の亀裂の原因となった。すなわち、
一般的に、半導体ペレット１の主面は、汚染防止のため
に、外部端子(ボンディングパッド)を除いて表面保護膜
１Ｃで被覆されるが、表面保護膜１Ｃは半導体ペレット
１の主面端部（スクライブ部分）より内側に形成され
る。これは、半導体ウエーハを複数個の半導体ペレット
に分割するダイシング工程において、表面保護膜１Ｃの
クラックの防止やダイシング刃の目詰まりを防止するた
めである。つまり、表面保護膜１Ｃは半導体ウエーハの
スクライブエリアを覆わないように形成される。従っ
て、表面保護膜１Ｃの端部は半導体ペレット１の端部よ
り内側に位置することになる。このため、前記熱圧着工
程時に、接着層６の一部６ａが、直接、半導体ペレット
１の端部にかかってしまうのである。As shown in FIG. 9, the pellet stage 20
Semiconductor pellet 1 placed on B and insulating film 7
In the step of thermocompression bonding the lead frame to which is adhered and fixed by the pellet mounting tool 20A, a part (6a) of the adhesive layer 6 of the insulating film 7 is squeezed out by heating and pressurization, and the semiconductor pellet 1 is directly End surface 1B
To contact. The contact between the adhesive layer and the surface of the semiconductor pellet 1 caused the semiconductor pellet 1 to crack. That is,
Generally, the main surface of the semiconductor pellet 1 is covered with a surface protective film 1C except for external terminals (bonding pads) to prevent contamination, but the surface protective film 1C is an end portion of the main surface of the semiconductor pellet 1. It is formed inside the (scribed portion). This is to prevent cracking of the surface protective film 1C and clogging of the dicing blade in the dicing step of dividing the semiconductor wafer into a plurality of semiconductor pellets. That is, the surface protective film 1C is formed so as not to cover the scribe area of the semiconductor wafer. Therefore, the end of the surface protective film 1C is located inside the end of the semiconductor pellet 1. Therefore, during the thermocompression bonding process, the part 6a of the adhesive layer 6 directly contacts the end of the semiconductor pellet 1.
【００１４】本発明の目的は、封止体により封止された
半導体ペレットの亀裂を防止することが可能な技術を提
供することにある。An object of the present invention is to provide a technique capable of preventing cracks in a semiconductor pellet sealed by a sealing body.
【００１５】本発明の他の目的は、高信頼度を有する樹
脂封止型半導体装置を提供することにある。Another object of the present invention is to provide a resin-sealed semiconductor device having high reliability.
【００１６】本発明の他の目的は、高信頼度で、かつ高
密度実装が可能な樹脂封止型半導体装置を提供すること
にある。Another object of the present invention is to provide a resin-encapsulated semiconductor device which is highly reliable and can be mounted at high density.
【００１７】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【００１８】[0018]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.
【００１９】半導体ペレットの表面上に一端側が配置さ
れた第１インナーリードと、前記半導体ペレットの一辺
の外側に一端側が配置された第２インナーリードとを有
する半導体装置において、前記半導体ペレットの表面上
であって、かつその半導体ペレットの一辺から離間して
配置された第１絶縁性フィルムによって前記第１インナ
ーリードの一端側が接着固定され、前記半導体ペレット
の一辺の外側に配置された第２絶縁性フィルムによって
前記第２インナーリードの一端側が接着固定されてい
る。In a semiconductor device having a first inner lead whose one end side is arranged on the surface of the semiconductor pellet and a second inner lead whose one end side is arranged outside one side of the semiconductor pellet, the surface of the semiconductor pellet is And one end side of the first inner lead is adhesively fixed by a first insulating film that is arranged apart from one side of the semiconductor pellet, and a second insulating property that is arranged outside one side of the semiconductor pellet. One end of the second inner lead is adhesively fixed by a film.
【００２０】[0020]
【作用】上述した手段によれば、半導体ペレットの端部
(又は角部)表面に絶縁性フィルムの接着層が接触しない
ので、製品完成後の環境試験である温度サイクル時や実
装時の温度変化で接着層が膨張、収縮しても、半導体ペ
レットの端部に応力が集中しない。この結果、封止体に
より封止された半導体ペレットの亀裂を防止することが
できる。According to the above-mentioned means, the end portion of the semiconductor pellet is
Since the adhesive layer of the insulating film does not come into contact with the (or corner) surface, even if the adhesive layer expands or contracts due to the temperature cycle during the environmental test after product completion or the temperature change during mounting, the edge of the semiconductor pellet Stress does not concentrate on the part. As a result, it is possible to prevent cracks in the semiconductor pellet sealed by the sealing body.
【００２１】なお、本発明において、インナーリードと
は封止体で封止された部分のリードを言う。一方、アウ
ターリードとは封止体の外に導出されているリードを言
う。In the present invention, the inner lead means the lead of the portion sealed with the sealing body. On the other hand, the outer lead means a lead led out of the sealing body.
【００２２】[0022]
【実施例】以下、本発明の構成について、ＺＩＰ構造の
半導体装置に適用した一実施例とともに説明する。な
お、実施例を説明するための全図において、同一機能を
有するものは同一符号を付け、その繰り返しの説明は省
略する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below together with an embodiment applied to a semiconductor device having a ZIP structure. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.
【００２３】（実 施 例 １）本発明の実施例１である
ＺＩＰ構造の半導体装置の概略構成を図１（樹脂封止体
の一部を除去した状態を示す要部平面図）及び図２（図
１に示すＡ−Ａ’線の切断々面図）に示す。(Embodiment 1) A schematic structure of a semiconductor device having a ZIP structure, which is Embodiment 1 of the present invention, is shown in FIG. 1 (a plan view of an essential part showing a state in which a part of a resin sealing body is removed) and FIG. (A sectional view taken along the line AA ′ shown in FIG. 1).
【００２４】図１及び図２に示すように、ＺＩＰ構造の
半導体装置は、半導体ペレット１の表面上に一端側が配
置された複数本のインナーリード２と、半導体ペレット
１の一辺１ａの外側に一端側が配置された複数本のイン
ナーリード３と、半導体ペレット１の一辺１ａと対向す
るその他辺１ｂの外側に一端側が配置された複数本のイ
ンナーリード４とを有する。つまり、本実施例の半導体
装置は半導体ペレット１の表面上に複数本のインナーリ
ード２の夫々の一端側が配置されたＬＯＣ構造で構成さ
れる。As shown in FIGS. 1 and 2, the semiconductor device having the ZIP structure has a plurality of inner leads 2 whose one end side is arranged on the surface of the semiconductor pellet 1 and one end outside the one side 1a of the semiconductor pellet 1. It has a plurality of inner leads 3 whose sides are arranged, and a plurality of inner leads 4 whose one ends are arranged outside the other side 1b facing one side 1a of the semiconductor pellet 1. That is, the semiconductor device of the present embodiment has a LOC structure in which one end side of each of the plurality of inner leads 2 is arranged on the surface of the semiconductor pellet 1.
【００２５】前記半導体ペレット１は例えば平面が方形
状（具体的には短辺が約６．６［ｍｍ］、長辺が約１５
［ｍｍ］の長方形状）に形成された単結晶珪素からなる
半導体基板１Ａを主体に構成される。この半導体基板１
Ａは、例えば３．１×１０~6［１／℃］程度の熱膨張係
数を有する。The semiconductor pellet 1 has, for example, a square plane (specifically, a short side of about 6.6 [mm] and a long side of about 15).
A semiconductor substrate 1A made of single crystal silicon formed in a [mm] rectangular shape is mainly configured. This semiconductor substrate 1
A has a coefficient of thermal expansion of, for example, about 3.1 × 10 6 [1 / ° C.].
【００２６】前記半導体基板１Ａの素子形成面には、記
憶回路システム、論理回路システム、或はそれらの混合
回路システム等が構成されている。半導体基板１Ａの素
子形成面上には、配線層、層間絶縁層の夫々を複数段積
み重ねた多層配線層１Ｂが形成される。この多層配線層
１Ｂの最上層の配線層には複数の外部端子（ボンディン
グパッド）ＢＰが形成される。A memory circuit system, a logic circuit system, or a mixed circuit system thereof is formed on the element formation surface of the semiconductor substrate 1A. On the element formation surface of the semiconductor substrate 1A, a multilayer wiring layer 1B is formed by stacking a plurality of wiring layers and interlayer insulating layers. A plurality of external terminals (bonding pads) BP are formed on the uppermost wiring layer of the multilayer wiring layer 1B.
【００２７】前記多層配線層１Ｂ上は外部端子ＢＰが露
出するように表面保護膜（最終保護膜）１Ｃで被覆され
ている。この表面保護膜１Ｃは、例えば、メモリにおけ
る耐α線強度向上を図ることができ、また、絶縁性フィ
ルムとの接着性向上を図ることができるポリイミド系樹
脂から成り、５．８×１０~5［１／℃］程度の熱膨張係
数を有する。この表面保護膜１Ｃはチップ端より内側に
形成される。これは、半導体ウエーハのダイシング工程
において、ダイシング刃の目詰まり等を防止するためで
ある。The multilayer wiring layer 1B is covered with a surface protective film (final protective film) 1C so that the external terminals BP are exposed. The surface protective film 1C is, for example, resistance to α-ray intensity improvement in the memory can be achieved, also made of polyimide resin which can be achieved improving adhesion between the insulating film, 5.8 × 10 ~ 5 It has a thermal expansion coefficient of about [1 / ° C]. The surface protective film 1C is formed inside the chip end. This is to prevent clogging of the dicing blade in the dicing process of the semiconductor wafer.
【００２８】前記インナーリード２の一端側は、絶縁性
フィルム７Ａの一方の表面上に接着層８を介在して接着
固定されている。そして、その絶縁性フィルム７Ａは、
半導体ペレット１の表面上に、その絶縁性フィルムの他
方の主面に接着された接着層６を介在して接着固定され
ている。特に、この両面に接着層６、接着層８を有する
絶縁性フィルム７Ａは、半導体ペレット１の一辺１ａか
ら外れたそのペレット主面上に位置して配置される。ま
た、絶縁性フィルム７Ａは、半導体ペレット１の一辺１
ａと対向するその他辺１ｂから外れたそのペレット主面
上に位置して配置される。例えば、半導体ペレット１の
一辺１ａとこの一辺に向かい合う絶縁性フィルム７Ａの
一辺との間の距離は０．２［ｍｍ］以上に設定される。
同様に、半導体ペレット１の他辺１ｂとこの他辺と向か
い合う絶縁性フィルム７Ａの一辺との間の距離は、０．
２［ｍｍ］以上に設定される。この半導体ペレット１の
夫々の一辺１ａ、１ｂと絶縁性フィルム７Ａとの間の距
離の設定は、絶縁性フィルム７Ａが半導体ペレット１の
表面上に熱圧着で固定される時に、接着層６が半導体ペ
レット１の夫々の辺(１ａ，１ｂ)に向ってはみ出さない
ように考慮されている。つまり、半導体ペレット１の一
辺１ａ及びそれと対向する他辺１ｂの夫々の近傍には、
ペレットクラックの要因となった接着層６が配置されな
い。なお、これら接着層６、接着層８の夫々は、例え
ば、ポリエーテルアミドイミド系樹脂やエポキシ系樹脂
で形成され、その熱膨張係数は５×１０~5［１／℃］程
度であり、単結晶珪素(Ｓｉ)からなる半導体ペレットの
１０倍以上の熱膨張係数を有する。絶縁性フィルム７Ａ
は、例えば、ポリイミド系樹脂で形成され、２．５×１
０~5［１／℃］程度の熱膨張係数を有する。One end side of the inner lead 2 is adhesively fixed on one surface of the insulating film 7A with an adhesive layer 8 interposed. And the insulating film 7A is
On the surface of the semiconductor pellet 1, the adhesive layer 6 adhered to the other main surface of the insulating film is adhered and fixed. In particular, the insulating film 7A having the adhesive layer 6 and the adhesive layer 8 on both sides thereof is arranged on the main surface of the pellet that is off the side 1a of the semiconductor pellet 1. In addition, the insulating film 7A is one side 1 of the semiconductor pellet 1.
It is located on the main surface of the pellet, which is separated from the other side 1b opposite to a. For example, the distance between one side 1a of the semiconductor pellet 1 and one side of the insulating film 7A facing this side is set to 0.2 [mm] or more.
Similarly, the distance between the other side 1b of the semiconductor pellet 1 and one side of the insulating film 7A facing the other side is 0.
It is set to 2 [mm] or more. The distance between each side 1a, 1b of the semiconductor pellet 1 and the insulating film 7A is set so that when the insulating film 7A is fixed on the surface of the semiconductor pellet 1 by thermocompression bonding, the adhesive layer 6 is a semiconductor. It is considered that the pellet 1 does not protrude toward the respective sides (1a, 1b). That is, in the vicinity of the one side 1a of the semiconductor pellet 1 and the other side 1b opposite thereto,
The adhesive layer 6 that causes the pellet crack is not arranged. Each of the adhesive layers 6 and 8 is formed of, for example, a polyether amide imide resin or an epoxy resin, and has a thermal expansion coefficient of about 5 × 10 to 5 [1 / ° C.]. It has a thermal expansion coefficient 10 times or more that of a semiconductor pellet made of crystalline silicon (Si). Insulating film 7A
Is formed of, for example, a polyimide resin, and is 2.5 × 1.
It has a coefficient of thermal expansion of about 0 to 5 [1 / ° C].
【００２９】前記インナーリード３の一端側は、前記絶
縁性フィルム７Ａとは独立して絶縁性フィルム７Ｂに接
着固定されている。すなわち、インナーリード３の一端
側は、その絶縁性フィルム７Ｂの表面上に接着層８を介
在して接着固定される。この絶縁性フィルム７Ｂは、半
導体ペレット１の一辺１ａの外側に絶縁性フィルム７Ａ
とは分割して配置され、かつ半導体ペレット１の一辺１
ａから外れた位置に配置される。つまり、半導体ペレッ
ト１の一辺１ａには接着層６及び絶縁性フィルム７Ｂが
配置されない。One end side of the inner lead 3 is adhesively fixed to the insulating film 7B independently of the insulating film 7A. That is, one end side of the inner lead 3 is adhesively fixed on the surface of the insulating film 7B with the adhesive layer 8 interposed. The insulating film 7B is formed on the outside of one side 1a of the semiconductor pellet 1 by the insulating film 7A.
Is divided and arranged, and one side 1 of the semiconductor pellet 1
It is arranged at a position away from a. That is, the adhesive layer 6 and the insulating film 7B are not arranged on the side 1a of the semiconductor pellet 1.
【００３０】なお、前記絶縁性フィルム７Ｂによる複数
のインナーリード３の一端側の接着固定は、リードの不
良、例えばモールド時の樹脂の流れによるリードの変形
やリードの移動を防止するためにある。The adhesive fixing of one end side of the plurality of inner leads 3 by the insulating film 7B is for preventing the defects of the leads, for example, the deformation of the leads and the movement of the leads due to the resin flow at the time of molding.
【００３１】前記インナーリード２、インナーリード３
及びインナーリード４の夫々の一端側は、ボンディング
ワイヤ５を介して半導体ペレット１の外部端子（ボンデ
ィングパッド）ＢＰに電気的に接続されている。ボンデ
ィングワイヤ５としては、例えば金(Ａｕ)ワイヤ、銅
(Ｃｕ)ワイヤ、アルミニウム(Ａｌ)ワイヤ、或は金属ワ
イヤの表面に絶縁性樹脂を被覆した被覆ワイヤが用いら
れる。Inner lead 2 and inner lead 3
One end side of each of the inner leads 4 is electrically connected to an external terminal (bonding pad) BP of the semiconductor pellet 1 via a bonding wire 5. As the bonding wire 5, for example, gold (Au) wire, copper
A (Cu) wire, an aluminum (Al) wire, or a coated wire in which the surface of a metal wire is coated with an insulating resin is used.
【００３２】前記半導体ペレット１、インナーリード
２、インナーリード３、インナーリード４及びボンディ
ングワイヤ５等は、トランスファモールド法に基づいて
成形された樹脂封止体９で封止される。樹脂封止体９
は、低応力化を図る目的として、例えばフェノール系硬
化剤、シリコーンゴム及びフィラーが添加されたエポキ
シ系樹脂で形成される。このエポキシ系樹脂は１３×１
０~6［１／℃］程度の熱膨張係数を有する。The semiconductor pellet 1, the inner lead 2, the inner lead 3, the inner lead 4, the bonding wire 5 and the like are sealed with a resin sealing body 9 molded by a transfer molding method. Resin sealing body 9
Is formed of, for example, an epoxy resin to which a phenolic curing agent, silicone rubber, and a filler are added for the purpose of reducing the stress. This epoxy resin is 13 × 1
It has a coefficient of thermal expansion of about 0 to 6 [1 / ° C].
【００３３】前記インナーリード２、インナーリード３
及びインナーリード４の夫々の他端側は、半導体ペレッ
ト１の一辺１ａと対向するその他辺１ｂに向かい合う樹
脂封止体９の一辺に沿ってジグザグに配置された複数本
のアウターリード１０の夫々に一体化されている。この
アウターリード１０は、半導体ペレット１、インナーリ
ード２、インナーリード３、インナーリード４及びボン
ディングワイヤ５等を樹脂封止体９で封止した後、リー
ドフレームの枠体から切断され、その後、ジグザグ形状
に成形される。なお、図１及び図２は、アウターリード
１０のジグザグ形状を省略してある。Inner lead 2 and inner lead 3
And the other end side of each of the inner leads 4 is connected to each of the plurality of outer leads 10 arranged in zigzag along one side of the resin sealing body 9 facing the one side 1a facing the semiconductor pellet 1 and the other side 1b. It is integrated. The outer lead 10 is obtained by sealing the semiconductor pellet 1, the inner lead 2, the inner lead 3, the inner lead 4, the bonding wire 5 and the like with a resin encapsulant 9 and then cutting the frame from the lead frame. Shaped into a shape. Note that the zigzag shape of the outer lead 10 is omitted in FIGS. 1 and 2.
【００３４】本実施例で使用されるリードフレームを図
３(要部平面図)に示す。図３に示すように、枠体１１で
規定された領域内に、複数本のインナーリード２、複数
本のインナーリード３、複数本のインナーリード４、複
数本のアウターリード１０等を配置する。複数本のイン
ナーリード２の夫々は、タイバー(ダムバー)１１Ａを介
して複数本のアウターリード１０の夫々に一体化されて
いる。複数本のインナーリード３の夫々は、タイバー１
１Ａを介して複数本のアウターリード１０の夫々に一体
化されている。複数本のインナーリード４の夫々は、タ
イバー１１Ａを介して複数本のアウターリード１０の夫
々に一体化されている。複数本のアウターリード１０の
夫々は枠体１１Ａに一体化されている。このようなリー
ドフレームの段階において、複数本のインナーリード２
の夫々の一端側には絶縁性フィルム７Ａがそのフィルム
表面に被覆された接着層(８)を介して接着固定されてい
る。複数本のインナーリード３の夫々の一端側には絶縁
性フィルム７Ｂがそのフィルム表面に被覆された接着層
(８)を介して接着固定されている。この絶縁性フィルム
７Ｂは、トランスファモールド法に基づいて樹脂封止体
９を成形する際、樹脂の流れによって生じるインナーリ
ード３の変形を防止する。なお、リードフレームは、例
えばＦｅ−Ｎｉ（例えばＮｉ含有率４２又は５０
［％］）合金で形成され、４．３×１０~6［１／℃］程
度の熱膨張係数を有する。The lead frame used in this embodiment is shown in FIG. 3 (plan view of the main part). As shown in FIG. 3, a plurality of inner leads 2, a plurality of inner leads 3, a plurality of inner leads 4, a plurality of outer leads 10, etc. are arranged in a region defined by the frame 11. Each of the plurality of inner leads 2 is integrated with each of the plurality of outer leads 10 via a tie bar (dam bar) 11A. Each of the plurality of inner leads 3 has a tie bar 1.
It is integrated with each of the plurality of outer leads 10 via 1A. Each of the plurality of inner leads 4 is integrated with each of the plurality of outer leads 10 via a tie bar 11A. Each of the plurality of outer leads 10 is integrated with the frame body 11A. In such a lead frame stage, a plurality of inner leads 2
An insulating film 7A is adhered and fixed to one end of each of them through an adhesive layer (8) coated on the surface of the film. An adhesive layer having an insulating film 7B coated on the surface of one end of each of the plurality of inner leads 3
It is bonded and fixed via (8). The insulating film 7B prevents the inner lead 3 from being deformed due to the flow of resin when the resin sealing body 9 is molded by the transfer molding method. The lead frame is made of, for example, Fe-Ni (for example, Ni content of 42 or 50).
[%]) Alloy and has a thermal expansion coefficient of about 4.3 × 10 6 [1 / ° C.].
【００３５】次に、前述のように構成されたリードフレ
ームに対し、半導体ペレット１を取り付ける工程を図４
を用いて説明する。Next, the process of attaching the semiconductor pellet 1 to the lead frame constructed as described above will be described with reference to FIG.
Will be explained.
【００３６】主面に保護保護膜１Ｃが被覆された半導体
ペレット１をペレットステージ２０Ｂに載置する。そし
て、この半導体ペレット１の主面上に、図３に示したリ
ードフレームが載せられ、ペレットステージ２０Ｂとペ
レット取付用ツール２０Ａとを、所望の温度に加熱した
状態で加圧することにより、その半導体ペレット１が絶
縁性フィルム７Ａに被覆されている接着層６を介してリ
ードフレーム（インナーリード２）に熱圧着される。こ
の熱圧着は、例えば、約４００［℃］の加熱温度、約４
［Ｋｇ］の圧力によって達成される。この時、絶縁性フ
ィルム７Ａは半導体ペレット１の夫々の辺(１ａ，１ｂ)
よりも内側に位置している。このため、ペレット取付用
ツール２０Ａがインナーリード２を加圧したところで、
接着層６が押し流されて、半導体ペレット１の夫々の辺
(１ａ，１ｂ)に向ってはみ出しても、その接着層６が半
導体ペレット１の各辺(１ａ，１ｂ)で直接その半導体ペ
レット１に接触するまでには至らない。The semiconductor pellet 1 whose main surface is covered with the protective film 1C is placed on the pellet stage 20B. Then, the lead frame shown in FIG. 3 is placed on the main surface of the semiconductor pellet 1, and the pellet stage 20B and the pellet mounting tool 20A are pressed in a state of being heated to a desired temperature, thereby the semiconductor The pellet 1 is thermocompression-bonded to the lead frame (inner lead 2) via the adhesive layer 6 covered with the insulating film 7A. This thermocompression bonding is performed, for example, at a heating temperature of about 400 [° C.], about 4
Achieved by a pressure of [Kg]. At this time, the insulating film 7A is formed on each side (1a, 1b) of the semiconductor pellet 1.
It is located inside. Therefore, when the pellet mounting tool 20A pressurizes the inner lead 2,
The adhesive layer 6 is washed away, and each side of the semiconductor pellet 1 is
Even if it protrudes toward (1a, 1b), the adhesive layer 6 cannot reach the semiconductor pellet 1 directly at each side (1a, 1b) of the semiconductor pellet 1.
【００３７】このように、リードフレームに対して半導
体ペレット１が取り付けられた後、図１に示すように、
前記インナーリード２、インナーリード３及びインナー
リード４の夫々の一端側と、半導体ペレット１の主面上
に露出した複数の外部端子ＢＰとはボンディングワイヤ
５によって電気的に接続される。そして、半導体ペレッ
ト１、インナーリード２、インナーリード３、インナー
リード４及びボンディングワイヤ５はトランスファモー
ルド法によって樹脂封止される。樹脂封止後、アウター
リード１０はリードフレームの枠体から切断され、ジグ
ザグ形状にリード成形される。After the semiconductor pellet 1 is attached to the lead frame in this way, as shown in FIG.
One end side of each of the inner lead 2, the inner lead 3 and the inner lead 4 and a plurality of external terminals BP exposed on the main surface of the semiconductor pellet 1 are electrically connected by a bonding wire 5. Then, the semiconductor pellet 1, the inner lead 2, the inner lead 3, the inner lead 4 and the bonding wire 5 are resin-sealed by a transfer molding method. After the resin sealing, the outer lead 10 is cut from the frame body of the lead frame and is lead-formed in a zigzag shape.
【００３８】このように構成されたＺＩＰ構造の半導体
装置は、製品完成後の環境試験である温度サイクル試験
が施された後、製品として出荷され、その後、実装基板
に実装される。この温度サイクル試験は、例えば、−５
５［℃］の温度下において１０分間、１５０［℃］の温
度下において１０分間を１サイクルとする条件で１００
０サイクル行なわれる。このような温度サイクル試験で
本実施例の半導体装置は、その半導体ペレット１に亀裂
が生じなかった。The thus structured semiconductor device having the ZIP structure is subjected to a temperature cycle test, which is an environmental test after the product is completed, and then shipped as a product, and then mounted on a mounting board. This temperature cycle test is, for example, −5.
100 under the condition that one cycle is 10 minutes at a temperature of 5 [° C.] and 10 minutes at a temperature of 150 [° C.].
0 cycles are performed. In such a temperature cycle test, in the semiconductor device of this example, the semiconductor pellet 1 was not cracked.
【００３９】上述した本発明の実施例によれば、半導体
ペレット１の表面上に一端側が配置されたインナーリー
ド２と、半導体ペレット１の一辺の外側に一端側が配置
されたインナーリード３とを有するＺＩＰ構造の半導体
装置において、前記半導体ペレット１の表面上であっ
て、かつその半導体ペレット１の一辺から離間して配置
された絶縁性フィルム７Ａによってインナーリード２の
一端側が接着固定され、そして、その半導体ペレット１
の一辺の外側に配置された他の絶縁性フィルム７Ｂによ
ってインナーリード３の一端側が接着固定される。した
がって、半導体ペレット１の一辺１ａにはその一辺をま
たぐように接着層６が覆われない。すなわち、半導体ペ
レット１の端部(又は角部)表面に絶縁性フィルムの接着
層６が接触しないので、製品完成後の環境試験である温
度サイクル時や実装時の温度変化で接着層６が膨張、収
縮しても、半導体ペレット１の一辺に応力が集中しな
い。この結果、樹脂封止体によって封止された半導体ペ
レット１の亀裂を防止することができる。According to the above-described embodiment of the present invention, the inner lead 2 having one end side disposed on the surface of the semiconductor pellet 1 and the inner lead 3 having the one end side disposed outside one side of the semiconductor pellet 1 are provided. In the semiconductor device having the ZIP structure, one end side of the inner lead 2 is adhesively fixed by an insulating film 7A arranged on the surface of the semiconductor pellet 1 and separated from one side of the semiconductor pellet 1, and Semiconductor pellet 1
One end side of the inner lead 3 is adhesively fixed by another insulating film 7B arranged on the outer side of one side. Therefore, the adhesive layer 6 does not cover the one side 1a of the semiconductor pellet 1 so as to extend over the one side. That is, since the adhesive layer 6 of the insulating film does not come into contact with the end (or corner) surface of the semiconductor pellet 1, the adhesive layer 6 expands due to a temperature cycle that is an environmental test after product completion or a temperature change during mounting. Even if it contracts, stress does not concentrate on one side of the semiconductor pellet 1. As a result, it is possible to prevent the semiconductor pellet 1 sealed by the resin sealing body from cracking.
【００４０】（実 施 例 ２）本発明の実施例２である
ＺＩＰ構造の半導体装置の概略構成を図５（樹脂封止体
の一部を除去した状態を示す要部平面図）に示す。(Embodiment 2) A schematic structure of a semiconductor device having a ZIP structure, which is Embodiment 2 of the present invention, is shown in FIG. 5 (a plan view of the principal part showing a state in which a part of the resin sealing body is removed).
【００４１】図５に示すように、半導体ペレット１の表
面上であって、かつその半導体ペレット１の一辺１ａか
ら離間して配置された絶縁性フィルム７Ａによってイン
ナーリード２の一端側が接着固定される。半導体ペレッ
ト１の一辺（１ａと直交する他の辺(短辺)１ｃ）の外側
に沿って配置された絶縁性フィルム７Ｂによりインナー
リード３及びインナーリード２ｍは共通に接着固定され
る。したがって、本実施例の場合でも、半導体ペレット
１の一辺にはその一辺をまたぐように接着層６が覆われ
ないので、製品完成後の環境試験である温度サイクル時
や実装時の温度変化で接着層６が膨張、収縮しても、半
導体ペレット１の一辺に応力が集中しない。そして、さ
らに、半導体ペレット１の短辺(１ｃ)から長辺(１ａ)に
沿って延在する比較的長いインナーリード３は、絶縁性
フィルム７Ｂを介して半導体ペレット１の主面上に接着
固定されたインナーリード２ｍに接着固定されているた
め、より一層インナーリード３の形状不良を防止するこ
とができる。As shown in FIG. 5, one end side of the inner lead 2 is bonded and fixed by an insulating film 7A arranged on the surface of the semiconductor pellet 1 and spaced from one side 1a of the semiconductor pellet 1. . The inner lead 3 and the inner lead 2m are commonly bonded and fixed by the insulating film 7B arranged along the outside of one side (the other side (short side) 1c orthogonal to 1a) of the semiconductor pellet 1. Therefore, even in the case of the present embodiment, the adhesive layer 6 is not covered on one side of the semiconductor pellet 1 so as to extend over the one side, and therefore, the semiconductor pellet 1 is bonded by a temperature change during a temperature cycle or mounting which is an environmental test after product completion. Even if the layer 6 expands or contracts, stress is not concentrated on one side of the semiconductor pellet 1. Further, the relatively long inner leads 3 extending from the short side (1c) to the long side (1a) of the semiconductor pellet 1 are adhesively fixed onto the main surface of the semiconductor pellet 1 via the insulating film 7B. Since the inner lead 2m is fixed by adhesion, it is possible to further prevent the defective shape of the inner lead 3.
【００４２】図６は本実施例で用いられるリードフレー
ムの要部平面図である。図６に示すように、リードフレ
ームの段階で絶縁性フィルム７Ｂは接着層を介してイン
ナーリード３及びインナーリード２ｍにまたがって接着
固定されている。図７は、図６に示すＢ−Ｂ’切断々面
図である。FIG. 6 is a plan view of the main parts of the lead frame used in this embodiment. As shown in FIG. 6, at the stage of the lead frame, the insulating film 7B is adhesively fixed across the inner leads 3 and the inner leads 2m via an adhesive layer. FIG. 7 is a sectional view taken along line BB ′ shown in FIG.
【００４３】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.
【００４４】例えば、実施例１において、絶縁性フィル
ム本体７Ａ、７Ｂは、図８に示す絶縁性フィルム７のよ
うに一体化された構成であってもよい。ただし、本発明
の解決すベき課題に従って、このフィルム本体の半導体
ペレット側に位置する接着層６は、半導体ペレットの一
辺、すなわち、半導体ペレットの端部(又は角部)に接触
しないように、その半導体ペレットの端部から離間さ
れ、半導体ペレットの主面に接着される。For example, in the first embodiment, the insulating film bodies 7A and 7B may be integrated as in the insulating film 7 shown in FIG. However, according to the problem to be solved by the present invention, the adhesive layer 6 located on the semiconductor pellet side of the film main body does not contact one side of the semiconductor pellet, that is, the end portion (or corner portion) of the semiconductor pellet, It is separated from the end of the semiconductor pellet and adhered to the main surface of the semiconductor pellet.
【００４５】また、実施例２において、絶縁性フィルム
７Ｂは、インナーリード３のみに接着固定させ、インナ
ーリード２ｍに接着固定させないようにしてもよい。こ
の場合、高価な絶縁性フィルム７Ｂの長さ削減により、
リードフレーム単価のコスト低減を図ることができる。
そして、さらに、半導体ペレット１から遠ざけて絶縁性
フィルム７Ｂを配置できる。このことは、その絶縁性フ
ィルム７Ｂの大きさに影響を受けることなく、半導体ペ
レット１を取り付けるためのペレットステージ２０Ｂを
小型で、かつ単純な構造とすることができる。Further, in the second embodiment, the insulating film 7B may be fixed to the inner lead 3 only, and not to the inner lead 2m. In this case, by reducing the length of the expensive insulating film 7B,
The cost of the lead frame unit price can be reduced.
Further, the insulating film 7B can be arranged further away from the semiconductor pellet 1. This allows the pellet stage 20B for mounting the semiconductor pellet 1 to have a small size and a simple structure without being affected by the size of the insulating film 7B.
【００４６】そして、さらに、前述の実施例はＺＩＰ構
造のＬＯＣに適用しているが、本発明はその構造に限定
されるものではなく、ＳＯＰ(Ｓmall Ｏut-line Ｐacka
ge)構造のＬＯＣに適用が可能である。[0046] Then, further, although the above-described embodiments are applied to LOC of ZIP structure, the present invention is not limited in its structure, SOP (S mall O ut- line P acka
It is applicable to LOC of ge) structure.
【００４７】[0047]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００４８】封止体により封止された半導体ペレットの
亀裂を防止することができる。すなわち、本発明によっ
て達成されたＬＯＣ構造の樹脂封止型半導体装置は高信
頼度を有する。It is possible to prevent cracks in the semiconductor pellet sealed by the sealing body. That is, the LOC structure resin-sealed semiconductor device achieved by the present invention has high reliability.
【００４９】また、実施例１及び実施例２に開示された
ＺＩＰ構造のＬＯＣから成る樹脂封止型半導体装置は、
高信頼度を有し、かつ高密度実装が可能となる。The resin-encapsulated semiconductor device made of LOC having the ZIP structure disclosed in the first and second embodiments is
It has high reliability and enables high-density mounting.
【図１】本発明の実施例１であるＺＩＰ構造の半導体装
置の樹脂封止体の一部を除去した状態を示す要部平面図
である。FIG. 1 is a main part plan view showing a state in which a part of a resin sealing body of a semiconductor device having a ZIP structure according to a first embodiment of the present invention is removed.
【図２】図１に示すＡ−Ａ’線の切断々面図である。FIG. 2 is a cross-sectional view taken along the line A-A ′ shown in FIG.
【図３】前記半導体装置の製造プロセス(半導体装置の
組立)で使用されるリードフレームの要部平面図であ
る。FIG. 3 is a plan view of a main part of a lead frame used in the manufacturing process of the semiconductor device (assembly of the semiconductor device).
【図４】前記半導体装置の製造プロセスにおいて、半導
体ペレットとリードフレームとを熱圧着する工程を示す
図である。FIG. 4 is a diagram showing a step of thermocompression bonding a semiconductor pellet and a lead frame in the manufacturing process of the semiconductor device.
【図５】本発明の実施例２であるＺＩＰ構造の半導体装
置の樹脂封止体の一部を除去した状態を示す要部平面図
である。FIG. 5 is a plan view of a principal part showing a state in which a part of a resin sealing body of a semiconductor device having a ZIP structure which is Embodiment 2 of the present invention is removed.
【図６】前記半導体装置の製造プロセスで使用されるリ
ードフレームの要部平面図である。FIG. 6 is a plan view of a main portion of a lead frame used in the manufacturing process of the semiconductor device.
【図７】図６に示すＢ−Ｂ’線の切断々面図である。7 is a cross-sectional view taken along the line B-B 'shown in FIG.
【図８】従来のＺＩＰ構造の半導体装置における樹脂封
止体の一部を除去した状態を示す要部平面図である。FIG. 8 is a plan view of relevant parts showing a state in which a part of a resin sealing body is removed in a conventional semiconductor device having a ZIP structure.
【図９】従来のＺＩＰ構造の半導体装置において、半導
体ペレットとリードフレームとを熱圧着する工程を示す
図である。FIG. 9 is a diagram showing a process of thermocompression bonding a semiconductor pellet and a lead frame in a conventional semiconductor device having a ZIP structure.
１…半導体ペレット、１Ａ…半導体基板、１Ｂ…多層配
線層、１Ｃ…表面保護膜(最終保護膜)、２…インナーリ
ード、３…インナーリード、４…インナーリード、５…
ボンディングワイヤ、６…接着層、７，７Ａ，７Ｂ…絶
縁性フィルム、８…接着層、９…樹脂封止体、１０…ア
ウターリード、１１…枠体、１１Ａ…タイバー。DESCRIPTION OF SYMBOLS 1 ... Semiconductor pellet, 1A ... Semiconductor substrate, 1B ... Multilayer wiring layer, 1C ... Surface protective film (final protective film), 2 ... Inner lead, 3 ... Inner lead, 4 ... Inner lead, 5 ...
Bonding wire, 6 ... Adhesive layer, 7, 7A, 7B ... Insulating film, 8 ... Adhesive layer, 9 ... Resin sealing body, 10 ... Outer lead, 11 ... Frame body, 11A ... Tie bar.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/50 Ｙ Ｕ (72)発明者 坪井 和哉 東京都小平市上水本町５丁目20番１号 日 立超エル・エス・アイ・エンジニアリング 株式会社内 (72)発明者 金本 光一 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所半導体事業部内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Reference number within the agency FI Technical indication location H01L 23/50 Y U (72) Inventor Kazuya Tsuboi 5-20-1 Kamimizumotocho, Kodaira-shi, Tokyo No. Nititsu Super LSI Engineering Co., Ltd. (72) Inventor Koichi Kanemoto 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Business Division, Hitachi, Ltd.
Claims (19)
おいて、半導体ペレットと第１のリード群とを接着する
接着層を有する第１のフィルムと、半導体ペレットの外
側であって、かつ半導体ペレットの端部から離れた位置
において、第２のリード群と接着する接着層を有する第
２のフィルムと、を有することを特徴とする半導体装
置。1. A first film having an adhesive layer for adhering the semiconductor pellet and the first lead group at a position remote from the end of the semiconductor pellet, and outside the semiconductor pellet, and And a second film having an adhesive layer that adheres to the second lead group at a position away from the end portion.
ルムは、その夫々の両主面に接着層を有する絶縁性フィ
ルムから成ることを特徴とする請求項１に記載の半導体
装置。2. The semiconductor device according to claim 1, wherein the first film and the second film are insulating films each having an adhesive layer on both main surfaces thereof.
膨張係数の１０倍以上の熱膨張係数を有することを特徴
とする請求項１又は請求項２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the adhesive layer has a coefficient of thermal expansion that is 10 times or more the coefficient of thermal expansion of the semiconductor pellet.
ド系樹脂から成ることを特徴とする請求項１乃至請求項
３のうちいずれか１項に記載の半導体装置。4. The semiconductor device according to claim 1, wherein the adhesive layer and the film are made of a polyimide resin.
側に表面保護膜を有することを特徴とする請求項１乃至
請求項４のうちいずれか１項に記載の半導体装置。5. The semiconductor device according to claim 1, wherein the semiconductor pellet has a surface protective film inside an end portion thereof.
第２のリード群、第１のフィルム、第２のフィルムの夫
々は、樹脂で封止されていることを特徴とする請求項１
乃至請求項５のうちいずれか１項に記載の半導体装置。6. The semiconductor pellet, a first lead group,
The second lead group, the first film, and the second film are each sealed with a resin.
A semiconductor device according to claim 5.
半導体ペレットの端部から離れた位置において半導体ペ
レットに接着された第１のリード群と、半導体ペレット
の端部から離れた位置において、接着層を有する第２の
フィルムと接着された第２のリード群と、を有すること
を特徴とする半導体装置。7. Through a first film having an adhesive layer,
A first lead group bonded to the semiconductor pellet at a position distant from the end of the semiconductor pellet, and a second lead bonded to a second film having an adhesive layer at a position distant from the end of the semiconductor pellet. A semiconductor device comprising: a group.
おいて、半導体ペレットと、第１のリード群とを接着す
る接着層を有する第１のフィルムと、半導体ペレットの
端部から離れた位置において、前記第１のリード群、及
び第２のリード群の一部と接着する接着層を有する第２
のフィルムと、を有することを特徴とする半導体装置。8. A first film having an adhesive layer for bonding the semiconductor pellet and the first lead group at a position distant from the end of the semiconductor pellet, and a position distant from the end of the semiconductor pellet, A second lead having an adhesive layer that adheres to the first lead group and a part of the second lead group
A film, and a semiconductor device.
て、半導体ペレットの端部から離れた位置において、半
導体ペレットと接着された第１のリード群と、半導体ペ
レットの端部から離れた位置において、接着層を有する
第２のフィルムと、接着された前記第１のリード群、及
び第２のリード群の一部と、を有することを特徴とする
半導体装置。9. A first lead group bonded to the semiconductor pellet at a position separated from the end of the semiconductor pellet through a first film having an adhesive layer, and a position separated from the end of the semiconductor pellet. 2. A semiconductor device comprising: a second film having an adhesive layer; and the first lead group and a part of the second lead group that are bonded together.
置された第１インナーリードと、前記半導体ペレットの
一辺の外側に一端側が配置された第２インナーリードと
を有する半導体装置において、前記半導体ペレットの表
面上であって、かつその半導体ペレットの一辺から離間
して配置された第１絶縁性フィルムによって前記第１イ
ンナーリードの一端側が接着固定され、前記半導体ペレ
ットの一辺の外側に配置された他の第２絶縁性フィルム
によって前記第２インナーリードの一端側が接着固定さ
れていることを特徴とする半導体装置。10. A semiconductor device having a first inner lead whose one end side is arranged on the surface of a semiconductor pellet, and a second inner lead whose one end side is arranged outside one side of the semiconductor pellet. One end side of the first inner lead is adhesively fixed by a first insulating film that is on the surface and is spaced apart from one side of the semiconductor pellet, and another end disposed outside the one side of the semiconductor pellet. A semiconductor device, wherein one end side of the second inner lead is bonded and fixed by a second insulating film.
に向かい合う前記第１絶縁性フィルムの一辺との間の距
離は、０．２［ｍｍ］以上に設定されていることを特徴
とする請求項１０に記載の半導体装置。11. The distance between one side of the semiconductor pellet and one side of the first insulating film facing the one side is set to 0.2 [mm] or more. The semiconductor device according to.
ード、第２インナーリード、第１絶縁性フィルム、第２
絶縁性フィルムの夫々は、樹脂封止体で封止されている
を特徴とする請求項１０又は請求項１１に記載の半導体
装置。12. The semiconductor pellet, first inner lead, second inner lead, first insulating film, second
The semiconductor device according to claim 10 or 11, wherein each of the insulating films is sealed with a resin sealing body.
ーリードの夫々の他端側は、前記半導体ペレットの一辺
と対向するその他辺に向かい合う樹脂封止体の一辺に沿
って配列された複数本のアウターリードの夫々に一体化
されていることを特徴とする請求項１２に記載の半導体
装置。13. The other ends of the first inner lead and the second inner lead are arranged along one side of the resin encapsulant facing the other side facing one side of the semiconductor pellet. The semiconductor device according to claim 12, wherein the semiconductor device is integrated with each of the outer leads.
ト主面上に配置された複数の第１リードと、その半導体
ペレット主面から離間して配置された複数の第２リード
とを有し、前記第１リードは主面に接着層を有する第１
フィルムを介して前記半導体ペレット主面上に接着固定
され、前記第２リードは主面に接着層を有する第２フィ
ルムに接着固定され、前記半導体ペレット主面上に接着
されている接着層はその半導体ペレットの端部より離間
して成ることを特徴とする樹脂封止型半導体装置。14. A semiconductor pellet, a plurality of first leads arranged on the main surface of the semiconductor pellet, and a plurality of second leads arranged apart from the main surface of the semiconductor pellet. The first lead has an adhesive layer on the main surface.
The second lead is adhesively fixed on the semiconductor pellet main surface via a film, the second lead is adhesively fixed to a second film having an adhesive layer on the main surface, and the adhesive layer adhered on the semiconductor pellet main surface is A resin-encapsulated semiconductor device, characterized in that it is separated from an end of a semiconductor pellet.
ムは一体化されて成ることを特徴とする請求項１４に記
載の樹脂封止型半導体装置。15. The resin-encapsulated semiconductor device according to claim 14, wherein the first film and the second film are integrated.
ト主面上に配置された複数の第１リードと、その半導体
ペレット主面から離間して配置された複数の第２リード
とを有し、前記第１リードは主面に接着層を有する第１
フィルムを介して前記半導体ペレット主面上に接着固定
され、前記第２リードは主面に接着層を有する第２フィ
ルムに接着固定されて成る樹脂封止型半導体装置であっ
て、温度サイクル試験で前記半導体ペレットに亀裂が生
じないことを特徴とする樹脂封止型半導体装置。16. A semiconductor pellet, a plurality of first leads arranged on the main surface of the semiconductor pellet, and a plurality of second leads arranged apart from the main surface of the semiconductor pellet. The first lead has an adhesive layer on the main surface.
A resin-encapsulated semiconductor device, which is adhered and fixed on the main surface of the semiconductor pellet through a film, and the second lead is adhered and fixed to a second film having an adhesive layer on the main surface. A resin-encapsulated semiconductor device, characterized in that the semiconductor pellet does not crack.
された、第１のリード群と、接着層を有する第２のフィ
ルムと固着された、第２のリード群と、から成る複数の
リードを有することを特徴とするリードフレームを用意
する工程と、前記第１リード群の夫々のリードの一端を
前記第１のフィルムの接着層を介し、その接着層が半導
体ペレットの端部に接しないように半導体ペレットに熱
圧着する工程と、前記半導体ペレットに設けられている
外部端子と前記第１のリード群のリードの一端とをワイ
ヤで電気的に接続する工程と、前記半導体ペレット、前
記ワイヤ、前記第１のリード群及び前記第２のリード群
とを樹脂封止する工程と、を有することを特徴とする半
導体装置の製造方法。17. A plurality of leads comprising a first lead group adhered to a first film having an adhesive layer and a second lead group adhered to a second film having an adhesive layer. And a step of preparing a lead frame, wherein one end of each lead of the first lead group is provided with an adhesive layer of the first film, and the adhesive layer does not contact an end portion of the semiconductor pellet. The thermocompression bonding to the semiconductor pellet, the step of electrically connecting the external terminal provided on the semiconductor pellet and one end of the lead of the first lead group with a wire, the semiconductor pellet, the wire And a step of resin-sealing the first lead group and the second lead group.
先端が固着され、半導体ペレットの主面上にその先端が
配置される第１のリード群と、接着層を有する第２のフ
ィルムにその先端が固着され、半導体ペレットから離間
してその先端が配置される第２のリード群とを有するこ
とを特徴とするリードフレーム。18. A first lead group, the tip of which is fixed to a first film having an adhesive layer, the tip being arranged on the main surface of a semiconductor pellet, and a second film having an adhesive layer. A lead frame having a second lead group in which the tip is fixed and the tip is arranged apart from the semiconductor pellet.
イミド系樹脂から成ることを特徴とする請求項１８に記
載のリードフレーム。19. The lead frame according to claim 18, wherein the adhesive layer and the film are made of a polyimide resin.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21483395A JP3555790B2 (en) | 1994-09-20 | 1995-08-23 | Semiconductor device |
| KR1019950028773A KR960012442A (en) | 1994-09-20 | 1995-09-04 | Semiconductor device and manufacturing method |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6-223888 | 1994-09-20 | ||
| JP22388894 | 1994-09-20 | ||
| JP21483395A JP3555790B2 (en) | 1994-09-20 | 1995-08-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08148518A true JPH08148518A (en) | 1996-06-07 |
| JP3555790B2 JP3555790B2 (en) | 2004-08-18 |
Family
ID=26520536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21483395A Expired - Fee Related JP3555790B2 (en) | 1994-09-20 | 1995-08-23 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3555790B2 (en) |
| KR (1) | KR960012442A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6518652B2 (en) | 2000-09-04 | 2003-02-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor package |
-
1995
- 1995-08-23 JP JP21483395A patent/JP3555790B2/en not_active Expired - Fee Related
- 1995-09-04 KR KR1019950028773A patent/KR960012442A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6518652B2 (en) | 2000-09-04 | 2003-02-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960012442A (en) | 1996-04-20 |
| JP3555790B2 (en) | 2004-08-18 |
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