JPH08147212A - Memory device - Google Patents

Abstract

PURPOSE: To easily provide continuous memory addresses when extending a memory by reading identification information corresponding to the extended memory and writing that information in the storage means of a memory control part under the control of a host device. CONSTITUTION: A CPU 10 not only accesses data through a DRAM control 13 but also extracts identification signals outputted from respective extended slots 123-12c and outputs the capacity of DRAM mounted on the respective extended slots 12a-12c to the DRAM control 13. Namely, the CPU 10 not only reads/writes data to a standard memory 11 and the DRAM mounted on the extended slots but also shares the memory control with the DRAM control 13. Then, an input/output port 14 receives the identification signals from the respective extended slots 12a-12c and outputs them to the CPU 10 and based on a signal showing the states of DRAM received from the CPU 10, the DRAM control 13 performs control so that the mounted DRAM can be the continuous addresses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device to which a plurality of additional memories can be attached / detached, and more particularly to a memory device capable of performing memory control without being affected by the number of additional memories.

[0002]

2. Description of the Related Art Generally, a memory device to which a plurality of additional memories can be attached and detached is known. This type of memory device has a plurality of expansion slots for detachably mounting the expansion memory, and the expansion memory having a desired capacity is mounted in the plurality of expansion slots.

By the way, in the conventional memory device using this extension slot, the capacity of the extension memory that can be installed in each extension slot is set in advance.

That is, there are some types of additional memory having different memory capacities, such as 4 Mbytes, 8 Mbytes, and 16 Mbytes, depending on the degree of integration.
The capacity of the installable additional memory is set in advance in each expansion slot.

However, if the user ignores the memory capacity set in this expansion slot and mounts an arbitrary expansion memory, the address space of this expansion memory becomes discontinuous and the mounted expansion memory can be used effectively. become unable.

FIG. 9A is a diagram showing an address map when an additional memory having the memory capacity set in the additional slot is installed, that is, when an additional memory having a proper memory capacity is installed, for example, 8 Mbytes. This corresponds to the case where the additional memory M1 and M2 each having a capacity of 8 Mbytes are attached to the additional slot S1 and the additional slot S2, respectively.

In this case, since the memory capacities of the extension memories M1 and M2 can be acquired without excess or deficiency, the extension memory M
1 and M2 can be used efficiently.

FIG. 9B is a diagram showing an address map when a memory having a smaller capacity than the memory capacity allocated to the additional slot is used as the additional memory. For example, an additional slot S1 for 8 Mbytes is provided. This is the case when the additional memory M3 having a capacity of 4 Mbytes is used.

In this case, since the additional memory does not have the memory capacity allocated to the additional slot, even if the legitimate additional memory M4 is used for the additional slot S2, the memory area where the memory addresses are discontinuous A1 will occur.

FIGS. 9 (c) and 9 (d) are diagrams showing an address map when an additional memory having a capacity larger than the memory capacity allocated to the additional slot is used, and FIG. 9 (c) shows , An additional slot S1 for 8 Mbytes, for example
9D shows the case in which the additional memory M5 having a capacity of 16 Mbytes is used, for example, in FIG.
Are shown respectively.

In this case, the additional memory has a larger capacity than the memory capacity allocated to the additional slot.
This results in wasted memory areas A2 and A3 that are not used.

As described above, when the memory capacity provided to each expansion slot does not match the memory capacity of the actually installed expansion memory, the memory addresses become discontinuous or the memory is wasted. Will occur.

Therefore, in Japanese Patent Laid-Open No. 4-336374, when a memory is mounted in each expansion slot, an identification signal for distinguishing the capacity and the configuration of the memory is output to the confirmation circuit, and the confirmation circuit A memory device configured to detect a mounted state of a memory based on an identification signal and acquire a continuous real storage area is disclosed.

Therefore, in this prior art, since the confirmation circuit is configured to receive the identification signal from each expansion slot, the confirmation circuit needs an input pin for inputting the identification signal output from each expansion slot. Become.

[0015]

However, when the input circuit for inputting each identification signal is provided in the confirmation circuit as in the prior art, the size and cost of the memory device are increased. .

That is, the number of input / output pins of the IC chip such as the confirmation circuit is basically determined depending on the size of the package, and even if the number of gates is small,
When the number of I / O pins is increased, it is necessary to change to a package with a larger size.

In particular, recent printers and the like are required to perform printing processing of image information having a huge amount of data and detailed color processing, and the memory capacity to be installed in the printer and the like is increasing. Therefore, the number of input pins becomes a serious problem when mounting a confirmation circuit that can meet the demand for such a memory.

Further, the number of signal lines used for outputting the identification signal from the expansion slot is determined by the type of memory that can be mounted in the expansion slot. The number of signal lines for outputting is increased, and the number of input / output pins required for the confirmation circuit is increased.

Further, recently, when manufacturing an IC chip, an ASIC in which a usable package is limited in advance.
(Apprication Specific IC) technology is often used, and there is a restriction that the number of input / output pins of the IC chip cannot be increased unnecessarily.

As described above, as a practical problem, the number of input / output pins of the IC chip such as the above-mentioned confirmation circuit has been a major limitation in the circuit configuration.

Therefore, according to the present invention, it is possible to solve the above problems and easily obtain continuous memory addresses when a memory is added without changing the number of input / output pins of the memory control unit for controlling the memory. An object is to provide a memory device.

[0022]

In order to achieve the above object, the present invention provides a storage means in which a plurality of extension memories are detachably attached and identification information including the respective capacities of the attached extension memories is stored. And a memory control unit for controlling the address space of the mounted additional memory to be continuous based on the identification information stored in the storage unit, and being accessed by the host device via the memory control unit. In the memory device according to the present invention, identification information generating means for generating the identification information corresponding to the attached additional memory when the additional memory is attached, and identification information generated by the identification information generating means are input / output to / from the host device. Identification information reading means to read through the port,
And an identification information writing unit for writing the identification information read by the identification information reading unit into the host device through the input / output port to the storage unit of the memory control unit under the control of the host device. And

[0023]

According to the present invention, the identification information generating means generates the identification information corresponding to the mounted additional memory, and the identification information reading means reads the generated identification information through the input / output port of the host device. The identification information writing means writes the read identification information in the storage means of the memory control unit under the control of the host device.

Therefore, continuous memory addresses corresponding to the expanded memory can be easily obtained without changing the number of input / output pins of the memory control unit for controlling the memory.

[0025]

[Embodiment] Three expansion slots are provided below, and one of the four types of dynamic RAM (D
One embodiment showing a case of mounting a RAM) will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the memory device 1 used in this embodiment.

As shown in FIG. 1, this memory device 1 is
CPU 10, standard memory 11, three expansion slots 12a, 12b and 12c, and DRAM control 1
3 and an input / output port 14.

The CPU 10 is connected to the DRAM control 13 and the input / output port 14 via the address bus 15 and the data bus 16 so that not only data access via the DRAM control 13 but also the expansion slots 12a to 12c. From the identification signal 20a output from
20c is taken out from the input / output port 14, and the capacity of the DRAM installed in each of the expansion slots 12a to 12c is DR.
Output to AM control 13.

That is, the CPU 10 is a DR installed in the standard memory 11 and the expansion slots 12a to 12c.
Not only reading / writing data from / to AM, but also DR
It plays a part in the memory control performed by the AM control 13.

The CPU 10 does not output the identification signals 20a to 20c received from the input / output port 14 to the DRAM control 13 as they are, but outputs each identification signal in the data format used by the DRAM control 13. ing.

The three expansion slots 12a to 12c are expansion slots provided for expanding the memory,
When expanding the memory, these additional memories 12a-12
One of three types of DRAMs of 4 Mbytes, 8 Mbytes, and 16 Mbytes is mounted on c.

The expansion slots 12a to 12c have a function of outputting 2-bit identification information indicating the memory capacity of the DRAM to the input / output port 14 when the DRAM is mounted. .

The DRAM control 13 is a DR installed in the standard memory 11 and the expansion slots 12a to 12c.
It is a control unit that controls so that the memory addresses of AM are continuous memory addresses.

Further, this DRAM control 13 is
Memory control is performed based on the signal indicating the state of the DRAM received from the CPU 10.

The input / output port 14 is connected to each expansion slot 12
The identification signals 20a to 20c output from a to 12c are received, and the identification signals 20a to 20c are output to the CPU 10 in response to a request for the identification signal from the CPU 10.

By using the memory device 1 having the above-mentioned configuration, the DRAM control 13 has the identification signals 20a-2 output from the respective expansion slots 12a-12c.
There is no need for an input pin for receiving 0c.

Next, detailed configurations of the DRAM control 13 and the input / output port 14 will be described. In addition,
Here, for convenience of description, items relating to processing of address data input from the CPU 10 via the address bus and identification signals input via the data bus will be mainly described.

FIG. 2 is a diagram showing a detailed configuration of the DRAM control 13.

As shown in FIG. 2, the DRAM control 13 includes a register 13a and an address decoder 13.
b, a timing generator 13c, a multiplexer 13d and the like.

The register 13a is used for each expansion slot 12a.
It is a storage unit that stores the memory capacity of the DRAMs installed in the ~ 12c, and stores three types of DRAMs with different memory capacities of 4 Mbytes, 8 Mbytes, and 16 Mbytes using 3-bit data for each expansion slot ing.

When the address decoder 13b receives the address data from the CPU 10, the address decoder 13b receives the register 13a.
The address data is decoded based on the memory capacity identification signal indicating the memory capacity of each DRAM stored in
The AM selection signal is output to the timing generator 13c.

The timing generator 13c is a CPU
10 read signal (RD) or write signal (WR) and D received from the address decoder 13b.
The multiplexer 13d based on the RAM selection signal
Address switching signal to RAS / CA
The S signal or the like is output to each DRAM.

The multiplexer 13d outputs a DRAM address to each DRAM based on the address switching signal output from the timing generator 13c and the address data output from the CPU 10.

DRAM control 1 having the above configuration
By using 3, the memory control can be performed based on the memory capacity stored in the register 13a.

Although not shown, the CPU 10 performs the DR
The data stored in the AM and the data accessed from the DRAM are transferred to and from the CPU 10 via the data bus.

Next, the data stored in the register 13a will be described with reference to FIG.

Here, (1, 0, 0) whose most significant bit is "1" is 16 Mbytes, and the second bit is "1".
(0, 1, 0) is associated with 8 Mbytes, and (0, 0, 1) whose least significant bit is '1' is associated with 4 Mbits, and each bit is all '0', that is, ( If it is 0, 0, 0), it means that the DRAM is not mounted in the expansion slot.

For this reason, 16 Mbytes of DRAM is mounted in the expansion slot 12a whose most significant bit is "1", and the expansion slot 1 whose second bit is "1".
2b is equipped with an 8-Mbyte DRAM, and the expansion slot 12c whose least significant bit is "1" has 4
It shows a case where an M-byte DRAM is mounted.

As described above, by configuring the three types of memory capacities of 4 Mbytes, 8 Mbytes, and 16 Mbytes to be distinguished by 3 bits, it is possible to easily perform the reading and writing process to the register 13a.

Next, the detailed structure of the input / output port 14 will be described.

FIG. 4 is a diagram showing a detailed configuration of the input / output port 14.

As shown in FIG. 4, this input / output port 14
Mainly comprises three bus drivers 14a, 14b and 1
4c, and each bus driver 14a-14
c receives the identification signals 20a to 20c output from the expansion slots 12a to 12c, and based on the selection signal from the CPU 10 input via the address bus 15,
The identification signals 20a to 20c are sequentially output to the data bus 16.

By using the input / output port 14 having the above configuration, the identification signals 20a to 20c output from the expansion slots 12a to 12c can be output to the CPU 10 via the data bus 16.

Here, for convenience of explanation, the case where each of the identification signals 20a to 20c is input by one signal line has been described, but when the identification signal is input by two or more lines, it corresponds. Requires a bus driver with a number of lines.

Next, the DRAM installed in each expansion slot
An identification circuit for identifying the memory capacity of will be described.

FIG. 5 is a diagram showing the configuration of an identification circuit added to the expansion slots 12a to 12c.

This identification circuit 21 is provided for each extension slot 12
a to 12c, and a pair of signal lines 2
It has a configuration in which 3a and 23b are pulled up.

Therefore, the DRAM 22 in which the signal lines 24a and 24b are both grounded is installed in the extension slots 12a to 12c.
, The potentials on the signal lines 23a and 23b become "low (0)", and the identification signal of (0, 0) is output to the input / output port 14.

If the DRAM 22 is not attached, the signal lines 24a and 24b are released, so that the signal line 2
The potentials at 3a and 23b are both "high (1)", and the identification signal of (1, 1) is output to the input / output port 14.

That is, the signal line 24a in the DRAM 22
By grounding at least one or both of 24b and 24b, the identification signal output from the identification circuit 21 can be represented by 2 bits.

Therefore, in this case, the signal lines 24a and 2 are
When both 4b are grounded, that is, (0, 0), the installed DRAM has a memory capacity of 4 Mbytes,
Only the signal line 24b is grounded, that is, (0,
In the case of 1), the memory capacity is 8 Mbytes, and in the case where only the signal line 24a is grounded, that is, in the case of (1, 0), the memory capacity is 16 Mbytes.

By providing the identification circuit 21 having the above-mentioned configuration in the extension slots 12a to 12c and providing a signal line corresponding to the memory capacity at a predetermined position of the DRAM 22, a DRAM is mounted in the extension slots 12a to 12c. , Identification signals 20a to 20 to the input / output port 14
c can be output.

As described above, in this embodiment, since the identification signal is output from the extension slot using the two signal lines, the input / output port 14 requires six bus drivers.

The DRAM control 13 is
Unlike the DRAM control 13 that requires simplification of processing, the identification circuit 21 distinguishes the memory capacity by 2 bits, while the memory capacity is represented by 3 bits. This is because it is necessary to reduce the number of signal lines for outputting the identification signal to 21.

As described above, since the identification circuit 21 and the DRAM control 13 distinguish the memory capacities in different modes, in the present embodiment, the CPU 10 is configured to convert the data indicating the memory capacities. .

FIG. 7 is a diagram showing a correspondence relationship between the bit indicating the memory capacity in the identification circuit 21 and the bit indicating the memory capacity in the DRAM control 13.

As shown in FIG. 7, the memory capacity of 4 Mbytes is (0, 0) in the identification circuit 21 and (0, 0, 1) in the DRAM control 13, so that the CPU
When the CPU 10 receives the identification signal (0, 0) from the input / output port 14, the CPU 10 outputs (0, 0, 1) to the DRAM control 13.

Similarly, the CPU 10 causes the identification signal (0,
If (1) is received, (0,1,0) is received, and if the identification signal (1,0) is received, (1,0,0) is received.
And (0, 0, 0) when the identification signal (1, 1) is received, the DRAM control 13
Output to.

In this way, each expansion slot 12a-12
the identification signals 20a to 20c output from the CPU 1 to the CPU 1
By configuring to output to the DRAM control 13 with 0 interposed, the memory capacity can be expressed according to the processing of each unit.

Next, the CPU 10 sets the memory capacity of the DRAM installed in each of the expansion slots 12a to 12c to D
A processing procedure for outputting to the RAM control 13 will be described.

FIG. 8 is a flow chart showing a processing procedure when the CPU 10 outputs the memory capacity of each DRAM to the DRAM control 13.

As shown in FIG. 8, the CPU 10 first identifies the identification signal 2 output from each of the expansion slots 12a to 12c.
0a to 20c are taken out from the input / output port 14 (step 801). That is, the CPU 10 uses the address bus 1
5 sequentially outputs the selection signal to the input / output port 14 via
An identification signal corresponding to the selection signal is input via the data bus 16.

Next, based on the identification signals 20a to 20c, the DRs installed in the expansion slots 12a to 12c
The memory capacity of each AM is determined (step 80).
2). Specifically, if the identification signal is (1, 1), DR
If the identification signal is (0, 0), it is determined that the 4 Mbyte DRAM is attached, and if the identification signal is (0, 1), the 8 Mbyte DRAM is determined. Is determined to be mounted, and if the identification signal is (1, 0), it is determined that a 16 Mbyte DRAM is mounted.

The DR installed in each expansion slot
When the memory capacity of the AM is confirmed, the data corresponding to the memory capacity is written in the register 13a provided inside the DRAM control 13 (step 803).

For example, if it is confirmed that the identification signal 20a output from the extension slot 12a is (0, 0), a 4 Mbyte DRAM is placed in the extension slot 12a.
Is recognized as being attached, and the data (0, 0, 1) representing the 4M bytes is written in a predetermined position of the register 13a.

By performing the above-mentioned series of processing, the memory capacity of the DRAM installed in each expansion slot is reduced to the DRAM.
The control 13 can be grasped.

As described above, in the present embodiment, the identification signals 20a to 20c indicating the memory capacities of the DRAMs installed in the expansion slots 12a to 12c are sent to the input / output port 14.
I / O port 14 that outputs the identification signal
Outputs an identification signal in response to a request from the CPU 10, and the CPU 10 causes each DRA corresponding to each identification signal to
Since the information indicating the state of M is output to the DRAM control 13, the D installed in the extension slot can be used without increasing the number of input pins of the DRAM control 13.
A continuous memory address corresponding to the RAM can be easily obtained.

Further, the mode of distinguishing the memory capacity by the identification circuit and the mode of distinguishing the memory capacity by the DRAM control 13 can be defined separately.

In the present embodiment, the identification circuits 21 and D
The case where the memory capacity of the RAM control 13 is expressed differently has been described, but the present invention is not limited to this, and the same data expression may be used to reduce the load on the CPU 10.

Further, in this embodiment, each expansion slot 12
The case of controlling only the memory capacity of the DRAMs mounted on a to 12c has been described, but the present invention is not limited to this, and a memory configuration or the like may be included.

[0081]

As described in detail above, the present invention provides
Generating identification information corresponding to the mounted additional memory, reading the identification information through the input / output port of the host device, and writing the read identification information in the storage means of the memory control unit under the control of the host device. Because I configured
The following effects can be obtained.

1) It becomes possible to eliminate the need to provide the memory control unit with input pins corresponding to the number of additional slots.

2) When adding a memory, it is possible to easily obtain consecutive memory addresses.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory device used in this embodiment.

FIG. 2 is a block diagram showing a detailed configuration of the DRAM control shown in FIG.

3 is a diagram showing an example of data stored in a register shown in FIG.

FIG. 4 is a diagram showing a detailed configuration of the input / output port shown in FIG.

5 is a diagram showing a configuration of an identification circuit provided in the extension slot shown in FIG.

FIG. 6 is a diagram showing a correspondence relationship between a state of a signal line added to a DRAM and a memory capacity.

FIG. 7 is a diagram showing a bit indicating a memory capacity in an identification circuit,
The figure which shows the correspondence with the bit which shows memory capacity in DRAM control.

FIG. 8 is a flowchart showing a processing procedure when the CPU shown in FIG. 1 notifies the DRAM control of the memory capacity of each DRAM.

FIG. 9 is a diagram showing a problem when a memory is added to an extension slot by using the conventional technique.

[Explanation of symbols]

1 memory device, 10 CPU, 11 standard memory, 12a to 12c expansion slot, 13 DRAM
Control, 14 I / O ports, 20a-20c
Identification signal, 21 identification circuit, 22 DRAM

Claims (1)

[Claims] 1. A plurality of extension memories are detachably attached, and a storage unit for storing identification information including respective capacities of the attached extension memories is provided, and based on the identification information stored in the storage unit. A memory device comprising a memory control unit for controlling the address space of the installed additional memory to be continuous, and the memory device being accessed by the host device via the memory control unit. Identification information generating means for generating the identification information corresponding to the additional memory; identification information reading means for reading the identification information generated by the identification information generating means via an input / output port of the host device; The identification information read by the host device via the input / output port by means of means for controlling the host device. A memory device, comprising: identification information writing means for writing in the storage means of the memory control unit.