JPH08146159A - Time counting device - Google Patents

Abstract

PURPOSE: To continuously count respective ones of time intervals in a range of the maximum enumerated value of a counter regardless of the overflow of the counter. CONSTITUTION: A counter 18 circularity counts reference clock signals, and a memory 26 stores the enumerated value of this counter with every counting time. A counter 22 whose maximum enumerated value is the same with the counter 18 is reset in a prescribed value with every counting time vicinity, and counts the reference clock signals. A memory 28 stores whether or not the counter 22 overflows in respective time interval periods at a counting point, and a processing circuit 30 finds respective time intervals of the counting point according to the content of the memories 26 and 28. When the storage content of the memory 28 shows overflow, the storage content of the corresponding memory 28 is invalidated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a time measuring device, in particular
The present invention relates to a time measuring device for continuously measuring each time interval between successively occurring measuring time points.

[0002]

2. Description of the Related Art When various events occur continuously, it is sometimes desired to measure the time intervals at which each event occurs sequentially. On the other hand, when measuring the time interval with the digital counter, the counter is reset to zero before the first event occurs,
After that, the counter counts the number of pulses of the reference clock signal generated between the first and second events. The count value is multiplied by the period of the reference clock signal to determine the time interval between the first and second events.

When a counter is used as described above, if three or more events occur, in order to measure the time interval between the second and third events, it is necessary to reset the counter after the second event occurs. is there. However, it takes time to reset the counter to zero, and since the counter cannot count the reference clock signal generated between the occurrence of the second event and the completion of the reset, the time interval after the second event occurs. Measurement error.

In the conventional example for solving such an error, the counter sequentially counts the reference clock signal, and the count value of the counter is stored in the storage means at each time when each event occurs (measurement time). The processing means sequentially reads the count values stored in the storage means, sequentially obtains the difference between the adjacent count values, and multiplies the difference by the clock period to measure continuous time intervals. In another conventional example, two counters are alternately used to measure the time interval. That is, the first counter counts the reference clock generated between the first and second event occurrence points, and resets the second counter to zero during that time. Next, the second counter counts the reference clock generated between the second and third event occurrence times,
Meanwhile, the first counter is reset to zero. Hereinafter, by repeating this operation, the time interval between each event can be continuously and accurately measured.

[0005]

However, in the conventional example in which a single counter is used to read the count value each time an event occurs, the cumulative value of the number of clocks at each time interval is the count value of the counter. Therefore, when the cumulative value reaches the maximum count value determined by the standard (bit number) of the counter, this counter overflows (overflows digits), and a new count is performed from zero. Therefore, when the event occurrence interval period includes overflow, the time interval cannot be determined from the count value of the counter because the number of overflow occurrences is unknown.
Therefore, the number of measurements in consecutive time intervals is limited. It is conceivable to separately provide a counter for counting the overflow of the counter, but this only increases the number of bits of the counter and has a similar problem. Further, in this method, since the maximum count value of the counter is divided, all the bits (maximum count value) of the counter cannot be used for measuring one time interval, and the resolution is reduced.

In the conventional case where two counters are alternately used,
A circuit for alternately resetting the two counters and a circuit for alternately reading the count values of the two counters while maintaining the measurement order are required, which complicates the circuit and its control.

Therefore, an object of the present invention is to provide a simple time measuring device capable of continuously measuring each time interval within the range of the maximum count value of the counter regardless of overflow of the counter.

[0008]

In the time measuring device of the present invention, the first counter cyclically counts the reference clock signal, and the first storage means stores the count value of the first counter at each measurement time point. The second counter, which has the same maximum count value as the first counter, is reset to a predetermined value at each measurement time point and counts the reference clock signal. The second storage means stores whether or not the second counter overflows during each interval period at the measurement time point, and the processing means stores the first and second intervals.
Each time interval at the time of measurement is obtained according to the stored contents of the storage means. Further, the address generating means generates an address signal which changes at every measurement time point and controls the addresses of the first and second storage means. At this time, the processing means invalidates the corresponding stored content of the first storage means when the stored content of the second storage means indicates an overflow.

[0009]

1 is a block diagram of a preferred embodiment of the present invention. The input terminal 10 is supplied with a pulse signal generated at each time when an event occurs (measurement time). The time interval between the pulse signals is the measurement target. The pulse signal from the input terminal 10 is supplied to the delay circuit 12 and the gate circuit 16. The gate circuit 16 passes only the pulse signal generated first after the start of measurement and supplies it to the reset terminal R of the first counter 18. This gate circuit 16 has an input terminal 1
An AND gate that receives a pulse signal from 0 at one input terminal, and a flip-flop that is set by the output signal of this AND gate and supplies the / Q output signal to the other input terminal of the AND gate. Can be configured.

The output signal of the delay circuit 12 is supplied to another delay circuit 14 and the write control terminal W of the memory (first storage means) 26. The output signal of the delay circuit 14 is the address
It is supplied to the clock terminal of the counter (address generating means) 20 and the load terminal 22 of the second counter 22. The reference clock generator 24 generates a reference clock signal having a stable frequency and supplies it to the clock terminals of the counters 18 and 22. The memory 26 receives the address signal from the address counter 20 at the address terminal A, and sequentially stores the count data of the counter 18 according to the signal from the write control terminal W. The memory (second storage means) 28 receives the address signal from the address counter 20 at the address terminal A.
Then, the overflow signal of the counter 22 is received by the data input terminal and the write control terminal W. Therefore, each time the counter 22 generates an overflow signal, writing is controlled by the overflow signal itself and the counter 22 stores the overflow signal. Processing circuit 3
Reference numeral 0 includes a microprocessor, a ROM storing a processing program, a RAM as a temporary storage device, an input device and an output device, and reads the stored contents of the memories 26 and 28 to perform processing at time intervals.

Next, the operation of FIG. 1 will be described with reference to the waveform chart of FIG. In the following description, in order to simplify the description, it is assumed that the decimal system is used, and the maximum count value of the counters 18 and 22 is also 99 (that is, 100 from 0 to 99 is counted). When the measurement is started, a pulse signal related to the event arrives at the input terminal 10. Also, the address counter 20 is reset to zero, the counters 18 and 22 start counting the reference clock, and the memory 2
The stored contents of 8 are reset to 0 at all addresses. The pulse at the input terminal 10 is delayed by the delay circuit 12 to become the pulse signal A. Since the delay circuit 12 delays all the pulse signals, the time interval of the delayed pulse signal A may be measured.

On the other hand, since the gate circuit 16 receives the pulse signal before being delayed and passes only the first pulse, its output signal becomes the pulse signal B. Pulse signal B
Note that occurs slightly before the first pulse of pulse signal A. Therefore, at the time T1 before the time T2 when the first pulse signal A reaches the memory 26,
The counter 18 is reset to zero. Further, since the delay time of the delay circuit 12 is set to the time required for resetting the counter 18, the counter 1 at the time T2.
The count value of 8 is zero. Therefore, at time T2,
The count value zero is stored in the address 0 of the memory 26.

If the count of the reference clock signal overflows between the start of measurement and the first pulse signal, the counter 22 stores an overflow signal at address 0 of the memory 28 at that time and overflows. If not, 0 is stored. At the time T3 after the delay time of the delay circuit 14 from the generation of the first pulse signal, the address counter 20 counts the pulse signal C and sets the address to 1. Therefore, the delay time of the delay circuit 14 is set so that the address is advanced after the count value of the counter 18 is written in the memory 26. On the other hand, the counter 22 loads a predetermined value at time T3. This is because the counter 18 still counts the clock signal between the time points T2 and T3, and it takes time for the counter 22 to load the predetermined value. The predetermined value starts from the time point T2. It is determined by the number of clocks of the reference clock signal generated until the load of 22 is completed. As a result, at each event occurrence (generation of the pulse signal A), the number of pulses counted by the counter 18, that is, not the count value of the counter 18 itself, but the count difference based on the time when the pulse signal A is generated, and the counter The count values of 22 match.

Next, when the pulse signal A is generated again at time T4, the memory 26 stores the count value of the counter 18 at that time, for example, 37 at address 1. If the counter 22 does not overflow between the time points T2 and T4, the content of the address 1 of the memory 28 remains 0.
This indicates that the counter 18 is not counting more than the maximum count value in the counting between the time points T2 and T4. The contents stored in the memories 26 and 28 are shown in FIG. At time T5, the address counter 20 advances the count by one, sets the address signal to 2, and the counter 22 loads a predetermined value.

When the pulse signal A is generated at time T6, the memory 26 causes the counter 18 to count the value at that time.
For example, 87 is stored at address 2. On the other hand, time point T4
Since the counter 22 does not overflow between T6 and T6, the stored content of the address 2 of the memory 28 remains 0. At time T7, the address signal from the address counter 20 becomes 3, and the counter 22 is again loaded with the predetermined value.

If the interval between time points T6 and T8 is equal to or greater than the product of the maximum count value of the counters 18 and 22 and the clock period, the memory 26 at time point T8 sets the count value of the counter 18 at that time, eg, 20 to the address 3. Remember. On the other hand, in the memory 28, at the time of overflow before time T8,
Store 1 at address 3. Hereinafter, the same operation is repeated.

The processing circuit 30 reads the contents of the memories 26 and 28 at the time when all the measurement of the time interval is completed or while measuring the time interval. Then, the processing circuit 30
Performs the following processing. That is, the content of the address 1 of the memory 28 is read, and the content is 0.
It is determined that the counter does not overflow between 2 and T4. Then, the difference (37-0) between the stored contents of the addresses 0 and 1 of the memory 26 is obtained and multiplied by the clock period to obtain the time interval between the time points T2 and T4. Similarly,
From the contents of address 2 of the memory 28, it is determined whether the difference between the contents of addresses 2 and 1 of the memory 26 is valid. When the storage content of the memory 28 is 1, like the address 3, an overflow occurred while writing the addresses 2 and 3 of the memory 26, so the difference between the contents of these addresses is invalid and the time difference between the time points T6 and T8 is determined. Judge that it does not correspond. These valid and invalid, and the time difference between valid and invalid are displayed on the output device or printed by the processing unit 30. Moreover, you may transmit these measurement results to another utilization circuit.

If the difference between the stored contents of the memory 26 is a negative value when the stored contents of the memory 28 is 0, indicating that there is no overflow, the count value of the counter 18 becomes zero from the maximum value. The difference can be easily calculated by considering that you have returned only once.

Although the preferred embodiment of the present invention has been described above, various changes and modifications can be made without departing from the spirit of the present invention. For example, the delay circuit 12 and the gate 16 may be removed. In that case, the storage content of the memory 26 does not become 0 at the address 0, but there is no problem in obtaining the difference from the storage content of the address 1.

[0020]

As described above, according to the time measuring device of the present invention, each time interval can be measured continuously within the range of the maximum count value of the counter regardless of the overflow of the counter. Also, the circuit connection can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram of a preferred embodiment of the present invention.

FIG. 2 is a timing diagram illustrating the operation of the present invention.

FIG. 3 is a diagram showing stored contents of a memory used in the present invention.

[Explanation of symbols]

 18 first counter 20 address generating means 22 second counter 26 first storing means 28 second storing means 30 processing means

Claims (3)

[Claims] 1. A first counter that cyclically counts a reference clock signal, and a first counter that stores the count value of the first counter at each measurement time point.
Storage means, a second counter that is reset to a predetermined value near the measurement time point, counts the reference clock signal, and has a maximum count value that is the same as the first counter, and the second counter during each interval period of the measurement time point. A time measuring device comprising a second storage means for storing whether or not the two counters have overflowed, and a processing means for obtaining each time interval at the measurement time point according to the stored contents of the first and second storage means. . 2. The time measuring method according to claim 1, further comprising address generating means for generating an address signal which changes every time the measurement is performed and controlling the addresses of the first and second storage means. apparatus. 3. The processing means invalidates the stored content of the corresponding first storage means when the stored content of the second storage means represents an overflow.
Time measuring device.