JPH08139098A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To form a contact hole of a dimension smaller than a PR limiting dimension in a simple process. CONSTITUTION: A gate oxide film 3, a field oxide film 2 and an N-type diffused layer 4 are formed on and in a P-type silicon substrate 1 to form an interlayer insulating film 5 on the films 3 and 2, a silicon layer 6 is formed on the film 5, a silicon nitride film 7 is formed on this layer 6 and this film 7 is etched on the basis of a mask of a prescribed pattern to form a mask consisting of the film 7 (a). The layer 6 exposed by the formation of this mask is thermally oxidized and a silicon oxide film 9, which is enlarged to the vicinity of the surface layer of the exposed surface of the layer 6 and a part of the layer 6, which is located under the mask consisting of the film 7, is formed (b). The mask consisting of the film 7 is removed and the layer 6 and the films 5 and 3 are etched in order using the film 9 as a mask (c), and after that, the film 9 is removed to form a contact hole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a contact hole having a diameter smaller than a critical dimension for forming an opening by photolithography is formed.

[0002]

2. Description of the Related Art With the high integration of semiconductor devices, the width of wiring formed on a substrate has become narrower, and therefore the contact hole diameter has become smaller. In a semiconductor device having a narrow wiring width and a small contact hole diameter, it is necessary to reduce the alignment margin between the contact hole and the wiring layer formed on the contact hole during processing. However, when reducing the alignment margin between the contact hole and the wiring layer, there are the following problems. That is, when the alignment margin is reduced, the wiring layer may not completely cover the contact hole portion when processing the wiring, and in this case, a slit is generated inside the contact hole. Furthermore, the possibility of short-circuiting between wirings due to misalignment increases.

As a measure against each of the above-mentioned problems, a method in which the opening of the contact hole is made smaller than the critical dimension of forming the opening by the photolithography technique (the limit of the resolution of PR) so that a large alignment margin can be obtained. Is proposed. Below, as specific examples of this method, JP-A-3-257963 and JP-A-4-257963.
Two methods disclosed in 196315 will be given.

First, the method disclosed in Japanese Patent Laid-Open No. 3-257963 will be described with reference to FIG.

FIG. 6 is a process chart showing the procedure of a method (polysilicon sidewall contact) for reducing the contact hole diameter by using a sidewall forming technique with polysilicon as a mask. The manufacturing state of each process is shown.

In the method disclosed in the above publication, first, a structure as shown in FIG. 6A is manufactured as follows. A field oxide film 102 and an N-type diffusion layer 104 formed by, for example, arsenic ion implantation are formed on a P-type silicon substrate 101, and a gate oxide film 103 is formed on the N-type diffusion layer 104. As the interlayer insulating film 105, a silicon oxide film is stacked up to a thickness of 4000 Å by, for example, a CVD method on the layer thus formed, and then the silicon layer 106 is formed on the interlayer insulating film 105 by about 20 nm.
Stack to a thickness of 00Å. Then, the photoresist 10
8 is used as a mask to etch the silicon layer 106 to form a region in the silicon layer 106 for forming a contact hole. The field oxide film 10 is used here.
2 and the gate oxide film 103 are formed by a normal LOCOS method.

Then, a silicon oxide film 116 is formed on the silicon layer 106 formed in the step of FIG.
The silicon oxide film 116 is laminated up to the thickness of Å (state of FIG. 6B), and the formed silicon oxide film 116 is anisotropically etched, whereby the silicon oxide film 11 is formed on the side wall of the silicon layer 106.
6 sidewalls are formed (state of FIG. 6C).

When the side wall of the silicon oxide film 116 is formed on the side wall of the silicon layer 106, subsequently, the side wall of the silicon oxide film 116 and the silicon layer 106 are used as a mask to form the interlayer insulating film 105 and the gate oxide film. The interlayer insulating film 1 is formed by etching 103.
05 and the gate oxide film 103, a contact hole is opened (state of FIG. 6D).

Through the steps shown in FIGS. 6A to 6D, the opening of the contact hole is made smaller than the limit of the resolution of PR, whereby a large alignment margin can be secured.

The above publication also discloses the following method different from the above method.

FIG. 7 is a process chart showing a procedure of a method (oxide film sidewall contact) of reducing a contact hole diameter by using a sidewall forming technique, which is different from the method shown in FIG. The state of each process is shown in c).

First, a structure as shown in FIG. 7A is manufactured as follows. On the P-type silicon substrate 201, as in the case of FIG. 6A, the field oxide film 20 is formed.
2 and an N-type diffusion layer 204 formed by ion implantation of arsenic, for example, and a gate oxide film 203 is formed on the N-type diffusion layer 204. On the layer thus formed,
As the interlayer insulating film 205, a silicon oxide film is stacked up to a thickness of 4000 Å by, for example, a CVD method, and then the interlayer insulating film 105 and the gate oxide film 203 are etched using the photoresist 208 as a mask to open contact holes. A region to be formed.

Next, after removing the photoresist 208 from the film manufactured as described above, a silicon oxide film 217 is laminated to a thickness of, for example, 1000 Å (FIG. 7B).
State). Further, the formed silicon oxide film 217 is anisotropically etched to form sidewalls of the silicon oxide film 217 on the sidewalls of the interlayer insulating film 105 and the gate oxide film 203 (state of FIG. 7C).

By the steps shown in FIGS. 7 (a) to 7 (c), the opening of the contact hole is made smaller than the limit of the resolution of PR, whereby a large alignment margin can be secured.

Next, the method disclosed in Japanese Patent Laid-Open No. 4-196315 will be briefly described.

FIG. 8 is a process chart showing the procedure of a method for reducing the contact hole diameter by tapering the polysilicon film based on the pattern of the resist film formed on the polysilicon film. The states of the respective steps are shown in a) to (e).

First, a structure as shown in FIG. 8A is manufactured as follows. An interlayer insulating film 305 of a silicon oxide film and a pair of electrode wirings 302a and 302b are formed on a P-type silicon substrate 301, and a polysilicon film 314 is deposited on the interlayer insulating film 305.

Subsequently, a resist 308 is applied onto the one produced as described above, and this is exposed and developed to form a predetermined resist pattern (FIG. 8).
(B) state). When the resist pattern is formed, based on this resist pattern, the polysilicon film 314 is formed.
Is taper-etched (state of FIG. 8C).

When the polycon silicon film 314 is taper-etched, the interlayer insulating film 305 is anisotropically etched on the basis of the taper-etched polycon silicon film 314 (state shown in FIG. 8D). The resist 308 is removed by O ₂ plasma (FIG. 8E).
State).

As described above, by tapering the polysilicon film 314 based on the pattern of the resist 308 formed on the polysilicon film 314, the opening diameter of the contact hole is smaller than the mask diameter of the resist 308. The contact holes can be made smaller than the resolution limit of PR, and a large alignment margin can be secured.

[0021]

However, each of the above-mentioned conventional methods for making the contact hole opening smaller than the PR resolution limit has the following problems.

(1) In the case of a method of reducing the contact hole diameter by using a side wall forming technique, a method of using a polysilicon side wall contact In order to make the side wall silicon film have a sufficient thickness, the side wall is formed. It is necessary to thicken the upper silicon layer 106 which serves as a mask at that time. in this way,
Since it is necessary to make the silicon layer 106 thick, there is a problem in that it takes time to perform processing such as formation and etching of the silicon layer.

When the silicon layer 106 becomes thicker, the wiring layer becomes thicker as a result, and an uneven surface is formed. Since the depth of focus is shallow for those intended for fine processing,
When the uneven surface is formed, there is a problem that a fine pattern cannot be formed on the layer formed thereon by exposure.

Furthermore, since the sidewalls are formed by etching back, it is difficult to control the dimensions.

Method Using Oxide Film Sidewall Contact Since the open area of the contact hole formed in the interlayer insulating film 105 shown in FIG. 7A has a PR critical dimension, a margin with the underlying wiring layer is provided. Otherwise, there is a problem that the wiring layer is damaged by etching.

Further, since the oxide film side wall is formed by etching back, there is a problem that control is difficult.

Furthermore, the interlayer insulating film 2 shown in FIG.
The diameter of the upper part of 05 is the same as the diameter formed on the photoresist 208, and as a result,
There is a problem that the margin between the wiring and the contact hole is not improved.

(2) In the method disclosed in Japanese Patent Laid-Open No. 4-196315, in which the contact hole diameter is reduced by etching the polysilicon film in a tapered shape, the polysilicon film is etched in a tapered shape to make contact. In the method of reducing the hole diameter, the number of steps required for forming the contact hole is smaller than that of the method using the polysilicon sidewall, but there are the following problems.

In order to make the contact hole diameter finer, it is necessary to thicken the polysilicon layer. Therefore, as in the case of the polysilicon sidewall contact, there is a problem in that it takes time to form the polysilicon layer, and perform processing such as etching. Further, as in the case of the polysilicon sidewall contact, there is a problem that a fine pattern cannot be formed by exposure due to the uneven surface caused by the thick wiring layer.

Further, since it is difficult to control the taper angle, there is a problem that the contact hole diameter cannot be accurately reduced.

Further, when the taper angle is reduced, the thickness of the polysilicon film at the taper end portion becomes small, so that the polysilicon film is simultaneously etched when the silicon oxide film is etched, and the contact hole diameter is designed. There is a problem that it is wider than the size. This problem becomes more prominent as the taper angle is made smaller, that is, as the contact hole diameter is made smaller.

An object of the present invention is to provide a semiconductor device manufacturing method capable of accurately forming a contact hole smaller than the PR critical dimension by a simple process.

[0033]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a gate oxide film,
A first step of forming an interlayer insulating film on a semiconductor substrate on which a field oxide film and a diffusion layer are formed by a predetermined procedure, and forming a silicon layer on the interlayer insulating film; and the first step. Forming a silicon nitride film on the silicon layer,
A second step of etching the silicon nitride film based on a mask having a predetermined pattern to form a mask of the silicon nitride film, and an exposed surface of the silicon layer exposed by the formation of the mask of the silicon nitride film in the second step. Third step of thermally oxidizing the silicon oxide film to form a silicon oxide film which is expanded to the vicinity of the surface layer of the exposed surface of the silicon layer and a part of the silicon layer under the mask of the silicon nitride film; The mask of the silicon nitride film formed in the step is removed, and the silicon oxide film formed in the third step is used as a mask, the silicon layer not covered with the silicon oxide film in the third step, and the interlayer insulation. A fourth step of sequentially etching the film and the gate oxide film and thereafter removing the silicon oxide film to form a contact hole.

The semiconductor device manufacturing method of the present invention is
An interlayer insulating film is formed on a semiconductor substrate on which a gate oxide film, a field oxide film and a diffusion layer are formed by a predetermined procedure.
A first step of forming a silicon layer on the interlayer insulating film,
A second step of forming a thin first silicon oxide film on the silicon layer formed in the first step, and silicon on the first silicon oxide film formed in the second step. A third step of forming a nitride film and etching the silicon nitride film based on a mask having a predetermined pattern to form a mask of the silicon nitride film, and exposing by the formation of the mask of the silicon nitride film in the third step The exposed surface of the first silicon oxide film is thermally oxidized to expose the silicon layer in the exposed surface region in the vicinity of the interface with the first silicon oxide film and in the silicon layer under the mask of the silicon nitride film. Fourth forming a second silicon oxide film partially enlarged
And the mask of the silicon nitride film formed in the third step, and the portion of the first silicon oxide film formed in the second step are removed, respectively, and formed in the fourth step. Using the second silicon oxide film as a mask, the silicon layer not covered with the second silicon oxide film in the fourth step, the interlayer insulating film, and the gate oxide film are sequentially etched, and then the silicon is removed. And a fifth step of removing the oxide film to form a contact hole.

The method for manufacturing a semiconductor device of the present invention is
An interlayer insulating film is formed on a semiconductor substrate on which a gate oxide film, a field oxide film and a diffusion layer are formed by a predetermined procedure.
Forming a first silicon nitride film on the interlayer insulating film;
Step, a second step of forming a silicon layer on the first silicon nitride film formed in the first step, and a second silicon nitride film formed on the silicon layer formed in the second step. Forming a film, etching the second silicon nitride film based on a mask having a predetermined pattern to form a mask of the silicon nitride film, and forming the mask of the silicon nitride film in the third step. A fourth step of thermally oxidizing the exposed surface of the silicon layer exposed by the step of forming a silicon oxide film expanded to the exposed portion and a part of the silicon layer under the mask of the first silicon nitride film; A mask of the silicon nitride film formed in the third step, and a portion of the silicon layer not oxidized in the fourth step are removed, and the silicon oxide film formed in the fourth step is masked. As above 1 of the silicon nitride film, are sequentially etching the interlayer insulating film and the gate oxide film, thereafter, characterized in that it comprises a fifth step of forming a contact hole by removing the silicon oxide film.

The method of manufacturing a semiconductor device according to the present invention is
An interlayer insulating film is formed on a semiconductor substrate on which a gate oxide film, a field oxide film and a diffusion layer are formed by a predetermined procedure.
Forming a first silicon nitride film on the interlayer insulating film;
Step, a second step of forming a silicon layer on the first silicon nitride film formed in the first step, and a thin film layer formed on the silicon layer formed in the second step. A third step of forming the first silicon oxide film, a second silicon nitride film is formed on the silicon oxide film formed in the third step, and the second silicon nitride film is masked in a predetermined pattern. A fourth step of forming a mask of a silicon nitride film by etching on the basis of: and thermally oxidizing an exposed surface of the first silicon oxide film exposed by the formation of the mask of the silicon nitride film in the fourth step. By the fifth step of forming a second silicon oxide film expanded to a part of the silicon layer under the mask of the silicon layer and the silicon nitride film under the exposed surface, and the fourth step. Mass of formed silicon nitride film , First formed in the third step
Part of the silicon oxide film and the part of the silicon layer not oxidized in the fifth step are removed respectively, and the first silicon oxide film formed in the fifth step is used as a mask to remove the first A sixth step of sequentially etching a silicon nitride film, an interlayer insulating film and a gate oxide film, and thereafter removing the silicon oxide film to form a contact hole
And the steps of.

The method of manufacturing a semiconductor device according to the present invention is
A first step of sequentially depositing a first silicon oxide film, a polysilicon film and a second silicon oxide film on a semiconductor substrate on which electrode wiring is formed to form an interlayer film, and a mask having a predetermined pattern as a base. And anisotropically etching the interlayer film formed in the first step by gas plasma capable of forming a selective protective film on the polysilicon film to form a first opening in the second silicon oxide film. A second step of forming
The polysilicon film exposed by the formation of the first opening in the second step is anisotropically etched by the gas plasma in the second step to form a protective film in the peripheral portion of the exposed surface. A third step of forming a second opening smaller than the first opening formed in the second step in the polysilicon film by performing etching in the central portion, and the gas plasma A fourth step of forming in the first silicon oxide film a third opening having the same size as the second opening formed in the second step by anisotropic etching by The second step is to remove the silicon oxide film of No. 2 and the protective film formed on the polysilicon film in the third step to form a contact hole.

In this case, the interlayer film formed on the semiconductor substrate may be formed by sequentially depositing the first silicon oxide film, the silicon nitride film and the second silicon oxide film.

Further, the gas used for the gas plasma may be CHF ₃ gas.

Further, the gas used for the gas plasma may be a mixed gas of CHF ₃ gas and CO gas.

[0041]

In the present invention, the silicon layer is thermally oxidized on the basis of a predetermined mask to form the mask of the silicon oxide film on the silicon layer, and the silicon layer is thermally oxidized to form the silicon oxide film. At this time, the oxide region generated by the diffusion of oxygen in the silicon layer is enlarged, so that a part of the silicon layer under the mask is made into an oxidized region by so-called bird's beak, so that an opening smaller than the size of the base mask is formed. The silicon oxide film which it has can be formed. Therefore, by sequentially etching the silicon layer or the silicon nitride film, the interlayer insulating film, and the gate oxide film using this silicon oxide film as a mask, a contact hole having an opening smaller than the size of the base mask can be formed. it can.

In the present invention, the first silicon oxide film, the polysilicon film and the second silicon oxide film are sequentially deposited to form an interlayer film, and the interlayer film is anisotropically and sequentially formed by gas plasma. In etching, formation of a protective film on a polysilicon film, which occurs when anisotropically sequentially etching a silicon oxide film and a polysilicon film by gas plasma, is used. That is, in the present invention, the exposed surface of the polysilicon film exposed by the formation of the first opening in the first silicon oxide film is etched as follows.

When the first silicon oxide film and the polysilicon film are anisotropically and sequentially etched by the gas plasma, a precursor of a protective film containing, for example, carbon or fluorine as a component is formed by gas decomposition in the gas plasma. To be done.
The formed precursor of the protective film is deposited as a protective film on the exposed surface of the polysilicon film because oxygen atoms do not exist in the film. The deposition of the protective film on the exposed surface of the polysilicon film is proceeding simultaneously with the etching. Therefore, in the peripheral part of the exposed surface of the polysilicon film, the formation of the protective film is more dominant than the etching, and the formation of the protective film progresses, and in the central part, the etching by ion bombardment is more dominant than the formation of the protective film. The etching progresses. As a result, a protective film is formed on the peripheral portion of the exposed surface of the polysilicon film, and only the central portion is etched. As a result, the first film formed on the second silicon oxide film is formed on the polysilicon film. A second aperture smaller than the aperture of is formed.

When the second opening is formed in the polysilicon film as described above, the third opening having the same size as the second opening formed in the polysilicon film is formed in the first silicon oxide film. An opening is formed. Therefore, if the second silicon oxide film is removed, a contact hole having a first opening, that is, an opening smaller than a predetermined mask is formed.

[0045]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a process diagram for explaining the steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
(D) to (d) show the manufacturing state of the semiconductor device in each step.

In the semiconductor device manufacturing method of this embodiment, first, the field oxide film 2 and the gate oxide film 3 are formed on the P-type silicon substrate 1 by the normal LOCOS method, and P
An N type diffusion layer 4 is formed between the silicon substrate 1 and the gate oxide film 3 by ion implantation of arsenic, for example. On the thus formed layer, a silicon oxide film is stacked up to a thickness of 4000 Å by, for example, a CVD method as the interlayer insulating film 5, and then the silicon layer 6 is deposited on the interlayer insulating film 5 up to a thickness of about 2000 Å. Stack. Further, a silicon nitride film 7 is laminated on the silicon layer 6 to a thickness of 7,000 Å, and thereafter, using the photoresist 8 formed by a predetermined mask pattern as a mask, the silicon nitride film 7 in the portion other than the contact holes is formed. Are removed by etching (state of FIG. 1A).

When the portion of the silicon nitride film 7 other than the portion where the contact hole is formed is removed by etching as described above, the surface of the lower silicon layer 6 is exposed. The exposed surface of the silicon layer 6 is thermally oxidized to form a silicon oxide film 9 having a thickness of 1000 Å, for example. The formed silicon oxide film 9 is formed under the film of the patterned silicon nitride film 7 due to so-called bird's beak in which an oxidized region generated by diffusion of oxygen is expanded inward from the edge of the silicon nitride film 7. It will be in the state of 1000 Å bite (state of Figure 1 (b)).

After the silicon oxide film 9 is formed on the surface of the silicon layer 6, the silicon nitride film 7 is removed, and the silicon layer 6 is etched using the silicon oxide film 9 as a mask. By this etching process, an opening region smaller than the patterned silicon nitride film 7 by the amount of the biting of the silicon oxide film 9 is formed in the silicon layer 6 (state of FIG. 1C).

When the open area is formed in the silicon layer 6,
Then, the silicon oxide film 9, the interlayer insulating film 5, and the gate oxide film 3 are sequentially removed by etching. By this process, an opening having the same diameter as the opening region formed in the silicon layer 6 is formed in the interlayer insulating film 5 and the gate oxide film 3 (state of FIG. 1D).

By the steps shown in FIGS. 1 (a) to 1 (d), it is possible to obtain a contact hole having a size smaller than the limit of the resolution of PR by the amount of the biting of the silicon oxide film 9. As a result, it becomes possible to secure a large alignment margin.

Next, a method of manufacturing the semiconductor device of the second embodiment of the present invention will be described.

FIG. 2 is a process chart for explaining each step of the method of manufacturing a semiconductor device according to the second embodiment of the present invention.
(A) to (d) show the manufacturing state of the semiconductor device in each step.

In the semiconductor device manufacturing method of this embodiment, the field oxide film 22, the gate oxide film 23, the N type diffusion layer 24, the interlayer insulating film 25 and the silicon layer 26 are formed on the P type silicon substrate 21 by the above-mentioned first method. It is formed in the same manner as in the embodiment. After that, the silicon oxide film 2 is formed on the silicon layer 26.
9 is laminated to a thickness of about 100Å by, for example, the CVD method. Further, the silicon nitride film 2 is formed on the silicon oxide film 29.
7 is stacked up to a thickness of 7000Å, and thereafter, as in the case of the first embodiment, the silicon nitride film 27 is removed by etching using the photoresist 28 formed by a predetermined mask pattern as a mask (FIG. State of a)). At this time, in this embodiment, since the silicon oxide film 29 is provided between the silicon layer 26 and the silicon nitride film 27, most of the damage to the silicon layer 26 due to the etching of the silicon nitride film 27 is caused. It never happens.

When the portions of the silicon nitride film 7 other than those for forming the contact holes are removed by etching as described above, the exposed surface of the silicon oxide film 29 is subsequently thermally oxidized. Then, since the thickness of the silicon oxide film 29 is as thin as 100 Å, the silicon layer 26 formed under the silicon oxide film 29 is oxidized and the silicon oxide film 29 is formed near the interface of the silicon layer 26 with the silicon oxide film 29. 'Is formed. The silicon oxide film 29 ′ formed here is under the patterned silicon nitride film 27, and in the same manner as in the case of the first embodiment, the oxidized region is inwardly intruded from the edge of the silicon nitride film 27. The film thickness is sufficiently larger than that of the silicon oxide film 29 (state of FIG. 2B).

When the silicon oxide film 29 'is formed in the vicinity of the interface between the silicon layer 26 and the silicon oxide film 29, the silicon nitride film 7 and the silicon oxide film 29 are successively removed by etching. Then, the portion of the silicon layer 26 that was not oxidized during the thermal oxidation is exposed.
The exposed silicon layer 26 is replaced with a silicon oxide film 29 '.
Is used as a mask for etching. By this etching process, an opening region is formed in the silicon layer 26, which is smaller than the patterned silicon nitride film 27 by the amount of the biting of the silicon oxide film 29 '(FIG. 2).
(State of (c)).

After the opening area is formed in the silicon layer 26, the silicon oxide film 29 ', the interlayer insulating film 25 and the gate oxide film 23 are successively removed by etching. By this process, an opening having the same diameter as the opening region formed in the silicon layer 26 is formed in the interlayer insulating film 25 and the gate oxide film 23 (state of FIG. 2D).

By the steps shown in FIGS. 2A to 2D, the opening of the contact hole can be made smaller than the limit of the resolution of PR by the amount of the biting of the silicon oxide film 29 '. As a result, it becomes possible to secure a large alignment margin.

Next, a method of manufacturing a semiconductor device according to the third embodiment of the present invention will be described.

FIG. 3 is a process chart for explaining each step of the method for manufacturing a semiconductor device according to the third embodiment of the present invention.
(A) to (d) show the manufacturing state of the semiconductor device in each step.

In the semiconductor device manufacturing method of this embodiment, first, the field oxide film 32 and the gate oxide film 33 are formed on the P-type silicon substrate 31 by the normal LOCOS method, and then the P-type silicon substrate 31 and the gate oxide film 33 are formed. Between,
For example, the N type diffusion layer 34 is formed by ion implantation of arsenic. The interlayer insulating film 35 is formed on the thus-formed one.
As an example, a silicon oxide film of 4000 Å is formed by the CVD method.
To a thickness of about 500 .ANG., And then a silicon nitride film 39 is stacked on the interlayer insulating film 35 to a thickness of about 500 .ANG.
Further, a silicon layer 36 is formed on the silicon nitride film 39 by 500.
The silicon nitride film 37 is laminated to a thickness of Å, and the silicon nitride film 37 is laminated to a thickness of 700 Å on the silicon layer 36. Then, using the photoresist 38 formed with a predetermined mask pattern as a mask, the silicon nitride film 37 in the portion other than the area where the contact hole is formed is removed by etching (state of FIG. 3A).

When the portion of the silicon nitride film 37 other than the contact hole is removed by etching as described above, subsequently, the exposed surface of the silicon layer 36 is thermally oxidized to form a silicon oxide film 36 '. . In the silicon oxide film 36 ′ formed at this time, as in the case of the first embodiment, in the sub-film portion of the patterned silicon nitride film 37, an oxidized region is inwardly intruded from the edge of the silicon nitride film 37. The state (state of FIG. 1B)).

After the silicon oxide film 36 'is formed, the silicon nitride film 37 is subsequently removed, and the silicon layer 36 exposed by the removal is removed by etching using the silicon oxide film 36' as a mask. Further, the silicon nitride film 39 is subsequently removed by etching using the silicon oxide film 36 'as a mask. As a result, an opening region is formed in the silicon nitride film 39, which is smaller than the patterned silicon nitride film 37 by the amount of the biting of the silicon oxide film 36 '(state shown in FIG. 3C).

When the opening region is formed in the silicon nitride film 39, the silicon oxide film 36 'and the interlayer insulating film 35 are subsequently formed.
And the gate oxide film 33 is sequentially removed by etching. By this process, an opening having the same diameter as the opening region formed in the silicon nitride film 39 is formed in the interlayer insulating film 35 and the gate oxide film 33 (FIG. 3D).
State).

By the steps shown in FIGS. 3A to 3D, it is possible to obtain a contact hole having a size smaller than the limit of the resolution of PR by the amount of the biting of the silicon oxide film 9. As a result, it becomes possible to secure a large alignment margin.

Next, a method of manufacturing the semiconductor device according to the fourth embodiment of the present invention will be described.

FIG. 4 is a process chart for explaining each step of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.
(A) to (d) show the manufacturing state of the semiconductor device in each step.

In the semiconductor device manufacturing method of this embodiment, the field oxide film 42, the gate oxide film 43, the N type diffusion layer 44, the interlayer insulating film 45, the silicon nitride film 49, and the silicon layer 46 are formed on the P type silicon substrate 41. It is formed by the same process as in the case of the above-mentioned third embodiment. Thereafter, the silicon oxide film 40 is laminated on the silicon layer 46 by, eg, CVD to a thickness of about 100 Å. Further, a silicon nitride film 47 is laminated on the silicon oxide film 40 to a thickness of 700 Å, and thereafter, using the photoresist 48 formed by a predetermined mask pattern as a mask, the silicon nitride film other than the part where the contact hole is formed is formed. Membrane 47
Are removed by etching (state of FIG. 4A). At this time, in this embodiment, the silicon layer 46 and the silicon nitride film 4 are
Since the silicon oxide film 40 is provided between the
Silicon layer 46 formed by etching silicon nitride film 47
Has little damage.

When the portions of the silicon nitride film 47 other than the contact holes are removed by etching as described above, the exposed surface of the silicon oxide film 40 is subsequently thermally oxidized. Then, since the film thickness of the silicon oxide film 40 is as thin as 100Å, the silicon layer 46 formed under the silicon oxide film 49 is oxidized and the silicon oxide film 40 is formed near the interface of the silicon layer 46 with the silicon oxide film 40. 'Is formed. The silicon oxide film 40 ′ formed here is under the patterned silicon nitride film 47 and has an oxidized region inwardly extending from the edge of the silicon nitride film 47 as in the case of the first embodiment. And the film thickness thereof is sufficiently larger than that of the silicon oxide film 40 (state of FIG. 4B).

After the silicon oxide film 40 'is formed, the silicon nitride film 47 is subsequently removed, and the silicon layer 46 exposed by the removal is removed by etching using the silicon oxide film 40' as a mask. Further, the silicon nitride film 49 is subsequently removed by etching using the silicon oxide film 40 'as a mask. As a result, an opening region is formed in the silicon nitride film 49, which is smaller than the patterned silicon nitride film 47 by the amount of the biting of the silicon oxide film 40 '(state of FIG. 4C).

After the opening region is formed in the silicon nitride film 49, the silicon oxide film 40 'and the interlayer insulating film 45 are subsequently formed.
The gate oxide film 43 is sequentially removed by etching. By this process, an opening having the same diameter as the opening region formed in the silicon nitride film 49 is formed in the interlayer insulating film 45 and the gate oxide film 43 (FIG. 4D).
State).

By the steps shown in FIGS. 4 (a) to 4 (d), it is possible to obtain a contact hole having a size smaller than the limit of the resolution of PR by the amount of the biting of the silicon oxide film 29 '. As a result, it becomes possible to secure a large alignment margin.

Next, a method of manufacturing a semiconductor device according to the fifth embodiment of the present invention will be described.

FIG. 5 is a process chart for explaining the steps of the method of manufacturing a semiconductor device according to the fifth embodiment of the present invention, in which (a)
(D) to (d) show the manufacturing state of the semiconductor device in each step.

In the method of manufacturing a semiconductor device of this embodiment, first, a pair of electrode wirings 52a,
52b is formed, and a silicon oxide film 53 which is an interlayer insulating layer is deposited on these. Then, the silicon oxide film 53
A polysilicon film 54 to be an intermediate layer is deposited thereon, and a silicon oxide film 55 is deposited again on the polysilicon film 54 to form an interlayer film (state of FIG. 5A).

When the structure as shown in FIG. 5A is manufactured as described above, the silicon oxide film 5 is subsequently formed.
5 is coated with a resist 56, and the coated resist 56 is exposed and developed using an appropriate mask to form a resist pattern (state of FIG. 5B).

After the resist pattern is formed on the silicon oxide film 55, anisotropic dry etching is performed using fluorocarbon gas with the resist 56 having the resist pattern as a mask. Anisotropic dry etching using fluorocarbon gas is performed using the resist 56 as a mask, and when this etching reaches the polysilicon film 54 of the intermediate layer (state of FIG. 5C),
A protective film containing carbon and fluorine as components is formed on the polysilicon film 54. That is, the precursor of the protective film containing carbon and fluorine as components is formed by gas decomposition in the fluorocarbon gas plasma. Such a phenomenon is a phenomenon observed when the oxide film is selectively etched with respect to polysilicon.

When the protective film precursor is formed as described above, the protective film precursor is bonded to oxygen atoms in the silicon oxide film 55 on the exposed surface of the silicon oxide film 55 to form a volatile substance (eg, , COF) and discharged. On the other hand, on the exposed surface of the polysilicon film 54, since oxygen atoms do not exist in the film, it is deposited as a protective film.

The deposition of the protective film on the exposed surface of the polysilicon film 54 is proceeding at the same time as the etching by the ion bombardment. Therefore, in the peripheral portion of the exposed surface of the polysilicon film 54 (in the vicinity of the edge of the etched silicon oxide film 55), the formation of the protective film is more dominant than the etching by ion bombardment, and the formation of the protective film progresses. In the area, the etching by ion bombardment becomes more dominant than the formation of the protective film, and the etching progresses. As a result, a protective film 57 is formed on the peripheral portion of the exposed surface of the polysilicon film 54, and only the central portion is etched, so that the silicon oxide film 53 is exposed in a diameter range smaller than the diameter of the resist pattern (FIG. 5). (State of (d)).

When the silicon oxide film 53 is exposed in a range of a diameter smaller than the diameter of the resist pattern,
Further anisotropic etching is performed to form a contact hole having a diameter smaller than that of the resist pattern (state of FIG. 5E).

Then, the resist 56 is removed by oxygen plasma. At this time, the protective film 57 deposited on the polysilicon film 54 is also removed at the same time (state of FIG. 5F). Then, the silicon oxide film 55 formed on the polysilicon film 54 is etched back and removed by anisotropic etching (state of FIG. 5G).

Through the steps shown in FIGS. 5A to 5G, a contact hole having a diameter smaller than the resist diameter is formed.

Although the polysilicon film 54 is used as the intermediate layer in this embodiment described above, the same effect can be obtained by using a silicon nitride film instead of the polysilicon film 54. That is, the same mechanism as the selective deposition of the protective film on the polysilicon film described above also occurs when the silicon nitride film is used, and the etching of the silicon nitride film is similar to the etching of the polysilicon film in the peripheral portion. Then, the protective film is deposited, and the etching is performed only in the central portion.

Further, as described above, in the case where the silicon nitride film is used for the intermediate layer, the silicon nitride film is an insulator, so that this silicon nitride film can be left as the intermediate layer. Therefore, it is not necessary to remove the silicon oxide film formed on the silicon nitride film, which makes it possible to further reduce the number of steps required for forming the contact hole.

In the following, as a specific experimental example of the present embodiment, an experimental example 1 using a polysilicon film as the intermediate layer and CHF ₃ gas as the fluorocarbon gas, a polycrystalline silicon film as the intermediate layer, and a fluorocarbon gas were used. As CHF ₃
An experimental example 2 using a mixed gas of gas and CO gas, and an experimental example 3 using a mixed gas of CHF ₃ gas and CO gas as a fluorocarbon gas using a silicon nitride film as an intermediate layer will be given. <Experimental Example 1> The magnetron RIE apparatus is set as follows. Supplying CHF ₃ gas at 100 sccm, etching pressure at 70 torr, and high frequency power voltage at 60
Set 0 w and lower electrode temperature to 10 ° C.

The magnetron RI set as described above
Using the E apparatus, the thickness of the polysilicon film 54 in FIG. 5 is 500Å and the thickness of the silicon oxide film 55 is 2500Å.
Etching is done. In this case, the diameter of the contact hole could be 0.3 μm with respect to the resist film diameter of 0.5 μm. <Experimental example 2> The magnetron RIE apparatus is set as follows. Supply the mixed gas of CHF ₃ gas and CO gas,
CHF ₃ / CO = 100/100 sccm, etching pressure set to 40 torr, high frequency power supply voltage 600
w, the lower electrode temperature is set to -30 ° C.

The magnetron RI set as described above
Using the E apparatus, as in Experimental Example 1, the polysilicon film 5
4 has a film thickness of 500Å and the silicon oxide film 55 has a film thickness of 25.
Etching that became 00Å. In this case, the diameter of the contact hole could be 0.26 μm with respect to the resist film diameter of 0.4 μm. <Experimental Example 3> The magnetron RIE apparatus is set as follows. Supply the mixed gas of CHF ₃ gas and CO gas,
With CHF ₃ / CO = 25/75 sccm, the etching pressure is set to 60 torr, the high frequency power supply voltage is set to 800 w, and the lower electrode temperature is set to 20 ° C.

Magnetron RI set as described above
Using the E apparatus, the silicon nitride film having a film thickness of 500Å and the silicon oxide film 55 having a film thickness of 2500Å are etched. In this case, the diameter of the contact hole could be 0.3 μm with respect to the resist film diameter of 0.5 μm.

[0089]

Since the present invention is configured as described above, it has the following effects.

The method according to any one of claims 1 to 4 has an effect that a contact hole smaller than the PR critical dimension can be accurately formed by a simple process.

Furthermore, since the thickness of the silicon layer provided on the interlayer insulating film can be reduced, the wiring layer can be reduced in thickness.

In the method according to any one of claims 5 to 8, in addition to the fact that a contact hole smaller than the PR critical dimension can be formed by a simple process, a conventional method of reducing the diameter of the contact hole by using a side wall. In comparison, there is an effect that the number of steps can be reduced by two steps.

Further, since the polysilicon layer forming the interlayer film is thin, the manufacturing time is shortened as compared with the conventional method of reducing the contact hole diameter by forming polysilicon in a tapered shape. The effect is that you can.

Further, since the protective film deposited on the polysilicon can be thickened, there is an effect that the diameter of the contact hole can be reduced with high accuracy.

[Brief description of drawings]

FIG. 1 is a process chart for explaining a process of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
(D) shows the manufacturing state of the semiconductor device in each step.

FIG. 2 is a process diagram for explaining each step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention, in which (a) to (d) show the manufacturing state of the semiconductor device in each step. ing.

FIG. 3 is a process diagram for explaining each step of the method for manufacturing a semiconductor device according to the third embodiment of the present invention, in which (a) to (d) show the manufacturing state of the semiconductor device in each step. ing.

FIG. 4 is a process diagram for explaining each step of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, in which (a) to (d) show the manufacturing state of the semiconductor device in each step. ing.

FIG. 5 is a process chart for explaining the steps of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention, in which (a) to (d) show the manufacturing state of the semiconductor device in each step. There is.

FIG. 6 is a process diagram showing a procedure of a method of using polysilicon as a mask and reducing a contact hole diameter by using a sidewall forming technique (polysilicon sidewall contact), and each step in (a) to (d). The manufacturing state of is shown.

7A to 7C are process charts showing a procedure of a method (oxide film sidewall contact) of reducing a contact hole diameter by using a sidewall formation technique, which is different from the method shown in FIG. The state of each process is shown.

FIG. 8 is a process chart showing the procedure of a method for reducing the contact hole diameter by tapering the polysilicon film based on the pattern of the resist film formed on the polysilicon film, The state of each process is shown in (e).

[Explanation of symbols]

1, 21, 31, 41 P-type silicon substrate 2, 22, 32, 42 Field oxide film 3, 23, 33, 43 Gate oxide film 4, 24, 34, 44 N-type diffusion layer 5, 25, 35, 45 Interlayer Insulating film 6,26,36,46 Silicon layer 7,27,37,39,47,49 Silicon nitride film 8,28,38,48 Photoresist 9,29,29 ', 36', 40,40 ', 53 , 55
Silicon oxide film 51 Silicon substrates 52a, 52b Electrode wiring 54 Polysilicon film 56 Resist

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/768

Claims (8)

[Claims] 1. A first step of forming an interlayer insulating film on a semiconductor substrate on which a gate oxide film, a field oxide film and a diffusion layer are formed by a predetermined procedure, and forming a silicon layer on the interlayer insulating film. A second step of forming a silicon nitride film on the silicon layer formed in the first step, and etching the silicon nitride film based on a mask having a predetermined pattern to form a mask of the silicon nitride film, The exposed surface of the silicon layer exposed by the formation of the mask of the silicon nitride film in the second step is thermally oxidized, and the vicinity of the surface layer of the exposed surface of the silicon layer and a part of the silicon layer under the mask of the silicon nitride film And a third step of forming a silicon oxide film enlarged to the step of removing the mask of the silicon nitride film formed in the second step, and using the silicon oxide film formed in the third step as a mask. Then, the silicon layer, the interlayer insulating film and the gate oxide film which are not covered with the silicon oxide film in the third step are sequentially etched, and then the silicon oxide film is removed to form a contact hole. 4. The method for manufacturing a semiconductor device, which comprises the step 4). 2. A first step of forming an interlayer insulating film on a semiconductor substrate on which a gate oxide film, a field oxide film and a diffusion layer are formed by a predetermined procedure, and forming a silicon layer on the interlayer insulating film. A second step of forming a thin first silicon oxide film on the silicon layer formed in the first step, and a second silicon oxide film formed in the second step on the first silicon oxide film. A third step of forming a silicon nitride film and etching the silicon nitride film based on a mask having a predetermined pattern to form a mask of the silicon nitride film; and a step of forming the mask of the silicon nitride film in the third step. The exposed surface of the exposed first silicon oxide film is thermally oxidized,
A second silicon oxide film is formed in the exposed surface region in the vicinity of the interface between the silicon layer and the first silicon oxide film and in a part of the silicon layer under the mask of the silicon nitride film. A fourth step, the mask of the silicon nitride film formed in the third step,
And the portions of the first silicon oxide film formed in the second step are removed respectively, and the second silicon oxide film formed in the fourth step is used as a mask to perform the second step in the fourth step. And a fifth step of sequentially etching the silicon layer not covered with the silicon oxide film, the interlayer insulating film and the gate oxide film, and thereafter removing the silicon oxide film to form a contact hole. A method for manufacturing a semiconductor device, comprising: 3. An interlayer insulating film is formed on a semiconductor substrate on which a gate oxide film, a field oxide film and a diffusion layer are formed by a predetermined procedure, and a first silicon nitride film is formed on the interlayer insulating film. A first step, a second step of forming a silicon layer on the first silicon nitride film formed in the first step, and a second silicon layer formed on the silicon layer formed in the second step. A third step of forming a nitride film and etching the second silicon nitride film based on a mask having a predetermined pattern to form a mask of the silicon nitride film; and a step of forming the mask of the silicon nitride film in the third step. A fourth step of thermally oxidizing the exposed surface of the silicon layer exposed by the formation to form a silicon oxide film expanded to the exposed portion and a part of the silicon layer under the mask of the first silicon nitride film.
And the mask of the silicon nitride film formed in the third step,
And the portions of the silicon layer not oxidized in the fourth step are removed respectively, and the first silicon nitride film, the interlayer insulating film and the gate oxide film are formed using the silicon oxide film formed in the fourth step as a mask. A fifth step of sequentially etching the films and thereafter removing the silicon oxide film to form a contact hole. 4. An interlayer insulating film is formed on a semiconductor substrate on which a gate oxide film, a field oxide film and a diffusion layer are formed by a predetermined procedure, and a first silicon nitride film is formed on the interlayer insulating film. A first step, a second step of forming a silicon layer on the first silicon nitride film formed in the first step, and a thin film thickness formed on the silicon layer formed in the second step. A third step of forming a first silicon oxide film, a second silicon nitride film is formed on the silicon oxide film formed in the third step, and the second silicon nitride film is formed into a predetermined pattern. A fourth step of forming a mask of a silicon nitride film by etching based on the mask, and the exposed surface of the first silicon oxide film exposed by the formation of the mask of the silicon nitride film in the fourth step is thermally oxidized. The above-mentioned A fifth step of forming a second silicon oxide film extended to a part of the silicon layer under the mask of the silicon nitride film and the silicon layer, and the mask of the silicon nitride film formed in the fourth step. ,
The portion of the first silicon oxide film formed in the third step and the portion of the silicon layer not oxidized in the fifth step are removed, and the second silicon layer formed in the fifth step is removed. A sixth step of sequentially etching the first silicon nitride film, the interlayer insulating film and the gate oxide film using the silicon oxide film as a mask, and thereafter removing the silicon oxide film to form a contact hole. A method of manufacturing a semiconductor device, comprising: 5. A semiconductor substrate on which electrode wiring is formed,
A first step of forming an interlayer film by sequentially depositing a first silicon oxide film, a polysilicon film and a second silicon oxide film; and an interlayer formed in the first step based on a mask of a predetermined pattern A second step of anisotropically etching the film by gas plasma capable of forming a selective protective film on the polysilicon film to form a first opening in the second silicon oxide film; The polysilicon film exposed by the formation of the first opening in the second step is anisotropically etched by the gas plasma in the second step to form a protective film in the peripheral portion of the exposed surface, A third step of performing etching in the central portion to form a second opening smaller than the first opening formed in the second step in the polysilicon film, and a difference due to the gas plasma Directional etching More, the third as large as the second hole formed in the second step
A fourth step of forming the opening in the first silicon oxide film, and removing the protective film formed on the polysilicon film in the second silicon oxide film and the third step to form a contact hole. And a fifth step of forming a semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the interlayer film formed on the semiconductor substrate is formed by sequentially depositing a first silicon oxide film, a silicon nitride film and a second silicon oxide film. A method of manufacturing a semiconductor device, which is characterized in that 7. The method of manufacturing a semiconductor device according to claim 5, wherein the gas used for the gas plasma is CHF ₃ gas. 8. The method of manufacturing a semiconductor device according to claim 5, wherein the gas used for the gas plasma is CHF ₃ gas and CO.
A method of manufacturing a semiconductor device, which is a mixed gas with a gas.