JPH0813037B2 - Speech path tester - Google Patents
Speech path testerInfo
- Publication number
- JPH0813037B2 JPH0813037B2 JP3964689A JP3964689A JPH0813037B2 JP H0813037 B2 JPH0813037 B2 JP H0813037B2 JP 3964689 A JP3964689 A JP 3964689A JP 3964689 A JP3964689 A JP 3964689A JP H0813037 B2 JPH0813037 B2 JP H0813037B2
- Authority
- JP
- Japan
- Prior art keywords
- test
- address
- value
- test packet
- line address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Monitoring And Testing Of Exchanges (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は通話路試験器に関し、特に交換機で使用され
る自己ルーチング型の通話路スイツチの試験を行なう通
話路試験器に関するものである。The present invention relates to a speech path tester, and more particularly to a speech path tester for testing a self-routing speech path switch used in an exchange.
従来の通話路試験器としては、空間分割交換機の通話
路であるクロスポイントを試験する通話路試験器や時分
割多重交換機の通話路であるタイムスイツチを試験する
通話路試験器が知られている。これらの通話路試験器
は、予めプロセツサ等で外部から被試験通話路スイツチ
へ所定の通話パスの設定制御を行ない、その後所定の入
線端子から信号を供給してこれを所定の出線端子で検出
することにより入線，出線間の導通を確認し、被試験通
話路スイツチの正否を判定するものであつた。As a conventional speech path tester, a speech path tester for testing a cross point which is a speech path of a space division exchange and a speech path tester for testing a time switch which is a speech path of a time division multiplex exchange are known. . These speech path testers control the setting of a prescribed speech path from the outside to the speech path switch under test with a processor in advance, and then supply a signal from a prescribed input line terminal to detect this at a prescribed output line terminal. By doing so, the continuity between the incoming and outgoing lines was confirmed, and the correctness of the speech path switch under test was determined.
最近の交換機の通話路としては上記のクロスポイント
やタイムスイツチの他の自己ルーチング型の通話路スイ
ツチ（自己ルーチング型の通話路スイツチについては日
経エレクトロニクス誌1988年１月11日号の132〜137ペー
ジ参照）も使用されているがこの通話路スイツチの試験
についても上述したと同様なものであつた。As a switching path of recent exchanges, other self-routing type switching paths other than the above-mentioned crosspoints and time switches (for self-routing type switching paths, see pages 132 to 137 of the January 11, 1988 issue of Nikkei Electronics magazine). However, the test of this channel switch was similar to that described above.
上述した従来の通話路試験器で、被試験通話路スイツ
チの入出線端子間のすべての通話パスの試験をするに
は、端子数の２乗の通話パスの設定制御が必要である。
従つて、この通話パスを外部から逐一設定して入線出線
間の導通を確認することは、端子数が多くなるほど試験
時間がかかつて、煩雑な手間を要するという問題があつ
た。In order to test all the communication paths between the input / output line terminals of the speech path switch under test with the above-mentioned conventional speech path tester, it is necessary to control the setting of the speech path that is the square of the number of terminals.
Therefore, there is a problem in that setting the call path from the outside one by one to check the continuity between the incoming and outgoing lines requires a longer test time as the number of terminals increases, and requires a complicated labor.
このような課題を解決するために本発明の通話試験器
は、入線数n,出線数ｎを有する被試験通話路スイツチの
第１の入線に出線アドレスの値と入線アドレスの値とが
ともに０に設定された第１の試験バケツトを送信し、こ
の試験パケツトを送信してから一定時間内に、被試験通
話路スイツチの第ｎの出線から出線アドレスの値と入線
アドレスの値とがともにｎ−１の値となる第２の試験パ
ケツトを受信したとき、試験正常終了と判定する通話路
試験器であつて、 被試験通話路スイツチの第１の入線に第１の試験パケ
ツトを送信する試験パケツト挿入回路と、 被試験通話路スイツチの第１〜第ｎ−１の出線にそれ
ぞれ接続され、この出線からの試験パケツトを受信し、
出線アドレスの値を１つ増加させて送信するｎ−１個の
出線アドレスインクリメント回路と、 被試験通話路スイツチの第ｎの出線に接続され、この
出線から上記の一定時間内に受信した試験パケツトが第
２の試験パケツトであるとき試験正常終了信号を出力
し、第２の試験パケツトではないときこの試験パケツト
をそのまゝ送信し、一定時間経過しても第２の試験パケ
ツトが受信できないとき試験異常終了信号を出力する試
験終了検出回路と、 この試験終了検出回路に接続され、受信した試験パケ
ツトの出線アドレスを０に設定して送信する出線アドレ
スリセツト回路と、 この出線アドレスリセツト回路に接続され、受信した
試験パケツトの入線アドレスを１つ増加させて送信する
入線アドレスインクリメント回路と、 上記ｎ−１個の出線アドレスインクリメント回路およ
び上記出線アドレスインクリメント回路にそれぞれ接続
され、受信した試験パケツトの出線アドレスの値と入線
アドレスの値とを入れ替えて送信するｎ個の第１のアド
レス入替回路と、 ｎ個の入線がそれぞれ上記ｎ個の第１のアドレス入替
回路に接続され、受信した試験パケツトの出線アドレス
に基づいて接続経路を選択し、ｎ個の出線の１つにこの
試験パケツトを送出する被試験通話路スイツチと同一構
成で正常が確認されている通話路スイツチと、 この通話路スイツチのｎ個の出線にそれぞれ接続さ
れ、受信した試験パケツトの出線アドレスの出線アドレ
スの値と入線アドレスの値とを入れ替えて被試験通話路
スイツチのｎ個にそれぞれ送信するｎ個の第２のアドレ
ス入替回路と、から構成されたものである。In order to solve such a problem, the speech tester of the present invention has the values of the outgoing line address and the incoming line address in the first incoming line of the speech path switch under test having the number of incoming lines n and the number of outgoing lines n. The first test bucket, both set to 0, is sent, and the value of the outgoing line address and the incoming line address of the nth outgoing line of the speech path switch under test are sent within a certain time after sending this test packet. When a second test packet in which both and n have a value of n-1 are received, the communication path tester judges that the test is completed normally, and the first test packet is connected to the first input line of the communication path switch under test. Is connected to the test packet insertion circuit for transmitting the test packet and the first to (n-1) th outgoing lines of the speech path switch under test, and receives the test packet from the outgoing line,
It is connected to the n-1 outgoing line address increment circuit that increases the outgoing line address value by 1 and sends it to the nth outgoing line of the speech path switch under test. When the received test packet is the second test packet, the test normal end signal is output, when it is not the second test packet, this test packet is transmitted as it is, and the second test packet is transmitted even after a certain time has elapsed. A test end detection circuit that outputs a test abnormal end signal when the test packet cannot be received; and an output line address reset circuit that is connected to the test end detection circuit and that sets the output line address of the received test packet to 0 and transmits the test packet. An in-line address increment circuit connected to the out-line address reset circuit, which increments the in-line address of the received test packet by one and transmits the result, and the n-1 outgoing lines N first address replacement circuits which are respectively connected to the address increment circuit and the above-mentioned outgoing line address increment circuit, and which exchange the outgoing line address value and incoming line address value of the received test packet for transmission, and n Incoming lines are respectively connected to the n first address replacing circuits, a connection route is selected based on the received outgoing line address of the test packet, and the test packet is sent to one of the n outgoing lines. A call path switch that has the same configuration as the test call path switch and has been confirmed to be normal, and the outgoing line address value and the incoming line of the outgoing line address of the received test packet that is connected to each of the n outgoing lines of this call line switch. And n number of second address exchange circuits for exchanging the address value and transmitting to the n number of speech path switches under test, respectively. A.
通話路試験器は、はじめに第１の試験パケツトを被試
験通話路スイツチの第１の入線に送信する。その後、こ
の試験パケツトの出線アドレスの値と入線アドレスの値
とを順次変えて被試験通話路スイツチの入線に送信し、
第１の試験パケツトを送信してから一定時間内に、被試
験通話路スイツチの第ｎの出線から送出される試験パケ
ツトを受信して、これが第２の試験パケツトであるとき
試験正常終了信号を出力する。The speech path tester first sends a first test packet to the first incoming line of the speech path switch under test. After that, the value of the outgoing line address and the value of the incoming line address of this test packet are sequentially changed and transmitted to the incoming line of the speech path switch under test,
When the test packet transmitted from the nth outgoing line of the speech path switch under test is received within a fixed time after the first test packet is transmitted and this is the second test packet, a test normal end signal Is output.
次に本発明について図面を参照して説明する。第１図
は本発明の通話路試験器の一実施例を示すブロツク図、
第２図はこの通話路試験に用いられる試験パケツトのフ
オーマツト、第３図は第２図の試験パケツトのデータを
変えてそれぞれ試験パケツトA,試験パケツトＢとして通
話路スイツチに入力した場合に、通話路スイツチの接続
経路選択動作を説明するルーチング説明図である。Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the speech path tester of the present invention.
Fig. 2 shows the format of the test packet used in this speech path test. Fig. 3 shows the data of the test packet in Fig. 2 changed and input as test packet A and test packet B into the speech path switch. It is a routing explanatory view explaining the connection route selection operation of a road switch.
まず第２図から説明する。同図の試験パケツトのフオ
ーマツトは、先頭に出線アドレス50次に入線アドレス60
で示されたヘツダ情報とその他の情報70から構成されて
いる。そしてこの試験パケツトは矢印の向きに、すなわ
ち出線アドレスから順に送信されるものである。First, FIG. 2 will be described. The format of the test packet in the figure is the outgoing line address 50 at the beginning and the incoming line address 60.
It is composed of the Hedsda information shown in and other information 70. Then, this test packet is transmitted in the direction of the arrow, that is, in order from the outgoing line address.
次に第３図について説明する。同図で試験される通話
路スイツチSW2は前掲文献に記述されているバンヤンス
イツチと呼ばれる自己ルーチング型の通話路スイツチで
ある。このスイツチSW2は出線アドレス50に基づいて、
出線を選択して通話パスを設定するものであり、入線橋
子L0,L1を切り替えるスイツチSW21、入線端子L2,L3を切
り替えるスイツチSW22、出線端子T0,T1を切り替えるス
イツチSW23、出線端子T2,T3を切り替えるスイツチSW24
から構成されている。そして、第２図で示された試験パ
ケツトのデータ、すなわち出線アドレス50の値を1,入線
アドレス60の値を０と設定した場合が第３図の試験パケ
ツトＡに相当するものであり、このとき通話路スイツチ
SW2の入線端子L0に入力された試験パケツトＡは、出線
アドレス50の値が１に設定されているので、スイツチSW
21,SW23を経由して出線端子T1から出力されるものであ
る。次に出線アドレス50の値を2,入線アドレス60の値を
２と設定した場合が試験パケツトＢに相当しこのとき通
話路スイツチSW2の入線端子L2に入力された試験パケツ
トＢは、出線アドレスの値が２に設定されているので、
スイツチSW22,SW24を経由して出線端子T2から出力され
るものである。Next, FIG. 3 will be described. The speech path switch SW 2 tested in the figure is a self-routing speech path switch called a Banyan switch described in the above-mentioned document. This switch SW 2 is based on the outgoing line address 50,
A call path is set by selecting an outgoing line, and a switch SW 21 for switching the incoming bridge L 0 , L 1 and a switch SW 22 for switching the incoming line terminals L 2 , L 3 and outgoing line terminals T 0 , T 1 Switch SW 23 for switching the switch and switch SW 24 for switching the output terminal T 2 and T 3.
It consists of The data of the test packet shown in FIG. 2, that is, the case where the value of the outgoing line address 50 is set to 1 and the value of the incoming line address 60 is set to 0 corresponds to the test packet A of FIG. At this time the call path switch
Since the value of the outgoing line address 50 of the test packet A input to the incoming line terminal L 0 of SW 2 is set to 1, the switch SW
It is output from the output terminal T 1 via 21 and SW 23 . Next, the case where the value of the outgoing line address 50 is set to 2 and the value of the incoming line address 60 is set to 2 corresponds to the test packet B. At this time, the test packet B input to the incoming line terminal L 2 of the communication path switch SW 2 is Since the value of the outgoing line address is set to 2,
It is output from the output line terminal T 2 via the switches SW 22 and SW 24 .
このように通話路スイツチSW2は、入力される試験パ
ケツトの出線アドレス50の内容に従つて出線端子T0〜T3
を選択するものであり、これによつて通話パスが設定で
きるのである。As described above, the communication path switch SW 2 outputs the outgoing line terminals T 0 to T 3 according to the contents of the outgoing line address 50 of the input test packet.
Is selected, which allows the call path to be set.
次に第１図について説明する。同図において、第３図
と相当部分については同一符号を付してその説明は省略
する。第１図において、１は試験器、２は試験入力端子
TINから試験パケツトを入力して試験開始を指示する試
験パケツト挿入回路、３は試験パケツト挿入回路２から
試験開始信号TRGを入力したのち、試験終了を検出して
端子TOUTから試験終了信号を出力する試験終了検出回
路、４は試験パケツトの出線アドレス50の値をリセツト
する出線アドレスリセツト回路、５は試験パケツトの入
線アドレス60の値を１つずつ増加させる入線アドレスイ
ンクリメント回路、６〜８はれぞれ出線アドレスの値を
１つずつ増加させる出線アドレスインクリメント回路、
９〜16はそれぞれ出線アドレス50の値と入線アドレス60
の値とを交換するアドレス入替回路である。そして試験
器１に組み込まれる通話路スイツチSW1は、正常性が確
認されているものでその内部構成は被試験通話路スイツ
チSW2と同等であり、内部にスイツチSW11,SW12,SW13,SW
14を有し入線端子P0〜P3,出線端子Q0〜Q3で構成されて
いるものである。Next, FIG. 1 will be described. In the figure, parts corresponding to those in FIG. 3 are assigned the same reference numerals and explanations thereof are omitted. In FIG. 1, 1 is a tester, 2 is a test input terminal
The test packet insertion circuit that inputs the test packet from T IN to instruct the start of the test, 3 inputs the test start signal TRG from the test packet insertion circuit 2, then detects the end of the test, and outputs the test end signal from the terminal T OUT. A test end detection circuit for outputting 4, an output line address reset circuit for resetting the value of the output line address 50 of the test packet, 5 for an input line address increment circuit for increasing the value of the input line address 60 of the test packet by one, 6 to 8. An outgoing line address increment circuit for increasing the outgoing line address value by one,
9 to 16 are the value of outgoing line address 50 and incoming line address 60 respectively
It is an address exchange circuit for exchanging the value of. The speech path switch SW 1 incorporated in the tester 1 has been confirmed to be normal, and its internal configuration is equivalent to that of the speech path switch under test SW 2, and the switches SW 11 , SW 12 , SW 13 are internally provided. , SW
It has 14 and is composed of input line terminals P 0 to P 3 and output line terminals Q 0 to Q 3 .
以上のように構成された通話路試験器についてその動
作を説明する。出線アドレス50の値と入線アドレス60の
値とがともに０に設定された第１の試験パケツトを試験
入力端子TINに入力すると試験パケツト挿入回路２はこ
の第１の試験パケツトを通話路スイツチSW2の入線端子L
0に送出する。通話路スイツチSW2は、L0端子から入力さ
れた試験パケツトの出線アドレスの値が０であるので、
このパケツトを出線端子T0にルーチングし、これと接続
された出線アドレスインクリメント回路６によつて出線
アドレス50の値をインクリメントして１とし、アドレス
入替回路９でアドレスの交換をして出線アドレス50の値
を0,入線アドレス60の値１としたのち、このパケツトを
通話路スイツチSW1の入線端子P0に送出する。通話路ス
イツチSW1は、このパケツトの出線アドレス50の値が０
であるので、出線端子Q0にルーチングし、これと接続さ
れたアドレス入替回路13でアドレスの交換をして出線ア
ドレス50の値を1,入線アドレス60の値を０としたのち、
このパケツトを試験パケツト挿入回路２を介して再び通
話路スイツチSW2の入線端子L0に送出する。通話路スイ
ツチSW2は、出線アドレス50の値が１であるので、出線
端子T1にルーチングする。The operation of the speech path tester configured as described above will be described. When the first test packet in which the value of the outgoing line address 50 and the value of the incoming line address 60 are both set to 0 is input to the test input terminal T IN , the test packet insertion circuit 2 switches the first test packet to the communication path switch. SW 2 input terminal L
Send to 0 . Since the output line address of the test packet input from the L 0 terminal of the call path switch SW 2 is 0 ,
This packet is routed to the output line terminal T 0 , the output line address increment circuit 6 connected to this packet increments the value of the output line address 50 to 1, and the address exchange circuit 9 exchanges the addresses. After setting the value of the outgoing line address 50 to 0 and the value of the incoming line address 60 to 1, the packet is sent to the incoming line terminal P 0 of the communication path switch SW 1 . The value of the outgoing line address 50 of this packet is 0 for the communication path switch SW 1.
Therefore, after routing to the output line terminal Q 0 and exchanging addresses in the address exchange circuit 13 connected to this, the value of the output line address 50 is set to 1, and the value of the input line address 60 is set to 0,
This packet is sent again to the line input terminal L 0 of the communication path switch SW 2 via the test packet insertion circuit 2. Since the value of the outgoing line address 50 is 1, the communication line switch SW 2 is routed to the outgoing line terminal T 1 .
このようにして、通話路スイツチSW2が出線端子T3ま
でルーチングを行なつたとき、これと接続される試験終
了検出回路３は、試験が終了したか否かの判断を行な
う。すなわち、この試験パケツトの出線アドレス50の値
が入線アドレス60の値と等しくなつたか否か、つまりこ
の通話路スイツチSW2の場合その値がそれぞれ３となつ
たか否かの判断をする。このとき、出線アドレスの値は
3,入線アドレスの値は０であるので、試験は終了してい
ないと判断し出線アドレスリセツト回路４で出線アドレ
ス50の値を０とし、さらに入線アドレスインクリメント
回路５で入線アドレス60の値をインクリメントして１と
したのち、これと接続されるアドレス入替回路12でアド
レスの交換を行なつて、出線アドレス50の値を1,入線ア
ドレス60の値を０として、このパケツトを通話路スイツ
チSW1の入線端子P3に送出する。通話路スイツチSW1は、
出線アドレスの値が１であるのでこのパケツトを出線端
子Q1にルーチングし、これと接続されるアドレス入替回
路14でアドレス交換を行なつて、出線アドレスの値を0,
入線アドレスの値を１としたのち、通話路スイツチSW2
の入線端子L1に送出するものである。In this way, when the communication path switch SW 2 has routed to the output terminal T 3 , the test end detection circuit 3 connected thereto determines whether or not the test has ended. That is, it is judged whether or not the value of the outgoing line address 50 of this test packet is equal to the value of the incoming line address 60, that is, whether or not the value is 3 in the case of this communication path switch SW 2 . At this time, the value of the outgoing line address is
3. Since the value of the incoming line address is 0, it is judged that the test is not completed, the value of the outgoing line address 50 is set to 0 by the outgoing line address reset circuit 4, and the value of the incoming line address 60 is further set by the incoming line address increment circuit 5. After incrementing to 1, the address exchange circuit 12 connected to this exchanges the addresses, sets the value of the outgoing line address 50 to 1 and the value of the incoming line address 60 to 0, and sets this packet to the call path. Send to switch SW 1 input terminal P 3 . Call path switch SW 1
Since the value of the outgoing line address is 1, this packet is routed to the outgoing line terminal Q 1 , and the address exchange circuit 14 connected to this packet exchanges the address to set the value of the outgoing line address to 0,
After setting the value of the incoming line address to 1, switch SW 2
It is sent to the input terminal L 1 of the.
こうして、最終的にこの試験パケツトは、通話路スイ
ツチSW2の入線端子L3に送出され、これが出線端子T3に
ルーチングされることの試験パケツトは、試験終了検出
回路３に送出され、この結果試験終了検出回路３は、こ
の試験パケツトの出線アドレス50の値と入線アドレス60
の値とがともに３に等しくなつたということで、通話路
スイツチSW2の全通話パスの試験が正常に終了したもの
とみなし、試験終了端子TOUTから試験正常終了信号を出
力する。Thus, finally the test packet is sent to the incoming line terminals L 3 of the speech path switch SW 2, which is the test packet of being routed to the outgoing line terminals T 3, is sent to the test end detecting circuit 3, the The result test end detection circuit 3 determines the value of the outgoing line address 50 and the incoming line address 60 of this test packet.
And the value of both are equal to 3, it is considered that the test of all the communication paths of the communication path switch SW 2 has been completed normally, and the test completion terminal T OUT outputs a test completion signal.
尚、試験終了検出回路３は、試験開始信号TRGを受信
したとき一定時間のタイマを起動する。この一定時間は
通話路スイツチSW2の試験が正常終了する時間に相当
し、この一定時間内に出線端子T3から送出される試験パ
ケツトの出線アドレス50の値と入線アドレス60の値とが
ともに等しく３となつたとき、試験終了出力端子TOUTに
試験正常終了信号を出力し、上記一定時間を経過しても
出線アドレス50の値と入線アドレス60の値とがともに等
しく３にならなかつたとき、試験異常終了信号を出力す
るものである。The test end detection circuit 3 starts a timer for a fixed time when receiving the test start signal TRG. This fixed time corresponds to the time when the test of the communication path switch SW 2 ends normally, and within the fixed time, the value of the outgoing line address 50 and the value of the incoming line address 60 of the test packet sent from the outgoing line terminal T 3 are compared. When both are equal to 3, a test normal end signal is output to the test end output terminal T OUT , and the value of the outgoing line address 50 and the value of the incoming line address 60 are both equal to 3 even after the lapse of the above fixed time. When this happens, a test abnormal end signal is output.
また本実施例の通話路試験器の場合、被試験用の通話
路スイツチSW2は、入線数4,出線数４とした通話路スイ
ツチを用いたが、一般的な入線数n,出線数ｎの通話路ス
イツチにも適用できることは明らかである。Further, in the case of the speech path tester of the present embodiment, the speech path switch SW 2 to be tested uses a speech path switch with 4 incoming lines and 4 outgoing lines. It is obvious that it can be applied to a channel switch of several n.
以上説明したことから明らかなように、本発明に係る
通話路試験器は、入線，出線数ともにｎ個の第１の通話
路スイツチの第１の入線に出線アドレスの値と入線アド
レス値とがともに０に設定された試験パケツトを送信
し、この試験パケツトを送信してから、一定時間内に、
上記第１の通話路スイツチの第ｎの出線から到来する試
験パケツトの受信を行ない、受信した試験パケツトの出
線アドレスの値と入線アドレスの値とがともにｎ−１の
値となつたとき試験正常終了と判断する構成となつてい
るので、プロセツサ等で逐一通話パスを設定して入線出
線間の導通を確認する煩雑な手間が省け、短時間に効率
の良い通話路スイツチの試験が行えるという効果があ
る。As is clear from the above description, in the speech path tester according to the present invention, the value of the outgoing line address and the incoming line address value are assigned to the first incoming line of the first speech path switch having n incoming lines and outgoing lines. Send a test packet with both 0 and 0 set, and within a certain time after sending this test packet,
When the test packet arriving from the nth outgoing line of the first communication path switch is received, and the value of the outgoing line address and the value of the incoming line address of the received test packet are both n-1. Since it is configured to judge that the test is completed normally, it is possible to save time and trouble by setting a call path one by one with a processor etc. and checking the continuity between the incoming line and the outgoing line. The effect is that it can be done.
第１図は本発明の通話路試験器の一実施例を示すブロツ
ク図、第２図はこの通話路試験に使用される試験パケツ
トのフオーマツト、第３図は通話路スイツチのルーチン
グ説明図である。 １……試験器、２……試験パケツト挿入回路、３……試
験終了検出回路、４……出線アドレスリセツト回路、５
……入線アドレスインクリメント回路、６〜８……出線
アドレスインクリメント回路、９〜16……アドレス入替
回路、SW1,SW2……通話路スイツチ。FIG. 1 is a block diagram showing an embodiment of the speech path tester of the present invention, FIG. 2 is a format of a test packet used in this speech path test, and FIG. 3 is an explanatory view of a speech path switch routing. . 1 ... Tester, 2 ... Test packet insertion circuit, 3 ... Test end detection circuit, 4 ... Outline address reset circuit, 5
...... Incoming line address increment circuit, 6 to 8 ... Outgoing line address increment circuit, 9 to 16 ... Address replacement circuit, SW 1 , SW 2 ...... Call path switch.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０４Ｑ 1/24 3/00 9466−5Ｋ Ｈ０４Ｌ 11/20 Ｄ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H04Q 1/24 3/00 9466-5K H04L 11/20 D
Claims (1)
されるバケツトの出線アドレスに従つて入線と出線との
間の接続経路が一義適に決定される第１と通話路スイツ
チを被試験対象とし、出線アドレスの値と入線アドレス
の値とがともに０に設定された第１の試験バケツトを前
記入線に送信してから一定時間内に前記出線から出線ア
ドレスの値と入線アドレスの値とがともにｎ−１の値と
なる第２の試験パケツトを受信したとき、前記第１の通
話路スイツチの正常を判定する通話路試験器であつて、 前記第１の通話路スイツチの第１の入線に前記第１の試
験パケツトを送信する試験パケツト挿入回路と、 前記第１の通話路スイツチの第１〜第ｎ−１の出線にそ
れぞれ接続され、この出線からの試験パケツトを受信し
て前記出線アドレスの値を１つ増加させて送信するｎ−
１個の出線アドレスインクリメント回路と、 前記第１の通話路スイツチの第ｎの出線に接続され、こ
の出線から前記一定時間内に受信した試験パケツトが前
記第２の試験パケツトであるとき試験正常終了信号を出
力し、第２の試験パケツトではないときこの試験パケツ
トをそのまま送信し、この一定時間経過後第２の試験パ
ケツトが受信できないと試験異常終了信号を出力する試
験終了検出回路と、 この試験終了検出回路に接続され、受信した試験パケツ
トの前記出線アドレスを０に設定して送信する出線アド
レスリセツト回路と、 この出線アドレスリセツト回路に接続され、受信した試
験パケツトの前記入線アドレスを１つ増加させて送信す
る入線アドレスインクリメント回路と、 前記ｎ−１個の出線アドレスインクリメント回路および
前記入線アドレスインクリメント回路にそれぞれ接続さ
れ、受信した試験パケツトの前記出線アドレスの値と入
線アドレスの値とを入れ替えて送信するｎ個の第１のア
ドレス入替回路と、 ｎ個の入線がそれぞれ前記ｎ個の第１のアドレス入替回
路と接続され、受信した試験パケツトの前記出線アドレ
スの値に基づいて接続経路を選択し、ｎ個の出線の１つ
にこの試験パケツトを送出する前記第１の通話路スイツ
チと同一構成で正常が確認されている第２の通話路スイ
ツチと、 この第２の通話路スイツチのｎ個の出線にそれぞれ接続
され、受信した試験パケツトの前記出線アドレスの値と
入線アドレスとの値を入れ替えて前記第１の通話路スイ
ツチのｎ個の入線にそれぞれ送信するｎ個の第２のアド
レス入替回路と を備えてなる通話路試験器。1. A first and call path switch in which both the number of incoming lines and the number of outgoing lines are n, and the connection route between the incoming line and the outgoing line is uniquely determined according to the outgoing line address of the input bucket. Is the object to be tested, and the first test bucket in which both the value of the outgoing line address and the value of the incoming line address are set to 0 is sent to the incoming line within a certain time after the outgoing line from the outgoing line. A speech path tester for determining the normality of the first speech path switch when a second test packet in which both the value and the value of the incoming address are the value of n-1 is received. A test packet insertion circuit for transmitting the first test packet to the first incoming line of the speech path switch, and the first to (n-1) th outgoing lines of the first speech path switch, which are respectively connected to the outgoing line. After receiving the test packet from The increase one transmits n-
One output line address increment circuit and the test packet connected to the nth output line of the first communication path switch and received from the output line within the certain time are the second test packets. A test end detection circuit that outputs a test normal end signal, transmits this test packet as it is when it is not the second test packet, and outputs a test abnormal end signal when the second test packet cannot be received after a certain period of time elapses. , An output line address reset circuit which is connected to the test end detection circuit and which sets the output line address of the received test packet to 0 and transmits, and a test line which is connected to the output line address reset circuit and which receives the received test packet. An incoming line address increment circuit that increments the entry line address by one, and transmits the n-1 outgoing line address increment circuit; N first address replacement circuits which are respectively connected to the incoming line address increment circuits and which exchange the value of the outgoing line address and the value of the incoming line address of the received test packet for transmission, and n incoming lines respectively. Connected to the n first address replacement circuits, selecting a connection route based on the value of the output line address of the received test packet, and transmitting the test packet to one of the n output lines. A second speech path switch having the same configuration as the first speech path switch and confirmed to be normal, and the outgoing line of the received test packet connected to each of the n outgoing lines of the second speech path switch. A call path tester comprising n second address replacement circuits for exchanging the value of the address and the value of the incoming line address and transmitting to each of the n incoming lines of the first call path switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3964689A JPH0813037B2 (en) | 1989-02-20 | 1989-02-20 | Speech path tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3964689A JPH0813037B2 (en) | 1989-02-20 | 1989-02-20 | Speech path tester |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02218239A JPH02218239A (en) | 1990-08-30 |
| JPH0813037B2 true JPH0813037B2 (en) | 1996-02-07 |
Family
ID=12558847
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3964689A Expired - Fee Related JPH0813037B2 (en) | 1989-02-20 | 1989-02-20 | Speech path tester |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0813037B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0504537A1 (en) * | 1991-03-22 | 1992-09-23 | International Business Machines Corporation | Method and apparatus for the testing and evaluation of geographically distributed telecommunication networks |
| JP7547789B2 (en) * | 2020-06-01 | 2024-09-10 | 株式会社デンソー | Repeater |
-
1989
- 1989-02-20 JP JP3964689A patent/JPH0813037B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02218239A (en) | 1990-08-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |