JPS6240897B2 - - Google Patents
Info
- Publication number
- JPS6240897B2 JPS6240897B2 JP54129525A JP12952579A JPS6240897B2 JP S6240897 B2 JPS6240897 B2 JP S6240897B2 JP 54129525 A JP54129525 A JP 54129525A JP 12952579 A JP12952579 A JP 12952579A JP S6240897 B2 JPS6240897 B2 JP S6240897B2
- Authority
- JP
- Japan
- Prior art keywords
- mfc
- signal
- backward
- mfc signal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000008054 signal transmission Effects 0.000 claims description 13
- 238000001514 detection method Methods 0.000 claims description 10
- 230000011664 signaling Effects 0.000 claims description 7
- 230000005540 biological transmission Effects 0.000 claims description 3
- 238000012360 testing method Methods 0.000 description 11
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 208000036828 Device occlusion Diseases 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/22—Arrangements for supervision, monitoring or testing
- H04M3/26—Arrangements for supervision, monitoring or testing with means for applying test signals or for measuring
- H04M3/28—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor
- H04M3/32—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for lines between exchanges
- H04M3/326—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for lines between exchanges for registers and translators
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
- Monitoring And Testing Of Exchanges (AREA)
Description
【発明の詳細な説明】
本発明は、時分割交換機において、デイジタル
式のコンペルド多周波信号（以下、MFC信号と
いう。）を送受するMFC信号装置の障害検出方式
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a failure detection method for an MFC signal device that transmits and receives digital comperdo multifrequency signals (hereinafter referred to as MFC signals) in a time division switch.
一般に、デイジタル式のMFC信号装置は、読
取り専用メモリ（以下、ROMという。）を使用し
た多重分配方式のものが基本となつているため、
その障害時の影響の波及範囲が非常に大きい。 Generally, digital MFC signal devices are based on a multiplex distribution method using read-only memory (hereinafter referred to as ROM).
The scope of the impact of such a failure is extremely large.
したがつて、その障害発生時には、可及的速や
かに、これを検出して予備装置への切替が必要で
ある。 Therefore, when a failure occurs, it is necessary to detect it and switch to a backup device as soon as possible.
従来の障害検出方式は、周期的に、フオアワー
ド信号装置とバツクワード信号装置との間を接続
して送受信符号をチエツクするようにしていた。 Conventional fault detection methods periodically check the transmitted and received codes by connecting forward and backward signaling devices.
ここで、フオアワード信号装置には、フオアワ
ード信号送出回路とバツクワード信号受信回路を
含み、バツクワード信号装置には、バツクワード
信号送出回路とフオアワード信号受信回路とを含
むものである。 Here, the forward signal device includes a forward signal sending circuit and a backward signal receiving circuit, and the backward signal device includes a backward signal sending circuit and a forward signal receiving circuit.
この場合、フオアワード信号装置を試験するた
めには、バツクワード信号装置も試験用に確保し
なければならず、切分けが困難であつた。 In this case, in order to test the forward signal device, the backward signal device must also be secured for testing, making it difficult to isolate.
また、信号処理中のタイムアウト呼の統計をと
るという方法もあるが、相手局装置の障害、線路
障害なども考えられるので、やはり、障害部位の
切分けが複雑となる。 Another method is to collect statistics on calls that time out during signal processing, but this also makes it complicated to isolate the location of the fault, as failures in the partner station equipment, line faults, etc. are also possible.
本発明の目的は、迅速、かつ、確実に障害を検
出することができるMFC信号装置の障害検出方
式を提供することにある。 An object of the present invention is to provide a fault detection method for an MFC signal device that can quickly and reliably detect faults.
本発明の特徴は、MFC信号装置の送信側、受
信側を、それぞれ、対となる入ハイウエイ、出ハ
イウエイを通して時分割スイツチへ収容し、外部
からの指示によりバツクワードMFC信号送出、
フオアワードMFC信号送出の両者を可能とし、
フオアワード信号装置試験時には、バツクワード
MFC信号送出指示を与えて受信側にそのバツク
ワードMFCを受信せしめ、また、バツクワード
信号装置試験時は、フオアワードMFC信号送出
指示を与えて受信側にそのフオアワードMFC信
号を受信せしめ、かつ同一MFC信号装置の送信
側、受信側を時分割スイツチによつて折返し接続
して信号の送受信を行わしめ、その照合を行いう
るごとくするMFC信号装置の障害検出方式にあ
る。 A feature of the present invention is that the transmitting side and receiving side of the MFC signal device are accommodated in a time division switch through a pair of incoming and outgoing highways, respectively, and a backward MFC signal is sent out in response to an external instruction.
Enables both forward and forward MFC signal transmission,
When testing the forward word signal equipment, use the backward
Give an MFC signal transmission instruction to make the receiving side receive the backward MFC signal, and when testing a backward signal device, give a forward MFC signal sending instruction to make the receiving side receive the forward word MFC signal, and use the same MFC signal device. This is a fault detection method for an MFC signal device that connects the transmitting side and receiving side of the MFC back and forth using a time division switch to transmit and receive signals, and to perform verification.
以下、本発明の実施例を図面に従つて説明す
る。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は、本発明に係るMFC信号装置の障害
検出方式の一実施例のブロツク図である。 FIG. 1 is a block diagram of an embodiment of a fault detection method for an MFC signaling device according to the present invention.
ここで、１００は、MFC信号装置、１０１
は、外部装置に係る中央制御装置CPU（図示省
略。）からの信号送出指示データDATAに基づい
てMFC信号を送出する信号送出回路、１０２
は、必要数設けられ、MFC信号を受信する信号
受信回路、１０３は、信号送出回路１０１に対す
るマルチプレクサ、１０４は、信号受信回路に対
するデマルチプレクサ、２０１は、MFC信号送
出用の入ハイウエイ、２０２は、MFC信号受信
用の出ハイウエイ、２０３，２０４は、トランク
用の入ハイウエイ、出ハイウエイ、３００は、時
分割スイツチ、３０１は、出トランクである。 Here, 100 is an MFC signal device, 101
102 is a signal sending circuit that sends an MFC signal based on signal sending instruction data DATA from a central control unit CPU (not shown) related to an external device;
103 is a multiplexer for the signal sending circuit 101; 104 is a demultiplexer for the signal receiving circuit; 201 is an input highway for sending MFC signals; 202 is a signal receiving circuit for receiving the MFC signal; Outgoing highways 203 and 204 are for receiving MFC signals; 203 and 204 are incoming and outgoing highways for trunks; 300 is a time division switch; and 301 is an outgoing trunk.
信号送出回路１０１は、指示されたMFC信号
を入ハイウエイ２０１に設けられたMFC信号送
出用タイムスロツトに送出すべく多重制御をす
る。 The signal sending circuit 101 performs multiplex control to send the instructed MFC signal to an MFC signal sending time slot provided on the incoming highway 201.
また、信号受信回路１０２は、バツクワード信
号受信用信号受信回路１０２−１とフオアワード
信号受信用信号受信回路１０２−２とに固定的に
分離され、それぞれ出呼、入呼のトラヒツク量に
応じて設置され、ハイウエイ２０２のMFC信号
受信用タイムスロツトと固定的に対応している。 Further, the signal receiving circuit 102 is fixedly separated into a signal receiving circuit 102-1 for receiving backward signals and a signal receiving circuit 102-2 for receiving forwardward signals, and each is installed according to the amount of outgoing and incoming call traffic. and corresponds fixedly to the MFC signal reception time slot of highway 202.
本実施例では、バツクワードMFC信号受信用
の信号回路に係るバツクワード信号受信用信号受
信回路１０２−１に対応しているタイムスロツト
（これは、複数であるが、以下、代表してｔbとい
う。）と同一時刻の入側ハイウエイ２０１のタイ
ムスロツトは、フオアワードMFC信号送出用と
している。 In this embodiment, there is a time slot (hereinafter, there is a plurality of time slots, which will be representatively referred to as tb ) corresponding to the signal receiving circuit 102-1 for receiving backward signals related to the signal circuit for receiving backward MFC signals. ) is used for transmitting forward MFC signals.
同様に、フオアワードMFC信号受信用の信号
回路１０２に対応しているタイムスロツト（これ
も、複数であるが、以下、代表してｔfという。）
と同一時刻の入側ハイウエイ２０１のタイムスロ
ツトは、バツクワードMFC信号送出用としてい
る。 Similarly, the time slots (hereinafter, representatively referred to as tf , although there are multiple time slots) corresponding to the signal circuit 102 for receiving the forward word MFC signal.
The time slot on the incoming highway 201 at the same time as the above is used for sending out the backward MFC signal.
一般接続の場合、出接続呼については、時分割
スイツチ３００を通し、タイムスロツトｔbで、
出トランク３０１に対してフオアワードMFC信
号を信号送出回路１０１から入ハイウエイ２０
１，出ハイウエイ２０４経由で送出し、出トラン
ク３０１からバツクワードMFC信号を入ハイウ
エイ２０３、出ハイウエイ２０２経由でバツクワ
ードMFC信号受信用の信号受信回路に係るバツ
クワード信号受信用信号受信回路１０２−１が受
信する。 In the case of a general connection, an outgoing call is sent through the time division switch 300 at the time slot tb .
The forward word MFC signal is sent from the signal sending circuit 101 to the outgoing trunk 301 on the incoming highway 20.
1. The backward MFC signal is sent via the outgoing highway 204 and received by the backward MFC signal receiving circuit 102-1, which is related to the signal receiving circuit for receiving the backward MFC signal, via the incoming highway 203 and outgoing highway 202. do.
また、図示省略しているが、入接続呼について
は、タイムスロツトｔfで、入トランクに対して
バツクワードMFC信号を信号送出回路１０１か
ら送出し、入トランクからフオアワードMFC信
号をフオアワードMFC信号受信用の信号受信回
路に係るフオアワード信号受信用信号受信回路１
０２−２が受信する。 Although not shown, for an incoming call, a backward MFC signal is sent from the signal sending circuit 101 to the incoming trunk at time slot t f , and a forward MFC signal is sent from the incoming trunk for forward MFC signal reception. Signal receiving circuit 1 for receiving forward word signals according to the signal receiving circuit of
02-2 receives it.
次に、試験接続について説明する。 Next, the test connection will be explained.
まず、対になるフオワード信号送出回路（また
はタイムスロツト）とバツクワード信号受信用信
号受信回路の試験をする場合は、中央制御装置
CPUから一般接続のときとは逆に、バツクワー
ドMFC信号送出指定を行い、信号送出回路１０
１からバツクワードMFC信号をタイムスロツト
tbで送出し、時分割スイツチ３００の試験接続路
TSTを通し、これをタイムスロツトtbでバツク
ワードMFC信号受信用の信号受信回路に係るバ
ツクワード信号受信用信号受信回路１０２−１が
受信するごとくし、送受データの照合を行う。 First, when testing the paired forward signal sending circuit (or time slot) and backward signal receiving signal receiving circuit, the central control unit
Contrary to the general connection from the CPU, specify backward MFC signal transmission, and
Time slot backward MFC signal from 1
tb transmission, test connection path of time division switch 300
Through TST, this is received by the signal receiving circuit 102-1 for backward signal reception related to the signal receiving circuit for receiving backward MFC signals in time slot tb, and the transmitted and received data are verified.
また、バツクワード信号送出回路（またはタイ
ムスロツト）とフオワード信号受信用信号受信回
路の試験をする場合は、同様に、中央制御装置
CPUから一般接続のときとは逆に、フオアワー
ドMFC信号送出指定を行い、信号送出回路１０
１からフオアワードMFC信号をタイムスロツト
ｔfで送出し、時分割スイツチ３００の試験接続
路TSTを通し、これをタイムスロツトｔfでフオ
アワードMFC信号受信用の信号受信回路に係る
フオアワード信号受信用信号受信回路１０２−２
が受信するごとくし、送受データの照合を行う。 In addition, when testing the backward signal sending circuit (or time slot) and the signal receiving circuit for forward signal reception, the central control unit
Contrary to the general connection from the CPU, the forward word MFC signal transmission is specified, and the signal transmission circuit 10
1, the forward-word MFC signal is sent through the time slot t f , passed through the test connection path TST of the time division switch 300, and sent to the time slot t f to receive the forward-word MFC signal for the signal receiving circuit for receiving the forward-word MFC signal. Circuit 102-2
The sent and received data is verified as if it were received by the sender.
このようにして、同一MFC信号装置１００内
で、信号送出回路１０１のすべてのバツクワード
MFC信号送出機能、フオアワードMFC信号送出
機能およびすべての信号受信回路１０２の受信機
能の試験を行い、障害の検出をすることができ
る。 In this way, all the backwords of the signal sending circuit 101 are transmitted within the same MFC signal device 100.
It is possible to test the MFC signal sending function, forward MFC signal sending function, and receiving functions of all signal receiving circuits 102 to detect failures.
さらに、MFC信号送出時のバツクワード、フ
オアワードの指定について、第２図および第３図
に基づき、詳細に説明する。 Furthermore, designation of the backward word and forward word when transmitting the MFC signal will be explained in detail with reference to FIGS. 2 and 3.
第２図は、本発明に係る信号送出指示データの
一実施例フオーマツト図で、そのａは、バツクワ
ードMFC信号送出指示を示すもの、ｂは、フオ
アワードMFC信号送出指示を示すもの、第３図
は、第１図における信号送出回路の一実施例の詳
細ブロツク図である。 FIG. 2 is a format diagram of an embodiment of signal transmission instruction data according to the present invention, in which a indicates an instruction to send a backward MFC signal, b indicates an instruction to send a forward MFC signal, and FIG. 2 is a detailed block diagram of one embodiment of the signal sending circuit in FIG. 1; FIG.
ここで、４０１は、中央処理装置CPUから送
られてくる直列の８ビツトの信号送出指示データ
DATAを並列に変換する直並列変換回路、４０
２は、MFC信号の2out of ６（６個中２個）符
号チエツクを行い、これをバイナリ符号に変換す
るチエツク回路、４０３は、バツクワード信号パ
タンメモリに係るROM、４０４は、フオアワー
ド信号パタンメモリに係るROM、４０５は、セ
レクタ、４０６は、クロツクパルスCPをうけ、
これを計数して所定のタイミングを発生するタイ
ミング回路、４０７は、並直列変換回路である。 Here, 401 is serial 8-bit signal sending instruction data sent from the central processing unit CPU.
Serial/parallel conversion circuit that converts DATA into parallel, 40
2 is a check circuit that checks the 2 out of 6 (2 out of 6) codes of the MFC signal and converts it into a binary code; 403 is a ROM for the backward signal pattern memory; and 404 is for the forward signal pattern memory. The ROM 405 is a selector, 406 receives a clock pulse CP,
A timing circuit 407 that counts this and generates a predetermined timing is a parallel-to-serial conversion circuit.
信号送出指示データDATAは、第２図に示す
ごとく、８ビツトからなり、そのうちの６ビツト
がMFC信号を構成すべき周波数f0〜f5に対応し、
残り２ビツトが信号方向指示、すなわち、バツク
ワードMFC信号送出指示（“01”）、フオアワード
MFC信号送出指示（“10”）いずれかに用いられ
る。 As shown in FIG. 2, the signal transmission instruction data DATA consists of 8 bits, 6 of which correspond to frequencies f 0 to f 5 that constitute the MFC signal.
The remaining 2 bits indicate the signal direction, that is, the backward MFC signal transmission instruction (“01”) and the forward direction.
Used for either MFC signal transmission instruction (“10”).
信号送出指示データDATAが入力されると、
チエツク回路４０２は、これのMFC信号に係る
６ビツトの2out of ６符号チエツクを行い、バイ
ナリ符号に変換し、これをアドレス指定として
ROM４０３，４０４へ送出する。 When signal sending instruction data DATA is input,
The check circuit 402 performs a 6-bit 2out of 6 code check on this MFC signal, converts it into a binary code, and uses this as an address specification.
Send to ROMs 403 and 404.
タイミング回路４０６は、ROM４０３，４０
４に対してMFC信号のサンプル時刻ごとのパタ
ン読出し指定を行う。 The timing circuit 406 includes ROMs 403 and 40.
4, designates pattern reading for each sample time of the MFC signal.
一方、信号送出指示データDATAの信号方向
指示部分は、直並列変換回路４０１を経てセレク
タ４０５へ入力される。 On the other hand, the signal direction instruction portion of the signal transmission instruction data DATA is input to the selector 405 via the serial/parallel conversion circuit 401.
セレクタ４０５は、これをデコードし、その信
号方向指示に従い、バツクワードMFC信号送出
の場合は、制御線ＦによつてROM４０４の出力
を禁止し、フオアワードMFC信号送出の場合
は、制御線ＢによつてROM４０３の出力を禁止
する。 The selector 405 decodes this and, according to the signal direction instruction, prohibits the output of the ROM 404 through the control line F in the case of sending a backward MFC signal, and prohibits the output of the ROM 404 through the control line B in the case of sending a forward MFC signal. Prohibits output of ROM403.
これによつて、信号方向指示に従つて、ROM
４０３，４０４からバツクワード信号、フオアワ
ード信号のパタンが読出され、並直列変換回路４
０７で直列PCM信号（パルスコード変調信号）
に変換され、マルチプレクサ１０３へ入力され、
入ハイウエイ２０１上へ送出される。 This allows the ROM to follow the signal direction instructions.
The patterns of the backward signal and forward signal are read out from 403 and 404, and the parallel-to-serial conversion circuit 4
07 is a serial PCM signal (pulse code modulation signal)
and input to the multiplexer 103,
It is sent onto the incoming highway 201.
以上の実施例では、バツクワードMFC信号
用、フオアワードMFC信号用として別々のROM
４０３，４０４を用いているが、本発明は、これ
に限定されるものではない。すなわち、この両者
を合併し、両信号用としてただ１つのROMを用
いるようにすることができることは、明らかであ
る。 In the above embodiment, separate ROMs are provided for backward MFC signals and forward MFC signals.
403 and 404, but the present invention is not limited thereto. That is, it is obvious that the two can be combined and only one ROM can be used for both signals.
以上、詳細に説明したように、本発明によれ
ば、他の信号との関係をもたずに、対になつてい
る送受信タイムスロツト単位に試験をし、容易
に、障害の検出をすることができるので、装置の
閉塞、系切替などの処理を迅速、かつ、確実に行
い、システムの保守・運用の容易化、信頼性の向
上、サービス性の向上に顕著な効果が得られる。 As described above in detail, according to the present invention, it is possible to easily detect faults by testing each paired transmission/reception time slot without any relationship with other signals. As a result, processing such as device blockage and system switching can be performed quickly and reliably, resulting in significant effects in facilitating system maintenance and operation, improving reliability, and improving serviceability.
第１図は、本発明に係るMFC信号装置の障害
検出方式の一実施例のブロツク図、第２図は、同
信号送出指示データの一実施例のフオーマツト
図、第３図は、第１図における信号送出回路の一
実施例の詳細ブロツク図である。
１００……MFC信号装置、１０１……信号送
出回路、１０２……信号受信回路、１０２−１…
…バツクワード信号受信用信号受信回路、１０２
−２……フオワード信号受信用信号受信回路、１
０３……マルチプレクサ、１０４……デマルチプ
レクサ、２０１，２０３……入ハイウエイ、２０
２，２０４……出ハイウエイ、３００……時分割
スイツチ、３０１……出トランク、４０１……直
並列変換回路、４０２……チエツク回路、４０
３，４０４……ROM、４０５……セレクタ、４
０６……タイミング回路、４０７……並直列変換
回路。
FIG. 1 is a block diagram of an embodiment of a fault detection method for an MFC signal device according to the present invention, FIG. 2 is a format diagram of an embodiment of the same signal sending instruction data, and FIG. FIG. 3 is a detailed block diagram of an embodiment of a signal sending circuit in FIG. 100...MFC signal device, 101... Signal sending circuit, 102... Signal receiving circuit, 102-1...
...signal receiving circuit for backward signal reception, 102
-2... Signal receiving circuit for forward signal reception, 1
03... Multiplexer, 104... Demultiplexer, 201, 203... Incoming highway, 20
2,204... Outgoing highway, 300... Time division switch, 301... Outgoing trunk, 401... Serial/parallel conversion circuit, 402... Check circuit, 40
3,404...ROM, 405...Selector, 4
06...Timing circuit, 407...Parallel-serial conversion circuit.
Claims (1)
の障害検出方式において、MFC信号装置は、そ
の送信側、受信側を、それぞれ、対となる入ハイ
ウエイ、出ハイウエイを通して時分割スイツチへ
収容し、外部装置からバツクワードMFC信号送
出指示、フオアワードMFC信号送出指示を与え
ることによつてMFC信号送出回路をバツクワー
ド用、フオアワード用共通に使用することを可能
とし、試験時には、通常動作時とは逆に、バツク
ワードMFC信号送出指示を与えて受信側にその
バツクワードMFC信号を受信せしめ、また、フ
オアワードMFC信号送出指示を与えて受信側に
そのフオアワードMFC信号を受信せしめるごと
く、同一MFC信号装置の送信側、受信側を時分
割スイツチによつて折返し接続して信号の送受信
を行わしめ、その照合を行うことを特徴とする
MFC信号装置の障害検出方式。 ２ 特許請求の範囲第１項記載のものにおいて、
バツクワードMFC信号送出指示、フオアワード
MFC信号送出指示は、送出すべきMFC信号デー
タに付属せしめて行うごとくしたMFC信号装置
の障害検出方式。 ３ 特許請求の範囲第１項または第２項記載のも
のにおいて、時分割スイツチによる折返し接続
は、MFC信号装置に係る入ハイウエイ、出ハイ
ウエイともに同一タイムスロツトで行うごとくし
たMFC信号装置の障害検出方式。[Claims] 1. In a fault detection method for a digital MFC signaling device of a time-division switch, the MFC signaling device connects its transmitting side and receiving side to the time-division switch through paired incoming and outgoing highways, respectively. The MFC signal sending circuit can be used for both backward and forward purposes by providing backward MFC signal sending instructions and forward MFC signal sending instructions from an external device. Conversely, the transmission of the same MFC signal device can be done by giving a backward MFC signal transmission instruction and making the receiving side receive the backward MFC signal, and by giving a forward MFC signal sending instruction and making the receiving side receive the forward word MFC signal. The device is characterized in that the side and the receiving side are connected back and forth through a time division switch to transmit and receive signals, and to verify the signals.
Fault detection method for MFC signaling equipment. 2. In what is stated in claim 1,
Backward MFC signal transmission instruction, forward word
A failure detection method for MFC signal equipment in which the MFC signal transmission instruction is attached to the MFC signal data to be transmitted. 3. In the item set forth in claim 1 or 2, a failure detection method of the MFC signaling device is such that the return connection by the time division switch is performed in the same time slot for both the incoming highway and the outgoing highway of the MFC signaling device. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12952579A JPS5654152A (en) | 1979-10-09 | 1979-10-09 | Failure detection system for mfc signal device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12952579A JPS5654152A (en) | 1979-10-09 | 1979-10-09 | Failure detection system for mfc signal device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5654152A JPS5654152A (en) | 1981-05-14 |
| JPS6240897B2 true JPS6240897B2 (en) | 1987-08-31 |
Family
ID=15011653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12952579A Granted JPS5654152A (en) | 1979-10-09 | 1979-10-09 | Failure detection system for mfc signal device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5654152A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03124497U (en) * | 1990-02-23 | 1991-12-17 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61198854A (en) * | 1985-02-27 | 1986-09-03 | Oki Electric Ind Co Ltd | Mfc signal test machine |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5178107A (en) * | 1974-12-27 | 1976-07-07 | Fujitsu Ltd | CHANERUHENKANSOCHISHIKENHOSHIKI |
-
1979
- 1979-10-09 JP JP12952579A patent/JPS5654152A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5178107A (en) * | 1974-12-27 | 1976-07-07 | Fujitsu Ltd | CHANERUHENKANSOCHISHIKENHOSHIKI |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03124497U (en) * | 1990-02-23 | 1991-12-17 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5654152A (en) | 1981-05-14 |
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