JPH08129480A - Ic for generating random number and pachinko play device - Google Patents

Abstract

PURPOSE: To effectively use an IC for generating random number and a memory which are capable of uniformly generating random numbers by hardware. CONSTITUTION: This device is provided with an interface part 3 performing the interface action with an external controller 2, an arithmetic timing control part 4 outputting an arithmetic timing signal CS to control the arithmetic timing for the generation of a random number and an arithmetic part 5 performing the random number generation calculation based on the arithmetic timing signal CS and outputting random number data X (n+1) to the external controller 2 via the interface part 3. The device is provided with a storage means where programs for control and data for control are preliminary stored, a fetching timing generation means outputting the fetching timing signal for fetching random number data in the interface part 3 and an operation control means performing the operation control of a PACHINKO (Japanese pinball game machine) play device based on the random number data inputted via the interface part 3, the programs for control and data for control.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to random number generation I.
The present invention relates to C, and more particularly to a pachinko game machine using a random number generating IC for generating random numbers used in various processes and a microcomputer.

[0002]

2. Description of the Related Art In a conventional pachinko game machine using a microcomputer, pseudo random numbers are generated by software in order to randomly change the progress of the game and to incorporate a probabilistic element in the score (the number of payouts). Then, there is a device in which the operation control is performed based on the generated pseudo random number.

Conventionally, in such a pachinko game apparatus, a ROM in a microcomputer is previously prepared.
The random number generation program was stored in and the random number was generated by software.

[0004]

By the way, in the above-mentioned conventional pachinko game machine, it is not allowed to incite too much euphoria due to the nature of the machine. , Have self-regulation.

Specifically, the capacity of the ROM is limited to 2.5 kBytes for the control program and 3 kBytes for the data, and the operation of the control program is further inspected to inflate the euphoria too much. I was trying not to.

Therefore, as described above, in order to generate random numbers by software, the ROM with this capacity limitation is used.
It is necessary to provide a storage area for the random number generation program therein, and the capacity of the control program other than the random number generation program is reduced, which causes a problem that complicated control cannot be performed.

Further, depending on the random number generation program,
The random numbers that are generated are not necessarily uniform random numbers, and there is a possibility that the progress of the game and the scores will be biased, which will fuel euphoria.

Therefore, conventionally, after the random number generation program is created, prior to incorporation into the pachinko game machine, the random number data generated by the random number generation program is the desired random number (uniform random number). In order to determine whether or not it was checked by the inspection department of the Japan Amusement Equipment Manufacturers Association.

Therefore, there is a problem in that it takes time and labor for checking and it takes time to commercialize the product. Therefore, a first object of the present invention is to provide a random number generation IC capable of generating uniform random numbers by hardware.

A second object of the present invention is to use a prescribed capacity to the maximum in a pachinko game machine for controlling the operation of the machine by using a random number, without the need to check the program for generating the random number. The purpose of the present invention is to provide a pachinko game machine that can perform various operation controls.

[0011]

In order to solve the above-mentioned problems, the invention according to claim 1 controls an interface section for interfacing with an external control device and a calculation timing for generating a random number. Therefore, a calculation timing control unit for outputting a calculation timing signal, and a calculation unit for performing random number generation calculation based on the calculation timing signal and outputting random number data to the external control device via the interface unit are provided. Configure.

According to a second aspect of the present invention, in the first aspect of the invention, the arithmetic unit sets the random number data generated at the (n + 1) th time to Xn + 1 and the random number data generated at the nth time. When Xn, the first random number generation constant is λ, and the second random number generation constant is μ, a random number is generated based on the following equation.

Xn + 1 ≡λ × Xn + μ (mod
2 ^S , where S is an integer) The invention of claim 3 is the same as the invention of claim 1,
The arithmetic unit generates the nth random number data Xn [m
[Bit] of the first random number data X (k) of the first register for storing while updating and the kth random number data X (k) generated last at a predetermined timing given from the outside.
-1) A second register for updating and storing [m bits], and the random number data X (k-2) [m bits] two times before the kth random number data X (k) at the predetermined timing.
And the random number data Xn
Is multiplied by random number data X (k-1) and multiplication result data M [2m
Bit]], the lower m bits of the multiplication result data M and the random number data X (k-2) are added to add (n +
1) th random number data X (n + 1) is output as an adder.

According to a fourth aspect of the present invention, there is provided a pachinko game machine provided with the random number generating IC according to the first to third aspects, wherein the storage means stores a control program and control data in advance. Based on the capture timing generation means for outputting a capture timing signal for capturing the random number data to the interface section, the random number data input via the interface section, the control program and the control data. And a motion control means for controlling the motion of the pachinko game machine.

[0015]

According to the first aspect of the invention, the operation timing control section outputs an operation timing signal to the operation section to control the operation timing for generating the random number. As a result, the calculation unit performs a random number generation calculation based on the calculation timing signal, and outputs the random number data to the external control device via the interface unit.

Therefore, the random number can be generated by hardware. According to the invention described in claim 2, the arithmetic unit sets the random number data generated at the (n + 1) th time to Xn + 1,
When the random number data generated at the n-th time is Xn, the first random number generation constant is λ, and the second random number generation constant is μ, a random number is generated based on the following equation.

Xn + 1 ≡λ × Xn + μ (mod
2 ^S , where S is an integer) Therefore, the setting of the first random number generation constant λ and the second random number generation constant μ is performed, for example, by setting the first random number generation constant λ at λ = 4K + 1 (K = 0, 1, 2). , ...) and the second random number generation constant μ is set to an odd number, a uniform random number having an appropriate period can be generated.

According to the third aspect of the invention, the first register causes the nth random number data Xn [m bits] to be generated.
Memorize while updating. The second register is the k-th register generated last at a predetermined timing given from the outside.
Last random number data X (k-1) of the th random number data X (k)
Store [m bits] while updating. The third register is
At the predetermined timing, the random number data X (k−2) [m bits] two times before the kth random number data X (k) is updated and stored.

Thus, the multiplier multiplies the random number data Xn by the random number data X (k-1) based on the data stored in the first register and the second register and outputs the multiplication result data M [2m bits].

As a result, the adder adds the lower m bits of the multiplication result data M and the random number data X (k-2) and outputs the result as the (n + 1) th random number data X (n + 1). .
Therefore, uniform random numbers can be easily generated by updating the stored contents of the second register and the third register at a predetermined timing that is set appropriately.

According to the fourth aspect of the invention, the storage means stores the control program and the control data in advance. The capture timing generation means outputs a capture timing signal for capturing random number data to the interface section.

As a result, random number data is input to the operation control means via the interface section. Thereby, the operation control means controls the operation of the pachinko game machine based on the input random number data, the control program, and the control data.

Therefore, in the pachinko game machine, since it is not necessary to generate random number data by software by the control program, it is not necessary to incorporate the random number generation software, and the capacity of the control program is substantially increased. It becomes possible to perform complicated control.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described with reference to the drawings. First Embodiment FIG. 1 shows a schematic block diagram of a random number generation IC according to the first embodiment.

The random number generating IC1 of the first embodiment is roughly classified into a so-called 68 series CPU such as MC6802 or Z80.
Interface unit 3 that performs an interface operation with an external CPU 2 such as a so-called 80-system CPU, and a calculation timing control unit 4 that outputs various calculation timing signals CS to control the calculation timing for random number generation.
And a calculation unit 5 that performs a random number generation calculation based on the calculation timing signal CS and outputs the random number data X (n + 1) to the external CPU 2 via the interface unit 3.

The calculation unit 5 calculates the nth random number data as Xn.
The external CPU 2 via the first register 6 for holding and the interface unit 3 or the operation timing control unit 4.
A first counter 7 for setting an arbitrary value in the first register 6 by the first clock signal clk ₁ input from
And a second register 8 for holding the M-bit first random number generation constant λ, and a second register by the second clock signal clk ₂ input from the external CPU 2 via the interface unit 3 or the operation timing control unit 4. A second counter 9 for setting an arbitrary value to 8, and an N-bit second counter 9.
A third register 10 that holds a random number generation constant μ, and a third clock signal c that is input from the external CPU 2 via the interface unit 3 or the operation timing control unit 4.
a third counter 11 for setting an arbitrary value in the third register 10 by lk ₃ , and first to third registers 6 and 8,
A sum-of-products calculation circuit 12 that performs a sum-of-products calculation based on the following data: Xn + 1 ≡λ · Xn + μ (mod 2 ^S , where S is an integer) .

In this case, in order to provide the longest period (2 ^S ), the second random number generating constant μ is set to an odd number,
It is preferable to set the first random number generating constant λ to λ = 4K + 1 (K = 0, 1, 2, ...).

In order to easily standardize the generated random number in the range of 0 to 1, it is preferable to set S = 20 (2 ^S = 1048576).

Further, when setting the initial value X0 of the random number data Xn, if the value is set too small, the random numbers may be biased to a small value first. Is preferred.

Next, the operation will be described. First, the first clock signal clk ₁ is input from the external CPU 2 via the interface unit 3 or the operation timing control unit 4, and the random number data Xn is input to the first register 6 via the first counter 7.
The random number data X0 which is the initial value of is set.

At the same time, the second clock signal clk ₂ is input from the external CPU 2 via the interface unit 3 or the operation timing control unit 4, and the second random number M 9 is input to the second register 8 via the second counter 9. The initial value of the generation constant λ is set, and the CPU 3 from the external CPU 2 receives the third value via the interface unit 3 or the operation timing control unit 4.
The clock signal clk ₃ is input and the initial value of the n-bit second random number generation constant μ is set in the third register via the third counter 11.

Next, the sum-of-products arithmetic circuit 12 operates the first register 6
Based on the random number data X0 in the second register 8, the initial value of the first random number generating constant λ in the second register 8 and the initial value of the second random number generating constant μ in the third register 10, Random number data X1 is generated.

X1 = λX0 + μ Then, the product-sum operation circuit 12 outputs the first random number data X1 to the external CPU 2 via the interface section 3 and the first random number data X1 as the first random number data X1. The value of the register 6 is updated.

Therefore, the first random number data X1 is used for the next product-sum calculation. Similarly, the product-sum calculation circuit 12 calculates the product-sum on the basis of the data stored in the first to third registers 6, 8, and 10 according to the following equation: Xn + 1 ≡ λ · Xn + μ (mod 2 ^S ). Will be done.

In the above description, the setting of the first random number generating constant λ and the second random number generating constant μ is described only at the time of initial setting, but based on a predetermined signal from the CPU 2 side. It is also possible to configure to update at any timing.

More specifically, regardless of the input of the read signal for reading the random number data generated from the external CPU 2 side, the product-sum operation circuit always generates and updates the random number data, and the external CPU If the first random number generating constant λ and the second random number generating constant μ are updated each time a read signal is input, a uniform random number can be generated at all times. If the processing is performed in the game machine by using, the game progress situation and score will not be biased. Second Embodiment FIG. 2 shows a schematic block diagram of a random number generation IC of the second embodiment.

The random number generating IC 20 of the second embodiment is roughly classified into various types such as an interface section 22 for interfacing with a CPU 21 which is an external control device, and various control timings for generating a random number. A calculation timing control unit 23 that outputs a calculation timing signal and a calculation unit 24 that performs a random number generation calculation based on the various calculation timing signals described above and outputs random number data to an external control device via the interface unit 22. It is equipped with.

The calculation unit 24 stores the first random number data Xn [20 bits] generated while updating it sequentially.
The register 25, the first flip-flop FF ₁ that sequentially updates and holds the (n−1) th generated random number data Xn [20 bits], and the (n−2) th generated random number data Xn [ 20 bits] is transferred from the first flip-flop FF ₁ to sequentially update and hold the second flip-flop FF _2, and the k-th random number data generated last at the last data read timing by the external CPU 21. Last random number data X of X (k)
(k-1) [20 bits] is transferred from the first flip-flop FF ₁ and stored, and the second register 26 that holds until the next data read timing of the CPU 21 and the external CP
At the last data read timing by U, the last random number data X (k-2) of the kth random number data X (k).
[20 bits] are transferred from the second flip-flop FF ₂ and stored, and the third register 27 that stores and stores the random number data X is held until the next CPU data read timing.
Multiplication result data ML by multiplying n by random number data X (k-1)
[40 bits] is output to the multiplier 28, the lower 20 bits of the multiplication result data ML and the random number data X (k-2) are added to add the (n + 1) th random number data X (n + 1) [20 Bit]] and a first adder 29
It is configured to include a third flip-flop FF ₃ for latching the output of the.

The multiplier 28 shifts the random number data Xn to the left (shifts to the MSB side) based on the clock signal input to the clock terminal CK, and the random number data X (k-1) to the clock terminal. The right shift circuit 31 that shifts to the right (shifts to the LSB side) based on the same clock signal that is input to the left shift circuit 30 that is input to CK, and the LSB of the right shift circuit 31 is “1”. In this case, the AND circuit 32 that directly outputs the output [20 bits] of the left shift circuit and the output of the AND circuit 32 are input to the terminal A, and the multiplication result data [40 bits] up to the previous shift is input to the terminal B. Then, the input data of the terminal A and the previous multiplication result data are added to obtain the multiplication result data M
The second adder 33 that outputs L [40 bits] and the fourth flip-flop FF ₄ that holds the output of the second adder 33
It is configured with.

Next, referring to the operation flowchart of FIG.
The operation of the second embodiment will be described. The external CPU 21
Control clock signal CC via the interface 22.
LK is input and the random number data Xn of the first register 25 is input.
Set the initial value X0 and generate the first random number in the second register 26
Initial value λ as constant λ₀(= In random number data X (k-1)
(Equivalent) is set, and the third register 27 has a second random number generation constant.
Initial value of several μ ₀(= Corresponds to random number data X (k-2))
Set. Furthermore, the first flip-flop FF₁And No. 2
Lip flop FF₂Set the initial value to
Step S1).

Next, the multiplier 28 multiplies the random number data X0 and the random number data X (k-1) (step S2). More specifically, the left shift circuit 30 of the multiplication circuit shifts the random number data Xn to the left (MSB) based on the clock signal input to the clock terminal CK by the operation timing control section 23.
Shift to the side). At the same time, the right shift circuit 31
The random number data X (k-1) is right-shifted (shifted to the LSB side) based on the same clock signal as the clock signal input to the left shift circuit 30 input to the clock terminal CK.

As a result, the AND circuit 32 shifts rightward.
Output of the left shift circuit when LSB = "1" of the road
Is directly output to the terminal A of the second adder 33. Second addition
The calculator 33 applies the fourth flip-flop to the input data of the terminal A and the terminal B.
Pro-flop FF _FourPower up to the previous shift input from
The latest multiplication result is obtained by adding the calculation result data (initial value = 0)
The fourth flip-flop FF is again used as the result data ML._FourTo
Output.

The left shift circuit 30 and the right shift circuit 3
The first and second adders 33 perform similar shift processing and addition processing 20 times (corresponding to 20 bits), transfer the multiplication result data ML obtained to the fourth flip-flop FF4, and perform the fourth
The flip-flop FF ₄ is the final multiplication result data ML.
To the first adder 29.

As a result, the first adder 29 adds the random number data X (k-2) transferred from the third register 27 and the lower 20 bits of the multiplication result data (step S3),
As the random number data X (n + 1), the third flip-flop F
It is output to the interface unit 22 via F ₃ and set as random number data X (n + 1) [20 bits] in the first register 25 and the first flip-flop FF ₁ (step S4). As a result, the third flip-flop flop F
In F ₃ , 0 to 104875 (= FFFFFh
The random number data corresponding to (h: represents a hexadecimal number) will be set.

In parallel with these and the processing of step S3 to step S4, the external CPU 21 makes the random number data X (n + 1)
Of the random number data X (n + 1) is determined by the CPU 21 (step S5).
) Read request (data read request), the data of the first flip-flop FF ₁ is transferred to the second register 26 and updated, and the second flip-flop FF ₂ is updated.
Is transferred to the third register 27 and updated (step S6).

As a result, every time the CPU 21 makes a read request, the initial value is constantly updated, and a uniform random number can be generated. Next, a case where the random number data generated by the random number generation IC 20 is read by the external CPU 21 and is actually used will be described.

As described above, the third flip-flop F
In F ₃ , 0 to 104875 (= FFFFFh)
2 is set, the external data bus DB of the interface section has an 8-bit configuration as shown in FIG. 2, and for example, when outputting 16-bit equivalent random number data. However, it is to be divided into 8 bits and output.

Therefore, the external CPU 21 has the 2-bit read control information CMD corresponding to the random number data to be read.
Is given to the interface part, and the interface part
Depending on the value of the read control information CMD, the external data bus DB
The random number data to be output to is determined.

More specifically, the read control information CMD = "0".
In the case of “0”, 0 to 0 of 20-bit random number data
The partial random number data corresponding to 7 bits is output. Also,
When the read control information CMD = "01", the partial random number data corresponding to 8 to 15 bits of the 20-bit random number data is output.

Further, when the read control information CMD = "10", the partial random number data corresponding to 4 to 11 bits of the 20 bit random number data is output. Furthermore, when the read control information CMD = “11”, the partial random number data of 16 to 19 bits is output from the random number data of 20 bits. In this case, the upper 4 bits of the 8-bit external data bus DB are all output as "0".

Here, a concrete example of random number generation will be described. a) When generating a random number from 0 to 255, the CPU 21 sets the read control information CMD to “00” or “0”.
Set to "1" or "10" and use the output 8-bit partial random number data as it is. b) When Generating Random Numbers from 0 to 65535 (= FFFFh) First, the CPU 21 sets the read control information CMD to "00" to output 8-bit partial random number data, and then sets the read control information CMD to " 01 ”to output 8-bit partial random number data again, and both partial random number data are output to the CPU.
It is used by synthesizing on the side as 16-bit random number data. c) When Random Numbers 0 to 199 are Generated First, the CPU 21 sequentially sets the read control information CMD to “0.
Set to "0", "01", "11" to output three 8-bit partial random number data, use 18 bits of the obtained 20-bit random number data, and weight each bit as shown below. It is used by adding and adding these.

0 to 6 bits: Corresponding to 0 to 127 7 to 12 bits: Corresponding to 0 to 63 (obtained value is divided by 2) 13 to 15 bits: Corresponding to 0 to 7 16 bits: 0 to 1 Corresponding to 17 bits: Corresponding to 0-1 More specifically, when the obtained 18 bits have the following values: 0 to 6 bits: "1001101" = 777 7 to 12 bits: "1111110" = 63 ( = 126
/ 2) 13 to 15 bits: “111” = 7 16 bits: “0” = 0 0 17 bits: “1” = 1 The random number XX to be obtained is XX = 77 + 63 + 7 + 0 + 1 = 148.

Although three random number generation examples have been described above, various modifications other than these are possible. FIG. 4 shows the relationship between the random number value and the frequency of occurrence when random numbers 0 to 255 are generated by the method a). In this case, the total number of samples (= number of times of random number generation) is set to 12,800,000.

As shown in FIG. 4, the occurrence frequencies of the random number values are almost equal, and it can be seen that uniform random numbers are generated. As described above, the initial value of the random number generation is automatically performed (= the first random number generation constant λ and the second random number generation constant μ).
To always generate a uniform random number,
There will be no bias in game progress or score.

Further, it is possible to speed up the random number generation process. Further, in the second embodiment, the CPU 2
When 1 makes a read request of random number data, the data of the first flip-flop FF ₁ is transferred to the second register 26 and updated, and at the same time, the second flip-flop FF ₂
However, the data of the first flip-flop FF ₁ is transferred to the second register 26, and the data of the second flip-flop FF ₂ is transferred to the second register 26. The transfer timing and the transfer timing may be set to different timings in the 3 register 27 under the control of the calculation timing control unit 23.

Furthermore, a nonvolatile and rewritable ROM such as an EEPROM that updates and stores the initial value of random number generation when the power is turned off may be provided and used as the initial value when the power is turned on next time. It is possible. This makes it possible to prevent the random numbers after power-on from becoming the same each time, and it is possible to generate more uniform random numbers. Third Embodiment FIG. 5 shows a control system 4 of a pachinko game machine using the random number generating IC of the first embodiment or the random number generating IC of the second embodiment.
0 shows a schematic configuration block diagram of 0.

The control system 40 of the pachinko game machine has a ROM 41 for storing a control program and control data,
A RAM 42 for temporarily storing various data, a random number generation IC 1 (or 20) for generating and outputting random number data,
Various sensors (not shown), LCD (Liquid
Crystal Display), LED (Light Emitting Diod)
e), an interface section 43 for interfacing with a sound board for voice control, and a CPU 44 for controlling the entire pachinko game machine.

In this case, as described above, the ROM
41 has a limited storage capacity, and the RAM 42 also has a limited storage capacity. Specifically, the ROM 41
Has 2.5kByte as a control program area,
It has 3 kBytes as a control data area. Also,
The RAM 42 has a storage area of 256 bytes.

Next, the operation will be described. CPU44 is RO
The control program and control data are read from M41, and the control operation is started based on these. Also CPU
44 indicates that the temporary data generated during this control operation is R
It is stored in the AM 42 and processed.

For example, when it is detected that a prize has been won (a ball has entered a pocket) via the interface unit 43, the CPU 44 sends a command C for reading random number data to the random number generating IC 1.

As a result, the random number generating IC 1 outputs the generated random number data X to the CPU 44 side via the data bus, and the CPU 44 shows the random number data X based on the obtained random number data X via the interface section 43. Not LE
It controls the D, LCD, sound board, etc.

As described above, according to the third embodiment, since the random number data is generated by hardware and the processing is performed by software based on the obtained random number data, the random number is calculated by software. Random number generation program area is unnecessary compared with the case of generating
The storage capacity of the ROM 41 whose capacity is limited can be used purely as the storage capacity of the control program and the control data, and more complicated control can be performed.

Further, since the random number generating program is not used, the verification process for checking whether or not the uniform random number is generated at the time of creating the program is unnecessary, and the product developing process can be simplified.

[0064]

According to the invention described in claim 1, since the random number can be generated by hardware, the program capacity and storage capacity of the device or the entire system using the random number generating IC and the check at the time of creating the program. The number of steps can be reduced, the cost of the product can be reduced, and the number of development steps can be reduced.

According to the second aspect of the present invention, the arithmetic unit comprises:
A random number is generated based on the following formula. Xn + 1 ≡λ × Xn + μ (mod 2 ^S , where S is an integer) Therefore, the first random number generation constant λ and the second random number generation constant μ are set, for example, by setting the first random number generation constant λ to λ. = 4K + 1 (K = 0, 1, 2, ...) And the second random number generation constant μ is set to an odd number, a uniform random number having an appropriate period can be generated. When a game machine or the like is constructed by using the game machine, there is no bias in the progress status or score of the game.

According to the third aspect of the invention, uniform random numbers can be easily generated by hardware by updating the storage contents of the second register and the third register at a predetermined timing set appropriately. And I for random number generation
When a game machine or the like is configured by using C, there is no bias in the progress status and the score of the game.

According to the fourth aspect of the invention, the operation control means outputs the fetch timing signal, whereby the random number data is input to the operation control means via the interface section. The operation control means, the input random number data,
Since the operation control of the pachinko game machine is performed based on the control program and the control data stored in the storage means in advance, it is not necessary to generate the random number data by software by the control program, and the random number generation software is incorporated. It is possible to substantially increase the storable capacity of the control program and the control data in the pachinko game machine without any need, and to perform more complicated control.

[Brief description of drawings]

FIG. 1 is a schematic configuration block diagram of a first embodiment.

FIG. 2 is a schematic configuration block diagram of a second embodiment.

FIG. 3 is an operation flowchart of the second embodiment.

FIG. 4 is a diagram showing a relationship between a random number value and its occurrence frequency.

FIG. 5 is a schematic configuration block diagram of a control system of a pachinko game machine of a third embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... IC for random number generation 2 ... CPU 3 ... Interface part 4 ... Operation timing control part 5 ... Operation part 6 ... 1st register 7 ... 1st counter 8 ... 2nd register 9 ... 2nd counter 10 ... 3rd register 11 ... Third counter 12 ... Sum of products arithmetic circuit 20 ... Random number generation IC 21 ... CPU 22 ... Interface section 23 ... Operation timing control section 24 ... Operation section 25 ... First register 26 ... Second register 27 ... Third register 28 ... Multiplication 29. First adder 30 ... Left shift circuit 31 ... Right shift circuit 32 ... AND circuit 33 ... Second adder 40 ... Pachinko game machine control system 41 ... ROM 42 ... RAM 43 ... Interface section 44 ... CPU CMD ... CS ... calculation timing signal clk ₁ ... first clock signal clk ₂ ... second clock signal clk ₃ ... third clock signal F ₁ ... first flip-flop FF ₂ ... second flip-flop FF ₃ ... third flip-flop FF ₄ ... fourth flip-flop ML ... multiplied data Xn, X (n + 1) ... random number data lambda ... first random number generation For constant μ ... Constant for second random number generation

Claims (4)

[Claims] 1. An interface section for interfacing with an external control device, a calculation timing control section for outputting a calculation timing signal to control a calculation timing for random number generation, and a calculation timing signal based on the calculation timing signal. An IC for random number generation, comprising: an arithmetic unit that performs a random number generation operation by using the interface unit and outputs random number data to the external control device via the interface unit. 2. The IC for random number generation according to claim 1, wherein the arithmetic unit sets Xn + 1 to the random number data generated at the (n + 1) th time, and sets Xn + 1 to the random number data generated at the nth time.
A random number generating IC, wherein n is a random number generating constant and λ is a first random number generating constant, and μ is a second random number generating constant. Xn + 1 ≡ λ · Xn + μ (mod 2 ^S , where S is an integer) 3. The random number generating IC according to claim 1, wherein the arithmetic unit generates the nth random number data Xn [m
Bit], and stores the last random number data X (k-1) [m of the kth random number data X (k) generated last at a predetermined timing given from the outside. A second register for updating and storing [bit], and for storing the random number data X (k-2) [m bits] two times before the k-th random number data X (k) at the predetermined timing. A third register, a multiplier for multiplying the random number data Xn by the random number data X (k-1) and outputting the multiplication result data M [2m bits], a lower m bits of the multiplication result data M and the random number data X (k- 2)
An IC for random number generation, comprising: an adder for adding and to output as (n + 1) th random number data X (n + 1). 4. A pachinko game apparatus provided with the random number generation IC according to claim 1, wherein a storage means in which a control program and control data are stored in advance, and a random number for the interface section. Capture timing generation means for outputting a capture timing signal for capturing data, and operation control of the pachinko game machine based on the random number data, the control program, and the control data input via the interface section. A pachinko game machine characterized by comprising: