JPH0812578B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0812578B2 JPH0812578B2 JP1231273A JP23127389A JPH0812578B2 JP H0812578 B2 JPH0812578 B2 JP H0812578B2 JP 1231273 A JP1231273 A JP 1231273A JP 23127389 A JP23127389 A JP 23127389A JP H0812578 B2 JPH0812578 B2 JP H0812578B2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- resistive element
- vcc2
- power supply
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Logic Circuits (AREA)
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は２つの異なる電源系にまたがる信号のイン
ターフェイスに関する。Description: FIELD OF THE INVENTION The present invention relates to the interfacing of signals across two different power systems.
この発明は２つの異なる電源系を有するMOS集積回路
装置において、一方の電源系（以下Vcc1系とする）の出
力信号を受ける他方の電源系（以下Vcc2系とする）の入
力信号線にプルダウントランジスタを付加することによ
り、前記Vcc1系の電源がOFFした時に前記Vcc2系の入力
信号線をローレベルに保持して安定し、前記Vcc2系の消
費電流を小さくするようにしたものである。According to the present invention, in a MOS integrated circuit device having two different power supply systems, a pull-down transistor is provided in an input signal line of another power supply system (hereinafter Vcc2 system) that receives an output signal of one power supply system (hereinafter Vcc1 system). Is added, the input signal line of the Vcc2 system is held at a low level to be stable when the power supply of the Vcc1 system is turned off, and the current consumption of the Vcc2 system is reduced.
従来、第２図に示すようにVcc1系７の出力信号をVcc2
系８で入力する時はインバータ４で受けていただけであ
った。Conventionally, as shown in FIG. 2, the output signal of the Vcc1 system 7 is changed to Vcc2.
When inputting in system 8, it was only received by inverter 4.
しかし、従来の技術ではVcc1系７の電源がOFFした時
にVcc2系８の入力信号線がフローティングとなる可能性
があり、従ってインバータ４の出力信号が定まらず、さ
らにVcc2系８の消費電流も増大するという欠点があっ
た。この発明は、従来のこのような欠点を解決するため
に、Vcc1系７の電源がOFFしてもVcc2系８の入力信号線
がフローティングにならないように安定させ、さらに、
この時のVcc2系８の消費電流を小さくすることを目的と
している。However, in the conventional technology, the input signal line of the Vcc2 system 8 may be floating when the power supply of the Vcc1 system 7 is turned off. Therefore, the output signal of the inverter 4 is not fixed, and the current consumption of the Vcc2 system 8 also increases. There was a drawback to do. In order to solve such a conventional drawback, the present invention stabilizes the input signal line of the Vcc2 system 8 so as not to float even when the power supply of the Vcc1 system 7 is turned off.
The purpose is to reduce the current consumption of the Vcc2 system 8 at this time.
上記課題を解決するために、この発明はVcc2系８の入
力信号線にプルダウントランジスタを付加するようにし
た。In order to solve the above problems, the present invention adds a pull-down transistor to the input signal line of the Vcc2 system 8.
上記のようにVcc2系８の入力信号線にプルダウントラ
ンジスタを付加することによって、Vcc1系７の電源がOF
Fした時、前記Vcc2系８の入力信号線はローレベルに安
定に保たれ、Vcc2系８の消費電流はリーク電流のみとな
って非常に小さくすることができる。By adding the pull-down transistor to the input signal line of Vcc2 system 8 as described above, the power supply of Vcc1 system 7 becomes OF.
When F is applied, the input signal line of the Vcc2 system 8 is stably maintained at a low level, and the consumption current of the Vcc2 system 8 is only a leakage current, which can be made extremely small.
本発明の実施例を図面に基づいて説明する。第１図に
おいて、Vcc2系８の入力信号線１を２つのＮチャンネル
トランジスタ（以下Nchトランジスタと略す）２及び３
のドレインに接続するとともにVcc2系８のインバータ４
に入力し、前記２つのNchトランジスタ２及び３のソー
スをVssに接続し、Nchトランジスタ２のゲートをVcc2系
８の電源に接続し、Nchトランジスタ３のゲートを前記V
cc2系８のインバータ４の出力信号線５に接続した。Vcc
1系７のインバータ６の出力インピーダンスはプルダウ
ンのNchトランジスタ２及び３のインピーダンスに比べ
十分低く設計するため、通常は、前記インバータ６の出
力信号はそのまま前記インバータ４に入力してVcc2系８
に伝達される。また、前記Nchトランジスタ２のインピ
ーダンスを比較的高く設計することにより、Vcc2系８の
入力信号線１がハイレベルの時の前記Nchトランジスタ
２に流れる電流を小さくすることができる。An embodiment of the present invention will be described with reference to the drawings. In FIG. 1, the input signal line 1 of the Vcc2 system 8 has two N-channel transistors (hereinafter abbreviated as Nch transistors) 2 and 3
Inverter 4 of Vcc2 system 8 connected to the drain of
, The sources of the two Nch transistors 2 and 3 are connected to Vss, the gate of the Nch transistor 2 is connected to the power supply of the Vcc2 system 8, and the gate of the Nch transistor 3 is connected to the Vss.
It was connected to the output signal line 5 of the inverter 4 of the cc2 system 8. Vcc
Since the output impedance of the inverter 6 of the 1-system 7 is designed to be sufficiently lower than the impedance of the pull-down Nch transistors 2 and 3, the output signal of the inverter 6 is normally input as it is to the inverter 4 and the Vcc2-system 8
Is transmitted to Further, by designing the impedance of the Nch transistor 2 to be relatively high, it is possible to reduce the current flowing through the Nch transistor 2 when the input signal line 1 of the Vcc2 system 8 is at a high level.
Vcc1系７の電源がOFFした時は、前記Vcc2系８の入力
信号線１は前記Nchトランジスタ２によりフローティン
グとならずにローレベルとなり、さらにVcc2系８のイン
バータ４の出力信号線５がハイレベルとなることによ
り、前記Nchトランジスタ３もONする。この時、前記Nch
トランジスタ３のインピーダンスを比較的低く設計する
ことにより前記Vcc2系８の入力信号線１は比較的低イン
ピーダンスでローレベルを保つことができ、ノイズに対
して強くなる。また、この時Vcc2系８の消費電流として
はリーク電流のみとなる。When the power supply of the Vcc1 system 7 is turned off, the input signal line 1 of the Vcc2 system 8 does not become floating due to the Nch transistor 2 and becomes a low level, and the output signal line 5 of the inverter 4 of the Vcc2 system 8 becomes a high level. Then, the Nch transistor 3 is also turned on. At this time, the Nch
By designing the impedance of the transistor 3 to be relatively low, the input signal line 1 of the Vcc2 system 8 can maintain a low level with a relatively low impedance, and it is resistant to noise. At this time, the leakage current is the only current consumption of the Vcc2 system 8.
以上説明したように、この発明はプルダウンのNchト
ランジスタ２及び３をVcc2系８の入力信号線１に付加し
たことによって、Vcc1系７の電源がOFFした時に前記Vcc
2系８の入力信号線１が安定したローレベルに保たれ、
さらにこの時のVcc2系８の消費電流も非常に小さくなる
効果がある。特に、メモリ内蔵のICにおいて、メモリの
電源系を前記ICの電源系と分離してICの電池交換時等に
よってメモリの電源系をバックアップするシステムのメ
モリの入力インターフェイスに用いることによって、メ
モリの電源系をバックアップしている時のメモリへの入
力信号を安定させて、RAM等の内容が書き換わらないよ
うにするとともに、メモリの電源系の消費電流を非常に
小さく押さえる効果がある。As described above, the present invention adds the pull-down Nch transistors 2 and 3 to the input signal line 1 of the Vcc2 system 8 so that when the power supply of the Vcc1 system 7 is turned off, the above Vcc
The input signal line 1 of system 2 is kept at a stable low level,
Further, the current consumption of the Vcc2 system 8 at this time is also very small. In particular, in an IC with a built-in memory, the power supply system of the memory is separated from the power supply system of the IC by using it as an input interface of the memory of the system that backs up the power supply system of the memory when the battery of the IC is replaced. It has the effect of stabilizing the input signal to the memory when the system is backed up so that the contents of RAM etc. are not rewritten and the current consumption of the memory power supply system is kept extremely small.
第１図は本発明の半導体集積回路装置の回路図、第２図
は従来の半導体集積回路装置の回路図である。 １……Vcc2系の入力信号線 ２……Ｎチャンネルトランジスタ ３……Ｎチャンネルトランジスタ ４……インバータ ５……出力信号線 ６……インバータ ７……Vcc1系 ８……Vcc2系FIG. 1 is a circuit diagram of a semiconductor integrated circuit device of the present invention, and FIG. 2 is a circuit diagram of a conventional semiconductor integrated circuit device. 1 …… Vcc2 system input signal line 2 …… N channel transistor 3 …… N channel transistor 4 …… Inverter 5 …… Output signal line 6 …… Inverter 7 …… Vcc1 system 8 …… Vcc2 system
Claims (3)
路装置において、第一の電源系で作動する回路の出力端
子を第一の抵抗性素子の第一の端子、第二の抵抗性素子
の第一の端子、及び第二の電源系で作動する回路のイン
バータの入力端子にに接続し、前期第一の抵抗性素子の
第二の端子、及び前記第二の抵抗性素子の第二の端子を
接地端子に接続し、前記第二の抵抗性素子の抵抗値を前
記インバータの出力端子から出力する信号により制御す
ることを特徴とする半導体集積回路装置。1. A MOS type semiconductor integrated circuit device having a plurality of power supply systems, wherein an output terminal of a circuit operating in the first power supply system is a first terminal of a first resistive element and a second resistive element. Connected to an input terminal of an inverter of a circuit that operates in a second power supply system, the second terminal of the first resistive element, and the second terminal of the second resistive element. Is connected to the ground terminal, and the resistance value of the second resistive element is controlled by a signal output from the output terminal of the inverter.
の電源の電源供給端子に接続した第一のMOSFETで、前記
第一の抵抗性素子の第一の端子が前記第一のMOSFETのド
レインで、前記第一の抵抗性素子の第二の端子が前記第
一のMOSFETのソースであることを特徴とする特許請求の
範囲第１項記載の半導体集積回路装置。2. A first MOSFET in which the first resistive element has a gate connected to a power supply terminal of the second power source, and a first terminal of the first resistive element is the first MOSFET. The semiconductor integrated circuit device according to claim 1, wherein the drain of the MOSFET and the second terminal of the first resistive element are the source of the first MOSFET.
バータの出力端子に接続した第二のMOSFETのドレイン
で、前記第二の抵抗性素子の第二の端子が前記第二のMO
SFETのソースで、前記第二のMOSFETのゲートが前記イン
バータの出力端子に接続したことを特徴とする特許請求
範囲第１項記載の半導体集積回路装置。3. The drain of the second MOSFET, wherein the second resistive element has a gate connected to the output terminal of the inverter, and the second terminal of the second resistive element is the second MO.
2. The semiconductor integrated circuit device according to claim 1, wherein the gate of the second MOSFET is connected to the output terminal of the inverter at the source of the SFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1231273A JPH0812578B2 (en) | 1989-09-06 | 1989-09-06 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1231273A JPH0812578B2 (en) | 1989-09-06 | 1989-09-06 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0392918A JPH0392918A (en) | 1991-04-18 |
| JPH0812578B2 true JPH0812578B2 (en) | 1996-02-07 |
Family
ID=16921019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1231273A Expired - Lifetime JPH0812578B2 (en) | 1989-09-06 | 1989-09-06 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0812578B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102009052947B3 (en) * | 2009-11-12 | 2010-12-16 | Sinitec Vertriebsgesellschaft Mbh | Energy saving circuit for a peripheral device, peripheral device, switching device and working method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4080539A (en) * | 1976-11-10 | 1978-03-21 | Rca Corporation | Level shift circuit |
-
1989
- 1989-09-06 JP JP1231273A patent/JPH0812578B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0392918A (en) | 1991-04-18 |
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