JPH08125162A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE: To obtain a finer semiconductor device in which the fluctuation of tunnel barrier can be suppressed between elements and the gate and conduction area can be realized at a constant interval with no misalignment. CONSTITUTION: The semiconductor device utilizing the quantum tunnel effect of electron comprises a gate electrode 2 grown on a semiconductor substrate 6, a mesa 15 formed contiguously to the gate electrode 2, a first conductive layer 3 grown on the side face of the mesa 15, and second conductive layers 5, 5' grown on the side face of the mesa 15. Carrier density of the first conductive layer 3 is varied depending on the voltage of the gate electrode 2 and the wave function of carrier of the first conductive layer 3 is superposed partially and spatially on that of the second conductive layer 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using the quantum tunnel effect of electrons and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as an electronic device using the quantum tunnel effect of electrons, a device in which a potential of a quantum well of a resonance tunnel diode is modulated to form a transistor and a single electron transistor have been developed.

As a conventional example, FIG. 16 shows a conceptual diagram of a single electron transistor. In this device, the charge storage conductive region 3 and the source or drain electrode 1 are tunnel-coupled,
The tunnel current flows between the source and drain. Further, the potential of the charge storage conductive region 3 is changed by the voltage of the gate electrode 2 and the tunnel probability is modulated to control the current. Here, since the tunnel probability exponentially depends on the thickness of the barrier layer 4, it is necessary to form the tunnel barrier layer 4 having a controllability of about an atomic layer in order to realize an element with good reproducibility. ing.

Here, in the single electron transistor in which the tunnel barrier layer 4 is formed by lithography, it is difficult to control the tunnel barrier to an atomic layer level. Further, as shown in FIG. 17, when the gate electrode 2 and the electric conduction region 3 are misaligned with each other, these capacitances change and it is difficult to form a single electron transistor with good reproducibility.

On the other hand, the molecular beam epitaxial growth method (MB
By using E) or the metal organic CVD method (MOCVD), the tunnel barrier can be formed with a precision of about an atomic layer. However, in the single-electron transistor using these stacking methods, the conventional lithography is used to process the gate electrode in the direction perpendicular to the stacking direction, and the distance between the gate electrode 2 and the electric conduction region 3 can be controlled with good controllability. It was difficult to form. This is because the gate electrode 2 has an electrically conductive region 3
Therefore, it is difficult to control the capacitance of the single electron transistor and it is difficult to form a single electron transistor with good reproducibility even by this method.

Further, as shown in FIG. 18, a method has been proposed in which a laminated structure is epitaxially grown on a semiconductor substrate, a mesa 15 is further formed, and a gate insulating film 9 on the mesa and a gate 2 are formed. However, according to this method, the mesas 15 exposed on the surface before forming the gate insulating film become the channel regions 3 and 5 of the transistor, so that they are easily affected by interface defects and the reproducibility of the carrier density of the channel is poor. . In the figure, 13 is a GaAs layer and 14 is A
The lGaAs layer is a mesa.

These problems occur not only in single-electron transistors, but also in devices that use the quantum tunnel effect and that control the potential of the conduction region in contact with the tunnel barrier with an insulated gate.

[0008]

As described above, in the conventional device in which the potential of the conduction region in contact with the tunnel barrier is controlled by the insulated gate by using the quantum tunnel effect, the tunnel barrier is formed with good reproducibility, and It was difficult to realize the space with the conduction region with good reproducibility.

The present invention has been made to solve the above problems, and an object of the present invention is to suppress variations in tunnel barrier between elements and to maintain a constant level without misalignment between the gate and the conduction region. It is an object of the present invention to provide a semiconductor device which can be realized at intervals and can be further miniaturized, and a manufacturing method thereof.

[0010]

According to the gist of the present invention, after forming a first laminated structure including a gate on a semiconductor substrate,
A mesa is formed on the surface and a second laminated structure including a tunnel barrier region is formed on the mesa. A feature of the present invention is that the potential forming the tunnel barrier is formed with good reproducibility by the first or second laminated structure without using lithography.

That is, according to the present invention (claim 1), in a semiconductor device using the quantum tunnel effect of electrons, a first electrode grown and formed on a semiconductor substrate is formed so as to be in contact with the first electrode. The formed mesa, the first conductive layer grown on the mesa, and the second conductive layer grown on the mesa.
And the carrier density of the first conductive layer is changed by the voltage of the first electrode, and the wave function of the carrier of the first conductive layer is equal to the wave function of the second conductive layer. It is characterized by overlapping spatially.

According to the present invention (claim 2), in the method of manufacturing a semiconductor device having the above structure, a step of epitaxially growing a first electrode on a semiconductor substrate, and patterning and etching the semiconductor to form a first electrode. A step of forming a mesa so as to be in contact with the mesa, a step of epitaxially growing a first conductive layer on the mesa, and a step of growing a second conductive layer on the mesa.

[0013]

In the structure of the present invention, the epitaxial technique can be used for forming the gate and the tunnel barrier, and they can be stacked with a thickness accuracy of about an atomic layer. Therefore, variations in the tunnel barrier and the gate in one direction can be kept constant. In addition to this, since the layers can be stacked on the mesa with good controllability also in the second stacking direction, the dimensional variation in the two directions is suppressed, and the quantum confinement in the two directions is facilitated by making the film as thin as the wavelength of electrons. realizable.

Further, since the potential change of the first laminated structure corresponds to the electron density change of the conductive region in the second laminated structure, the electric conduction region is aligned with the gate region formed by the first laminated structure. 3 and 5 can be formed.
In addition, since the electrically conductive regions 3 and 5 can be formed at a position away from the mesa, the influence of defects on the mesa generated during the mesa etching process is small. Further, a new gate 2 can be added to the substrate surface, a dual gate structure can be easily realized, and electrodes can be easily formed from the substrate surface.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view of an element structure showing a semiconductor device according to a first embodiment of the present invention, and FIG.
FIG. 9 is a sectional view taken along line AA ′ of FIG.

The transistor region is formed on the semiconductor mesa 15, and a channel region is formed on the mesa 15 via the gate insulating film 9 for the gate electrode 2. In the channel region, the first conductive layer 3, the second conductive layers 5, 5 ',
The tunnel barrier 4 is formed, and the epitaxial layer 10 is formed thereon. An n-type diffusion layer is formed in the first conductive layer and serves as a source 1 and a drain 1'of the planar MOS transistor.

On the substrate on which the semiconductor mesa is formed, the n-type semiconductor layer 7, the p-type semiconductor layer 8, the n-type semiconductor layer 2, the p-type semiconductor layer 8 and the n-type semiconductor layer 7 are epitaxially formed. 2 is a gate electrode. Further, since these p-type semiconductor layers have a higher potential for electrons than the n-type semiconductor layers, a potential barrier for electrons is formed in the channel region on the p-type semiconductor layer as the tunnel barrier 4 as shown in FIG. There is.

In the present embodiment, the capacitance sandwiching the tunnel barrier 4 is increased by increasing the barrier thickness, and the electric conduction region 3 of FIG. 2 is narrowed in the direction perpendicular to the paper surface.
A single electron transistor can be realized by reducing the capacitance of the electrically conductive region 3 with respect to the gates 2 and 5, 5 ', and making it possible to observe the potential change in the region 3 due to one-electron charging.

Next, a method of manufacturing the device of this embodiment will be described. 3 to 5 are process cross-sectional views corresponding to the cross-section of FIG.

First, as shown in FIG. 3, for example, semi-insulating Ga is used.
On the As (100) substrate 6, for example, a silicon concentration of 10 ¹⁷
cm ⁻³ n-type AlGaAs layer 7, beryllium concentration 10 ¹⁸
cm ⁻³ p-type AlGaAs layer 8, silicon concentration 10 ¹⁸ c
m ⁻³ n-type GaAs layer 7 (gate 2), beryllium concentration 10 ¹⁸ cm ⁻³ p-type AlGaAs layer 8, silicon concentration 1
The 0 ¹⁷ cm ⁻³ n-type AlGaAs layer 7 is grown by, for example, the molecular beam epitaxial growth method. The respective film thicknesses are, for example, 0.5 μm, 0.05 μm, 0.05 μm, 0.0
The thickness is 5 μm and 0.20 μm. By adding impurities at the same time during growth, a steep impurity distribution is formed.
The molar ratio of Al to Ga of AlGaAs is 0.2, for example.
5: 0.75.

Next, after covering the portion other than the portion where the mesa is exposed with lithography and a resist, for example, as shown in FIG.
The mesa is formed by an anisotropic etching solution such as brom methanol. The depth of the mesa is, for example, up to the semiconductor substrate 6. Then, the resist is ashed and removed.

Next, as shown in FIG. 5, for example, an n-type AlGaAs layer 9 having a silicon concentration of 10 ¹⁷ cm ^-3 , a GaAs channel layer 5 without addition of impurities, and an epitaxial layer 10 are formed.
For example, it is formed by a molecular beam epitaxial growth method. The respective film thicknesses are, for example, 0.1 μm and 0.3 μm.

After that, for example, using AuSi,
An ohmic electrode is formed for the drain diffusion layer 1 and the gate 2. To form the gate 2, selective etching of AlGaAs and GaAs is used, and n-type Al is formed from the surface.
The GaAs layer 7 and the p-type AlGaAs layer 8 can be etched to selectively make contact with the gate 2 of the n-type GaAs layer.

In this embodiment, since the thickness of the first laminated structure can be controlled in the order of atomic layers, the tunnel barrier can be formed with good reproducibility without lithography. Further, in the embodiment, a further gate electrode 2 ′ may be formed on the epitaxial layer 10. Furthermore, instead of 2, the n-type epitaxial layer 7 may be used as the gate electrode.

(Embodiment 2) FIG. 6 is a cross-sectional view of an element structure showing a semiconductor device according to a second embodiment of the present invention. The same parts as those in FIGS. 1 and 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

The cross-sectional structure of this embodiment is basically the same as that of the first embodiment, but the gate electrode 2 and the barrier forming p are formed.
The GaAs layer 8 is periodically repeated to form a superlattice potential in the channel region, and the gate 2'is formed on the surface, which is different from the first embodiment.

This structure is an embodiment for a superlattice FET. When this structure is used, the amplitude of the superlattice potential is changed by changing the gate voltage of 2, and the surface gate independently controls the overall electron density. Can be changed to
It has the advantage that nonlinear control such as Bragg reflection of superlattice is easy.

(Embodiment 3) FIG. 7 is a plan view showing an element structure of a semiconductor device according to a third embodiment of the present invention, FIG.
9 and 10 are sectional views taken along the lines AA ', BB', and CC 'in FIG. The same parts as those in FIGS. 1 and 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, unlike the first and second embodiments in which the tunnel barrier 4 is formed in the direction parallel to the mesa surface 15, the tunnel barrier 4 is formed in the direction perpendicular to the mesa surface. The conductive layer 3 and the second conductive layer 5 have a laminated structure. In the present embodiment, an electron wave directional coupling type switch is illustrated in order to show that the first conductive layer 3 and the second conductive layer 5 can have electrodes respectively.

The active device region is formed on the semiconductor mesa 15, and a channel region is formed on the mesa 15 via the gate insulating film 9 for the gate electrode 2. From the bottom, the channel region includes the first conductive layer 3, the tunnel barrier 4, the second conductive layer 5, the upper gates 2 ′, 2 ″,
2 "'for gate insulating layer 9', upper gate 2 ',
2 ″, 2 ′ ″ are formed. The first conductive layer 3 and the second conductive layer 3
The n-type diffusion layer is formed in the conductive layer 5 to form the source 1 and the drain 1 ', 1 ". In the region where the gate is formed, the second laminated structure is patterned and the device when the upper gate is applied. The defect region 11 is formed by ion implantation or diffusion in order to improve the isolation.

Here, when a voltage is applied to the gate 2 in the positive direction, carriers exist in the second conductive layer 5 only above the gate 2 where the potential for electrons has decreased.
Therefore, as shown in FIG. 9, the drain 1 ″ that does not exist on the gate 2 serves as a contact only to the first conductive layer 3. On the other hand, as shown in FIG. 10, the upper gates 2 ″ and 2 ″ are provided. 'By applying a negative voltage to
The conductive layer 3 can be selectively depleted. Therefore, the source 1 and the drain 1 ′ are contacts only to the first conductive layer 5.

The electron-wave directional coupling type gate has a gate 2'which is a quantum mechanical coupling between two tunneling conductive layers.
It is a device that is controlled by, and changes the current distribution of each drain, and requires independent contacts to each of the above conductive layers.

Next, the manufacturing process of the semiconductor structure of this embodiment will be described with reference to FIGS. 11 to 14 are shown in FIG.
FIG. 6 is a process sectional view corresponding to a section of FIG.

First, for example, as shown in FIG.
On the aAs (100) substrate 6, for example, a beryllium concentration of 1
0 ¹⁸ cm ⁻³ p-type AlGaAs layer 8, silicon concentration 10
^{An 18} cm ⁻³ n-type GaAs layer 7 (gate 2) and a beryllium concentration of 10 ¹⁸ cm ⁻³ p-type AlGaAs layer 8 are formed by, for example, a molecular beam epitaxial growth method. The respective film thicknesses are, for example, 0.5 μm, 0.05 μm, and 0.20 μm. By adding impurities at the same time during growth, a steep impurity distribution is formed. Al and Al of AlGaAs
The molar ratio of a is, for example, 0.25: 0.75.

Next, after covering a portion other than the portion where the mesa is exposed with lithography and a resist, a mesa is formed with an anisotropic etching solution such as brommethanol as shown in FIG. The depth of the mesa is, for example, p-type Al below.
Up to the GaAs layer 8. Then, the resist is ashed and removed.

Next, as shown in FIG. 13, for example, an n-type AlGaAs layer 9 having a silicon concentration of 10 ¹⁷ cm ^-3 , a GaAs channel layer 5 without addition of impurities, and an Al without addition of impurities.
As tunnel barrier layer 4, GaAs channel layer 3 without impurities, n-type AlGa with a silicon concentration of 10 ¹⁸ cm ^-3
The As layer 9'is grown by, for example, the molecular beam epitaxial growth method. Each film thickness is, for example, 0.1 μm, 0.0
3 μm, 0.01 μm, 0.03 μm, 0.05 μm.

Next, as shown in FIG. 14, after the second laminated structure is etched by using lithography and etching, a defect 11 for preventing inversion is formed by ion implantation at the etching edge. Reactive ion etching may be used as the etching, and the etching damage may be substituted for 11.

After that, the source and
An ohmic electrode is formed for the drain diffusion layer 1 and the gate 2. To form the gate 2, selective etching of AlGaAs and GaAs is used to p-type Al from the surface.
By etching up to the GaAs layer 8, n-type Ga
The gate 2 of the As layer can be selectively contacted.

In this embodiment, since the tunnel barrier is formed in the stacking direction, a steep heterostructure can be obtained.
It is easy to realize a more uniform and favorable tunnel element. Furthermore, the reproducibility of the distance between the gate electrode 2 and the second conductor 5 from the back surface, which has been a problem in the conventional electron-wave directional coupling type switch using the quantum well, is good, and the second electrode is taken from the front surface. Therefore, the device can be formed with better controllability.

(Embodiment 4) FIG. 15 is a sectional view of an element structure showing a semiconductor device according to a fourth embodiment of the present invention.
The same parts as those in FIGS. 1 and 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the tunnel barrier 4 is formed in the direction perpendicular to the mesa surface, and the first conductive layer 3 and the second conductive layer 5 are formed.
And have a laminated structure. The second conductive layer 5 operates as a channel of the transistor and is connected to the source and drain diffusion layers 1 and 1 '. Further, the first conductive layer 3 operates as a floating gate, and together with the control gate 2, EP
It functions as a ROM. The manufacturing process of this embodiment is the third
Since it is almost the same as the embodiment of FIG.

In the present embodiment, since the tunnel barrier is formed by the epitaxial growth method, which has a very good thickness controllability, the film thickness of the ordinary silicon oxide film is smaller than that of the EPROM used for the tunnel barrier or hot electron barrier. A barrier can be formed with good controllability. In addition, the width of the n-type layer of the gate 2 can be narrowed regardless of lithography, and high integration can be easily achieved.

The present invention is not limited to the above embodiments. In the examples, the molecular beam epitaxial method (MBE) is shown as the method of forming the laminated film, but the epitaxial growth method capable of stacking with an accuracy of about an atomic layer, such as a metal organic CVD method (MOCVD) and a liquid phase growth method (LPE). If that's the case.

In the embodiment, the constituent materials 7 and 8 of the laminated film and the substrate 6 are made of AlGaAs / GaAs, but AlGaAs may be InAlAs or GaAs may be GaInAs, InP or Si. . In addition, Si / SiGe system and CaF ₂ / GaAs
Cobalt silicide or nickel silicide may be used as the material of the system and the gate 2. In addition, the place where AlGaAs is shown as the constituent material of the first and second laminated films is Ga
It may be As or vice versa. These materials can also be combined and implemented as a composite membrane. In addition, incidentally, silicon is changed to germanium, copper, and beryllium to zinc as an additive impurity, or P, As, Sb is used as an n-type impurity and B, Al is used as a p-type impurity in a Si / SiGe system.
May be used.

In the embodiment, the method of uniformly adding impurities has been described, but the impurities are added in a sheet shape to a certain growth surface.
So-called δ-doping may be used. At this time, the surface density of the impurities is, for example, 10 ¹² to 10 ¹³ cm ⁻² . In the examples, the anisotropic wet etching method using bromethanol was shown for forming the mesa, but the reactive ion etching method may be used. Although the method of ashing to remove the resist is shown as an example, it may be removed using an organic solvent. Although the semiconductor structure is formed on the GaAs substrate 1 in the embodiment, an SOI substrate, a GaAs substrate, or an InP substrate may be used instead.

In the third and fourth embodiments, the epitaxial growth method is used for forming the conductive layer and the gate insulating film 9'after forming the tunnel barrier, but it is not always necessary to use the epitaxial growth method here. Further, in Examples 3 and 4, 2
Although a conductive layer having a stacked layer is shown, a conductive layer having a stacked structure of three or more layers may be used. In the second embodiment, the number of gates 2 may be plural. Although the structure in which the impurity is added to the gate insulating film is illustrated in the embodiment, the impurity may not be added.

In addition, various modifications can be made without departing from the scope of the present invention.

[0049]

As described in detail above, according to the present invention, a first laminated structure including a gate is formed on a semiconductor substrate, a mesa is formed on the surface thereof, and a tunnel barrier region is included on the mesa. By forming the second laminated structure, the potential forming the tunnel barrier can be formed with good reproducibility by the first or second laminated structure without using lithography. Therefore, it is possible to provide a semiconductor device which can suppress variations in tunnel barrier between elements and can be realized at a constant interval without misalignment between a gate and a conduction region and which can be further miniaturized, and a manufacturing method thereof. it can.

[Brief description of drawings]

FIG. 1 is a sectional view of an element structure showing a semiconductor device according to a first embodiment.

FIG. 2 is a diagram showing a potential distribution for electrons in the AA ′ cross section of FIG. 1.

FIG. 3 is a sectional view showing a first stage of the manufacturing process of the first embodiment.

FIG. 4 is a sectional view showing a second stage of the manufacturing process of the first embodiment.

FIG. 5 is a sectional view showing a third stage of the manufacturing process of the first embodiment.

FIG. 6 is a sectional view of an element structure showing a semiconductor device according to a second embodiment.

FIG. 7 is a plan view of an element structure showing a semiconductor device according to a third embodiment.

8 is a cross-sectional view taken along the line AA ′ of FIG.

9 is a sectional view taken along the line BB ′ of FIG. 7.

10 is a sectional view taken along the line CC ′ of FIG. 7.

FIG. 11 is a sectional view showing a first stage of the manufacturing process of the third embodiment.

FIG. 12 is a sectional view showing a second stage of the manufacturing process of the third embodiment.

FIG. 13 is a sectional view showing a third stage of the manufacturing process of the third embodiment.

FIG. 14 is a sectional view showing a fourth stage of the manufacturing process of the third embodiment.

FIG. 15 is a sectional view of an element structure showing a semiconductor device according to a fourth embodiment.

FIG. 16 is a conceptual diagram of a single electron transistor.

FIG. 17 is a diagram illustrating a problem of a single electron transistor.

FIG. 18 is a cross-sectional view of a conventional edge electron transistor formed on a mesa.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Source or drain electrode 2 ... Gate electrode 3 ... 1st conductive area 4 ... Tunnel barrier layer 5 ... 2nd conductive area 6 ... Semiconductor substrate 7 ... N type epitaxial layer 8 ... P type epitaxial layer 9 ... Gate insulating film 10 ... Epitaxial layer 11 ... Defect introduction region 12 ... Back gate contact 13 ... GaAs layer 14 ... AlGaAs layer 15 ... Mesa

Claims (2)

[Claims] 1. A first electrode grown and formed on a semiconductor substrate, and a mesa formed in contact with the first electrode,
A first conductive layer grown and formed on the mesa; and a second conductive layer grown and formed on the mesa, wherein the carrier density of the first conductive layer is the voltage of the first electrode. And the wave function of the carrier of the first conductive layer partially spatially overlaps with the wave function of the second conductive layer. 2. The carrier density of the first conductive layer is changed by the voltage of the first electrode, and the wave function of the carrier of the first conductive layer partially spatially overlaps with the wave function of the second conductive layer. In the method for manufacturing a semiconductor device as described above, a step of epitaxially growing a first electrode on a semiconductor substrate, a step of patterning and etching the semiconductor to form a mesa in contact with the first electrode, and a step of forming a mesa on the mesa A method of manufacturing a semiconductor device, comprising: a step of epitaxially growing a first conductive layer; and a step of growing a second conductive layer on the mesa.