JPH08125036A - Mask rom device and its manufacture - Google Patents

Abstract

PURPOSE: To provide a program-system mask ROM device having short TAT and highly integrable. CONSTITUTION: The title mask ROW device has memory cell transistors M11 -Mmn with gate electrodes 36 arranged into the shape of a matrix, and the impurity concentration in the gate electrode 36a of a specific memory cell transistor M22 to be programmed differ from those of gate electrodes of other memory cell transistors not to be programmed. Or, the polarities of the impurities differ.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask ROM device, and more particularly to a mask ROM device having a short TAT and capable of high integration.

[0002]

2. Description of the Related Art In a semiconductor memory device such as a mask ROM, it is important that TAT is short. That is, it is better that the time from the acquisition of the program content data from the customer and the writing of this data to the shipping of the product is short.

Contact hole method and ion implantation method are well known as methods for writing program data to a mask ROM. The contact hole method is a method of performing programming depending on whether a contact hole that contacts the diffusion layer of the memory cell transistor is formed or whether a wiring that connects to the contact hole is formed. The ion implantation method is a method in which data is written by selectively performing ion implantation in an active region below a gate electrode of a memory cell transistor and changing a threshold voltage of the transistor. For example, B ⁺ (P-type impurity) is added to the channel portion of a specific N-type transistor for writing.
V _{th of the} transistor by implanting
Becomes high, and no current flows (does not turn on) even if the transistor is selected.

An example of a mask ROM device programmed by a contact hole method according to a conventional example will be described. 6 is a diagram showing a memory cell array of a mask ROM device programmed by a contact hole method, FIG. 7 is a plan view showing a pattern layout of the memory cell array shown in FIG. 6, and FIG. 8 is taken along line VII-VII shown in FIG. FIG. 9 is a cross-sectional view of an essential part showing a contact hole forming step, which is a programming step, as viewed from the same section side as FIG.

As shown in FIGS. 7 and 8, in a mask ROM programmed by the contact hole method, an element isolation region (LOCOS) 4 is formed in a predetermined pattern on the surface of the semiconductor substrate 2 and surrounded by the LOCOS 4. A gate insulating film 6 is formed on the surface of the semiconductor substrate 2. On the gate insulating film 6, the word lines W ₁ , W ₂ ,
W ₃ (also serving as a gate electrode) is formed in a predetermined pattern.

As shown in FIGS. 7 and 8, the surface region of the semiconductor substrate 2 is ion-implanted from above the word lines W ₁ , W ₂ and W ₃ , which are gate electrodes, to form the drain region 8a and the source region 8b. And are formed. The source region 8b is
It corresponds to the source line S shown in FIG. An interlayer insulating film 10 shown in FIG. 8 is formed on the word lines W ₁ , W ₂ and W ₃ which are gate electrodes.

As shown in FIG. 7, word lines W ₁ , W ₂ ,
Memory cell transistors M _{11 to} M _mn are formed at the intersections of W ₃ and the impurity diffusion layers 8a and 8b. When programming a specific memory cell transistor M ₂₂ , a contact hole is not formed only in the drain region 8a of the transistor M ₂₂ , but a contact hole 12 is formed in the drain regions 8a of the other memory cell transistors. That is, the contact hole 12 is formed according to the program specifications. Specifically, as shown in FIG. 9, when the program specifications are determined, a resist film 14 is formed on the interlayer insulating film 10, and the resist film 14 is formed according to the program specifications by photolithography. Then, the inter-layer insulating film 10 is etched by using the resist film 14 having the above pattern. As a result, the contact hole 12 only in the drain region 8a is formed of a specific memory cell transistor, a particular memory cell transistors M ^22, contact holes 12 are not formed.

Thereafter, the contact hole 12 is internally
Embedded wiring layers for bit lines such as aluminum metal wiring layers
Bit line B shown in FIG.₁ , B₂ , B₃ To form
As shown in FIG. 6, the feature that the contact hole is not formed
Memory cell transistor M_{twenty two}To bit line B₂ Contact
Not continued. Therefore, the memory cell transistor M _{twenty two}
Is the word line W₂ Bit line B₂ From
Current is not detected. That is, the program specifications
It is possible to store the corresponding data.

Next, an ion implantation program type mask ROM device will be described. 10 is a diagram showing a memory cell array of a mask ROM device programmed by an ion implantation method, FIG. 11 is a plan view showing a pattern layout of the memory cell array shown in FIG. 10, and FIG. 12 is taken along line XII-XII shown in FIG. FIG. 13 is a cross-sectional view of a main part, and FIG. 13 is a cross-sectional view of a main part showing an ion implantation step which is a programming step viewed from the same section side as FIG.

As shown in FIGS. 11 and 12, in the mask ROM programmed by the ion implantation method, the semiconductor substrate 2 is used.
An element isolation region (LOCOS) 4 is formed in a predetermined pattern on the surface of, and a gate insulating film 6 is formed on the surface of the semiconductor substrate 2 surrounded by the LOCOS 4. On the gate insulating film 6, the word lines W ₁ , W ₂ ,
The gate electrode 13 to be W ₃ is formed in a predetermined pattern.

As shown in FIGS. 11 and 12, the semiconductor substrate 2
Of the word lines W ₁ , W ₂ , W which are gate electrodes
By implanting ions from above ₃ , the drain region 8
a and the source region 8b are formed. Source region 8b
Corresponds to the source line S shown in FIG. Further, the interlayer insulating film 10 shown in FIG. 12 is formed on the word lines W ₁ , W ₂ and W ₃ which are the gate electrodes 13.

[0012] The interlayer insulating film 10, a contact hole 12 which opens toward the drain region 8a of the memory cell transistors M ₁₁ ~M _mn is is formed. Interlayer insulating film 10
A wiring layer 15 (see FIG. 12) to be the bit lines B _{1 to} B _n is formed on the above in a pattern orthogonal to the word lines W _{1 to} W _n so as to enter into each contact hole 12. ing. In the ion implantation method, one contact hole 12 may be provided for each pair of memory cell transistors adjacent in the vertical direction shown in FIG.

As shown in FIG. 11, word lines W ₁ , W
Memory cell transistors M _{11 to} M _mn are formed at the intersections of ₂ and W ₃ with the impurity diffusion layers 8 a and 8 b.
When programming a specific memory cell transistor M ₂₂ , as shown in FIG. 13, the gate insulating film 6 is formed on the surface of the semiconductor substrate 2 before the gate electrodes and the source / drain regions 8a and 8b are formed. Immediately after forming the film,
A resist film 20 is formed in a predetermined pattern and is formed of, for example, B ⁺
Ions are ion-implanted at a dose amount of 1 × 10 ¹¹ to 1 × 10 ¹⁴ / cm ² into a region where a channel 22 of a specific memory cell transistor will be formed. By performing this ion implantation, the threshold voltage V _th of the specific memory cell transistor rises from 1 V to about 5 V, and no current flows during reading. Note that the reverse method can also be used for programming.

[0014]

However, in the above-mentioned contact hole type program mask ROM device, the programming process is in the subsequent process, so that T
While it has the advantage of short AT, as shown in FIG.
Since one contact hole 12 is required for one memory cell, there is a problem that the memory cell area becomes large.

On the other hand, in the ion implantation type mask chrome apparatus, a method of implanting ions into the channel portion of the memory cell transistor and controlling the threshold voltage V _{th of the} transistor is used. As shown in FIG. While the area can be reduced and high integration can be achieved, there is a problem that TAT becomes long because the ion implantation, which is a programming step, is performed before and after the gate insulating film is formed.

Therefore, there is a demand for a program type mask ROM device which has a short TAT and can be highly integrated. The present invention has been made in view of such circumstances, and
An object of the present invention is to provide a program-type mask ROM device having a short AT and capable of high integration.

[0017]

To achieve the above object, a first mask ROM device according to the present invention is a mask ROM device in which memory cell transistors having gate electrodes are arranged in a matrix. The impurity concentration in the gate electrode of a specific memory cell transistor to be programmed is different from the impurity concentration in the gate electrode of another memory cell transistor that is not programmed.

[0018] and the impurity concentration of the gate electrode of the specific memory cell transistor to be the program, either the impurity concentration in the gate electrode of the other memory cell transistors is not the program, 1 × 10 ¹⁸ cm - ³ or less , and the other one is, 1 × 10 ¹⁹ cm - is preferably ³ or more.

It is preferable that the impurities of the gate electrode of the specific memory cell transistor to be programmed have the same polarity as the impurities of the gate electrode of the other memory cell transistor which is not programmed. A first mask ROM device manufacturing method according to the present invention comprises a step of forming a gate insulating film on a surface of a semiconductor substrate, and a step of forming a gate electrode doped with a relatively low concentration of impurities on the gate insulating film. After the step of forming, the step of forming an interlayer insulating film on the gate electrode, and the program specifications are determined,
For the gate electrode of a specific memory cell transistor,
Impurity having the same polarity as the impurity contained in the gate electrode is used to perform additional ion implantation so that the concentration of the impurity contained in the gate electrode of the specific memory cell transistor is contained in the gate electrodes of other memory cell transistors. And a step of setting the impurity concentration higher.

Before forming the interlayer insulating film, an insulating film containing an impurity having the same polarity as the impurity contained in the gate electrode is formed in the peripheral circuit region of the memory cell transistor, and then heat-treated, It is preferable to set a high concentration of impurities contained in the gate electrode of the peripheral circuit.

A second mask ROM device according to the present invention is
In a mask ROM device in which memory cell transistors having gate electrodes are arranged in a matrix, the polarity of impurities in a gate electrode of a specific memory cell transistor to be programmed is in a gate electrode of another memory cell transistor which is not programmed. The polarities of the impurities are different from each other.

A second method for manufacturing a mask ROM device according to the present invention comprises a step of forming a gate insulating film on the surface of a semiconductor substrate, and a first step of relatively low concentration on the gate insulating film.
A step of forming a gate electrode doped with impurities, a step of forming an interlayer insulating film on the gate electrode, and a step of forming a gate electrode with respect to a gate electrode of a specific memory cell transistor after the program specifications are determined. First included in
A second impurity having a polarity opposite to that of the impurity is used, and additional ion implantation is performed so that the concentration is higher than that of the first impurity, and the polarity of the impurity contained in the gate electrode of the specific memory cell transistor Is different from the polarity of impurities contained in the gate electrode of another memory cell transistor.

Before forming the interlayer insulating film, an insulating film containing an impurity having the same polarity as the first impurity contained in the gate electrode is formed in the peripheral circuit region of the memory cell transistor, and then heat treatment is performed. Therefore, it is preferable to set the concentration of impurities contained in the gate electrode of the peripheral circuit to be high.

[0024]

Operation: The threshold voltage V of the memory cell transistor
_th can be expressed by the following equation.

[0025]

[Formula 1] V_th= Φ_MS+ 2Φ_f+ Q_B/ C_ox Where Φ_MSIs the work function, Φ_fFermi Potentia
Le, Q_BIs the depletion charge, C _oxIs the gate capacitance.

Here, the gate capacitance C _ox is expressed by the following equation.

[0027]

## EQU00002 ## where _C.sub.ox = .epsilon. / T where .epsilon. Is the dielectric constant of the gate insulating film and t is the film thickness of the gate insulating film.

In the mask ROM device according to the first aspect of the present invention, the impurity concentration in the gate electrode of each memory cell transistor is controlled. From Equations 1 and 2, the threshold voltage V _th of the memory cell transistor becomes higher as the gate insulating film becomes thicker. Further, as shown in FIG. 2, the higher the impurity concentration in the gate electrode, the lower the substantial film thickness of the gate insulating film. Note that FIG. 2 shows the results when a polysilicon film is used as the gate electrode, N-type impurities are used as impurities to be doped into the polysilicon film, and a silicon oxide film is used as the gate insulating film.

According to the results shown in FIG. 2, when the impurity concentration in the gate electrode is 1 × 10 ²⁰ / cm ³ or less, the gate insulating film (silicon oxide film) is depleted due to the depletion effect of the gate electrode (polysilicon film). It can be seen that the substantial thickening of the film appears. For example, the impurity concentration in the gate electrode is 1 × 1
When it is 0 ¹⁹ / cm ³ or less, the substantial thickness t of the gate insulating film is t.
Has a thickness of 10 nm to 12 nm, which is about 20% thicker, and 10 nm to 20 n at 1 × 10 ¹⁸ / cm ³ or less.
It can be seen that the value becomes m, which is approximately doubled.

From the above equations 1 and 2 and the results shown in FIG. 2, it is understood that the threshold voltage V _th of the memory cell transistor can be changed by changing the concentration of the impurity contained in the gate electrode. . In the first mask ROM device according to the present invention, phosphorus is additionally ion-implanted into the gate electrode of the specific memory cell transistor to be programmed, so that the impurity concentration in the gate electrode of another memory cell transistor is higher than that of the other memory cell transistor. The programming is performed by setting it high and decreasing the V _th of the transistor. Alternatively, it is possible to perform programming by reducing only the impurity concentration in a specific gate electrode and increasing the threshold voltage V _th of the specific transistor.

That is, in the first memory cell transistor according to the present invention, by utilizing the depletion effect of the gate electrode, the threshold voltage V _th of the memory cell transistor is controlled without increasing the size of the memory cell. It becomes possible to do. In the mask ROM device according to the second aspect of the present invention, the polarities of the impurities in the gate electrodes of the individual memory cell transistors are controlled.

Since the threshold voltage V _th of the memory cell transistor depends on the work function difference Φ _MS from the above formula 1, in the present invention, the work function difference is controlled by controlling the polarity of the impurities in the gate electrode. It is possible to control Φ _MS and control the threshold voltage V _th of a specific memory cell transistor.

For example, if the polarity of the impurities in the gate electrode is changed from N type to P type, the threshold voltage V _th of the memory cell transistor can be increased by about 1 V due to the work function difference. is there. Of course, the reverse program is also possible. That is, in the second mask ROM according to the present invention, by controlling the polarities of the impurities in the gate electrodes of the individual memory cell transistors, the threshold voltage of the memory cell transistor can be increased without increasing the size of the memory cell. It becomes possible to control V _th .

In the method for manufacturing the mask ROM device according to the first and second aspects of the present invention, the programming step is performed by forming impurities in the ions in the gate electrode after forming the gate electrode. Therefore, it can be performed in a later step of the process, and thus TAT can be shortened.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A mask ROM device according to the present invention will be described below in detail with reference to the embodiments shown in the drawings. FIG. 1 is a diagram showing a memory cell array of a mask ROM device according to an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between the N-type impurity concentration in the gate electrode and the substantial film thickness of the gate insulating film, and FIG. FIG. 4 is a plan view showing the pattern layout of the memory cell array shown in FIG. 1, FIG. 4 is a cross-sectional view of an essential part taken along line IV-IV shown in FIG.
FIG. 6 is a cross-sectional view of an essential part showing a contact hole forming step which is a programming step viewed from the same section side as FIG. 4.

As shown in FIGS. 1, 3 and 4, in a mask ROM device according to an embodiment of the present invention, an element isolation region (LOCOS) 32 is formed in a predetermined pattern on the surface of a semiconductor substrate 30, A gate insulating film 34 is formed on the surface of the semiconductor substrate 30 surrounded by the LOCOS 32. The word lines W _{1 to} W shown in FIG. 3 are formed on the gate insulating film 34.
_m (also serving as the gate electrode 36) is formed in a predetermined pattern.

As shown in FIG. 3, the surface layer of the semiconductor substrate 30.
Is a word line W which is a gate electrode. ₁ ~ W_mFrom above
By injecting on, the drain region 42a and the source
A region 42b is formed. Source region 42b is
1 corresponds to the source line S shown in FIG. In addition, the gate electrode 36
Is the word line W₁ ~ W_mAbove the top is the interlayer edge shown in FIG.
A film 38 is formed.

The interlayer insulating film 38 is formed a contact hole 44 which opens toward the drain region 42a of the memory cell transistors M ₁₁ ~M _mn. Interlayer insulation film 3
Wiring layers 40 (see FIG. 4) to be the bit lines B _{1 to} B _n are formed on the wirings 8 in a pattern orthogonal to the word lines W _{1 to} W _n , and each contact hole 44 (see FIG. 3). It is designed to get inside. In the programming method of this embodiment, one contact hole 12 may be provided for each pair of memory cell transistors adjacent in the vertical direction shown in FIG.

As shown in FIG. 3, word lines W ₁ -W
_At the intersection of _m and the impurity diffusion layers 42a and 42b,
Memory cell transistors M _{11 to} M _mn are formed. In this example, to program a particular memory cell transistor M ₂₂ is only the gate electrode 36a of the memory cell transistor, by performing additional ion implantation, the concentration of the impurity contained in the gate electrode 36a , Is set higher than the gate electrodes 36 of other memory cell transistors. Alternatively, only compared to the gate electrode 36a of the particular memory cell transistors M _22, by not performing the additional ion implantation, the concentration of the impurity contained in the gate electrode 36a, the gate electrode 36 of the other memory cell transistors And set it low.

For example, the impurity concentration in the gate electrode 36a of the memory cell transistor M ₂₂ to be programmed is
1 × 10 ¹⁹ / cm ³ or more, or 1 × 10 ²⁰ / cm ³
With the above settings, the impurity concentration in the gate electrodes of the other memory cell transistors is set to 1 × 10 ¹⁸ / cm ³ or less. With this setting, the threshold voltage V _th of the specific memory cell transistor should be set sufficiently lower than those of the other memory cell transistors from the tendency shown in FIG. You can Therefore, it is easy to determine the data.

Next, a method for manufacturing the mask ROM according to this embodiment will be described with reference to FIGS.
As shown in FIG. 5A, first, LO is formed on the surface of the semiconductor substrate 30 by a selective thermal oxidation method using a silicon nitride film.
COS 32 is formed. As the semiconductor substrate 30, for example, in the case of forming an N-channel type transistor, P
A type single crystal silicon wafer or an N type single crystal silicon wafer having a P well formed on its surface is used. Further, when forming a P-channel type transistor, an N-type single crystal silicon wafer or a P-type single crystal silicon wafer having an N well formed on the surface thereof is used. In the following description, a case where an N channel type MOS transistor is used as the memory cell transistor will be described as an example. The LOCOS 32 is made of silicon oxide.

Next, a gate insulating film 34 is formed on the surface of the semiconductor substrate 30 surrounded by the LOCOS 32. The gate insulating film 34 is formed by, for example, a thermal oxidation method, and is composed of a silicon oxide film having a thickness of about 10 nm or less. Next, as shown in FIG. 5B, a low concentration (1 × 10 ¹⁸ / c
A gate electrode 36 having an N-type impurity of m ³ or less) is formed on the gate insulating film 34 and the LOCOS 32.
The gate electrode 36 is formed of, for example, a polysilicon film or a polycide film which is a laminated film of a polysilicon film and a silicide film (for example, a tungsten silicide film), and its film thickness is not particularly limited, but is 200 nm.
It is about the following. To form this gate electrode 36,
After a non-doped polysilicon film or polycide film is formed on the entire surface of the substrate, phosphorus (Phos ⁺ ) ions are ion-implanted at a dose of about 1 × 10 ¹² to 1 × 10 ¹⁵ / cm ² , and then the word line Etch into a pattern.

Next, as shown in FIG. 5C, an impurity-containing insulating film 37 is deposited on the gate electrode 36 by CVD or the like. The impurity-containing extinction film is not particularly limited, but in the present embodiment, for example, P containing 3 to 5% by weight of phosphorus is used.
An SG film (phosphorus-doped glass film) is used. The film thickness is not particularly limited, but is, for example, about 200 nm or less.

Next, as shown in FIG. 5D, the impurity-containing insulating film 37 in the memory cell region (the region where the memory cells are formed in a matrix) is removed. However, the impurity-containing insulating film 37 in the peripheral circuit is not removed. After that, the substrate 30 is annealed at about 900 ° C. for about 30 minutes. As a result, the phosphorus concentration in the gate electrode in the memory cell region can be set as low as 1 × 10 ¹⁸ / cm ³ or less, and the phosphorus concentration in the gate electrode of the transistor in the other peripheral circuits can be set to that of phosphorus from the PSG film. By diffusion,
It is set as high as 1 × 10 ²¹ / cm ³ and does not limit the capacity of the transistor.

After that, ion implantation for forming source / drain regions is performed from above the gate electrode to form an interlayer insulating film 38 as shown in FIG. 5 (E). The interlayer insulating film 38 is not particularly limited, but is made of, for example, a silicon oxide film. After that, when the program specifications are determined, a resist film 46 is formed on the interlayer insulating film 38,
The resist film 46 is processed by photolithography according to the program specifications. Thereafter, the opening 48 formed in the resist film 46, to the gate electrode 36a of the specific memory cell transistor M ₂₂ shown in FIG. 3, phosphorus (Pho
s ⁺ ) ions are additionally ion-implanted with an implantation energy of 200 KeV to 2 MeV and a dose amount of about 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ² . As a result, in the gate electrode 36a of the specific memory cell transistor M _22, the concentration of phosphorus as an impurity ^{1 × 10 19 ~1 × 10 20} / cm
It is set to about ³ or more.

Therefore, only the threshold voltage of the specific memory cell transistor M ₂₂ becomes lower than the others, and programming becomes possible. Note that programming can also be performed by performing additional ion implantation to the gate electrodes of memory cell transistors other than the specific memory cell transistor M ₂₂ . Further, the type of the impurity for performing the additional ion implantation is not particularly limited as long as it is the same as the polarity of the impurity initially contained in the gate electrode.

Next, another embodiment of the present invention will be described. In the following embodiment, the steps up to the middle are the same as those in the above embodiment, and the description thereof will be omitted. In this embodiment, as shown in FIG. 5E, a resist film 46 is formed on the interlayer insulating film 38 at the stage when the program specifications are determined,
The resist film 46 is processed by photolithography according to the program specifications. Then, from the opening 48 formed in the resist film 46, boron (B ⁺ ) ions are implanted into the gate electrode 36a of the specific memory cell transistor M ₂₂ shown in FIG. 3 with an implantation energy of 100 KeV to 2 MeV, 1 × 10 3. Additional ion implantation is performed with a dose amount of about ¹⁴ to 1 × 10 ¹⁶ / cm ² . As a result, in the gate electrode 36a of the specific memory cell transistors M _22, it contains boron as an impurity, the concentration of 1 × 10 ¹⁹ ~
It is set to about 1 × 10 ²⁰ / cm ³ or more, and the gate electrode changes to P type.

Therefore, due to the work function difference, only the threshold voltage of the specific memory cell transistor M ₂₂ can be set higher by about 1 V as compared with the others, and the programming becomes possible. Note that programming can also be performed by performing additional ion implantation to the gate electrodes of memory cell transistors other than the specific memory cell transistor M ₂₂ . Further, the type of the impurity for performing the additional ion implantation is not particularly limited as long as it is opposite to the polarity of the impurity initially contained in the gate electrode.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention.

[0050]

As described above, in the first memory cell transistor according to the present invention, by utilizing the depletion effect of the gate electrode, the memory cell transistor can be formed without increasing the size of the memory cell. It becomes possible to control the threshold voltage V _th .

Further, in the second mask ROM according to the present invention, the polarity of the impurities in the gate electrode of the memory cell transistor here is controlled, so that the memory cell transistor can be formed without increasing the size of the memory cell transistor. It becomes possible to control the threshold voltage V _th .

In the method of manufacturing the mask ROM device according to the first and second aspects of the present invention, the program step is performed by forming impurities in the ions in the gate electrode after forming the gate electrode. Therefore, it can be performed in a later step of the process, and thus TAT can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a memory cell array of a mask ROM device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an N-type impurity concentration in a gate electrode and a substantial film thickness of a gate insulating film.

3 is a plan view showing a pattern layout of the memory cell array shown in FIG.

FIG. 4 is a cross-sectional view of main parts taken along the line IV-IV shown in FIG.

5A to 5E are main-portion cross-sectional views showing a contact hole forming step which is a programming step as viewed from the same cross-sectional side as FIG.

FIG. 6 is a diagram showing a memory cell array of a mask ROM device programmed by a contact hole method.

7 is a plan view showing a pattern layout of the memory cell array shown in FIG.

8 is a cross-sectional view of a main part taken along the line VII-VII shown in FIG.

9 is a main-portion cross-sectional view showing a contact hole forming step which is a programming step viewed from the same cross-sectional side as FIG.

FIG. 10 is a diagram showing a memory cell array of a mask ROM device programmed by an ion implantation method.

11 is a plan view showing a pattern layout of the memory cell array shown in FIG.

12 is a cross-sectional view of essential parts taken along line XII-XII shown in FIG.

13 is a fragmentary cross-sectional view showing an ion implantation step, which is a programming step, viewed from the same section side as FIG.

[Explanation of symbols]

30 ... semiconductor substrate 32 ... LOCOS 34 ... gate insulating film 36, 36a ... gate electrode 38 ... interlayer insulation film 40 ... wiring layer M ₁₁ ~M _mn ... memory cell transistor B ₁ .about.B _n ... bit lines W ₁ to _W-m ... Word line

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 21/265 21/76 H01L 21/265 W 21/76 M

Claims (8)

[Claims] 1. A mask ROM device in which memory cell transistors having gate electrodes are arranged in a matrix, and the impurity concentration in the gate electrode of a specific memory cell transistor to be programmed is not programmed. The mask ROM device is different from the impurity concentration in the gate electrode of the above. 2. One of the impurity concentration of the gate electrode of the specific memory cell transistor to be programmed and the impurity concentration of the gate electrode of the other memory cell transistor which is not programmed is 1 × 10 ¹⁸ cm ^−. 3
Hereinafter, and the other one is, 1 × 10 ¹⁹ cm - ³ or more in the mask ROM according to claim 1. 3. The impurity of the gate electrode of the specific memory cell transistor to be programmed and the impurity in the gate electrode of the other memory cell transistor which is not programmed have the same polarity. Mask ROM device. 4. A step of forming a gate insulating film on the surface of a semiconductor substrate, a step of forming a gate electrode doped with a relatively low concentration of impurities on the gate insulating film, and a step of forming a gate electrode on the gate electrode. After the step of forming the interlayer insulating film and the program specifications are determined, additional ion implantation is performed on the gate electrode of the specific memory cell transistor by using an impurity having the same polarity as the impurity contained in the gate electrode. A step of setting the concentration of impurities contained in the gate electrode of a specific memory cell transistor higher than the concentration of impurities contained in the gate electrode of another memory cell transistor. 5. An insulating film containing impurities of the same polarity as the impurities contained in the gate electrode is formed in the peripheral circuit region of the memory cell transistor before forming the interlayer insulating film, and then heat treatment is performed. 5. The method for manufacturing a mask ROM device according to claim 4, wherein the concentration of impurities contained in the gate electrode of the peripheral circuit is set high. 6. A mask ROM device in which memory cell transistors having gate electrodes are arranged in a matrix, and the polarity of impurities in a gate electrode of a specific memory cell transistor to be programmed is not programmed. A mask ROM device in which the polarities of impurities in the gate electrode of a transistor are different from each other. 7. A step of forming a gate insulating film on a surface of a semiconductor substrate; a step of forming a gate electrode doped with a relatively low concentration of a first impurity on the gate insulating film; After the step of forming the interlayer insulating film and the program specifications are determined, a second impurity having a polarity opposite to the first impurity contained in the gate electrode is applied to the gate electrode of the specific memory cell transistor. By using additional ion implantation so that the concentration is higher than the concentration of the first impurity, the polarity of the impurity contained in the gate electrode of a specific memory cell transistor is changed to that in the gate electrode of another memory cell transistor. A method of manufacturing a mask ROM device, the method including the step of changing the polarity of impurities contained in the mask ROM device. 8. An insulating film containing an impurity having the same polarity as the first impurity contained in the gate electrode is formed in the peripheral circuit region of the memory cell transistor before forming the interlayer insulating film, and then heat treatment is performed. By this, the concentration of impurities contained in the gate electrode of the peripheral circuit is set high.
A method for manufacturing the mask ROM device according to 1.