JP4223551B2 - Method for manufacturing floating gate nonvolatile memory device - Google Patents

Description

The present invention relates to a first MOS transistor having an insulating gate made of polycrystalline or amorphous silicon, a gate made of polycrystalline or amorphous silicon that is electrically floated, and electrically located from the floating gate located above the floating gate. The invention relates to a semiconductor device having a semiconductor body made of silicon, on the surface of which a nonvolatile writable memory element in the form of a second MOS transistor having a control electrode of polycrystalline or amorphous silicon that is insulated. is there. The present invention also provides a first MOS transistor having an insulating gate made of polycrystalline or amorphous silicon, a gate made of polycrystalline or amorphous silicon that is electrically floated, and the floating gate. Device manufacture having a semiconductor body made of silicon, on the surface of which a nonvolatile writable memory element in the form of a second MOS transistor having a control electrode of polycrystalline or amorphous silicon which is electrically insulated It is about the method.
The term “poly” is abbreviated in the following description, and this term includes not only single crystal silicon but also amorphous silicon.
This semiconductor device and a method for manufacturing this semiconductor device are known from the applicant's US Pat. No. 5,395,778. This memory element and a number of similar elements form part of a non-volatile memory, commonly known by the name of EEPROM or (flash) EPROM. This memory element can be of an isolated type, in which case the semiconductor device can be mainly composed of a memory and peripheral electronic circuits necessary for this memory. Therefore, the first MOS transistor described above can be formed by a transistor in a peripheral circuit, but can also be formed by a select transistor that forms a memory cell together with a memory semiconductor. While not particularly limited, in another example where the invention is particularly important, the memory can be embedded and the semiconductor device can be integrated with an integrated signal processing circuit having a non-volatile memory embedded therein. can do. In order to manufacture such a circuit, a standard CMOS process is widely used which includes several additional processing steps for the memory of the signal processing part (hereinafter referred to as logic). As is generally known, information is written in the form of charge that is stored in the floating gate and defines the threshold voltage of the transistor. When an appropriate voltage is applied to the control electrode, whether or not the transistor is turned on is confirmed, so that information can be read out.
U.S. Pat. No. 5,395,778 describes a process in which the floating gate and the limiting electrode are formed by a split poly process where the poly deposition necessary to form the logic gate is performed in two steps. In the first step, a first partial layer for logic is formed with a floating gate poly layer, and then an interlayer dielectric is formed in this layer. In the second step, the remaining portion of the poly layer is formed for the logic gate, and at the same time, the poly for the control electrode is formed on the floating gate poly layer by being electrically insulated by an interlayer dielectric.
In this process, the logic poly layer has a thickness that is greater than the thickness of the memory control electrode poly layer, which under certain circumstances is a drawback. That is, when the control electrode and the logic insulated gate are simultaneously defined and etched, it is necessary to over-etch the memory portion. Another disadvantage may arise when spacers are formed on the sides of the control electrode and insulated gate by deposition and oxide layer etchback. In this case, the oxide layer in the memory part may be relatively etched too much as a result of the thickness difference between the poly layers. As a result, when silicide contacts are formed in the source and drain regions and the gate in the known salicide process, a short circuit (bridge) may occur.
The object of the present invention is to eliminate at least most of these drawbacks. To achieve this object, in the present invention, in the semiconductor device of the type described at the beginning of the specification, the thickness of the insulated gate is equal to or greater than the thickness of the floating gate, It is characterized by being equal to or at least approximately equal to the thickness of the control electrode. If the control electrode of the memory transistor has the same thickness as the insulated gate of the MOS logic transistor, the above-described problem can be solved.
The first embodiment of the present invention, which has the advantage that the insulated gate is formed from a single poly layer, comprises forming the floating gate and the insulated gate from a common first deposited silicon layer of equal thickness and The control electrode is formed from a second deposited silicon layer. In the second embodiment of the present invention, which has the advantage that the thickness of the floating gate can be selected independently from the thickness of the logic gate, the insulated gate and the control electrode have a thickness greater than that of the floating gate. It is characterized by. Since the thickness of the poly layer in this example can be reduced, the resulting structure is relatively planar, which is preferable in subsequent processing steps.
Another embodiment of the semiconductor device according to the present invention, which provides the advantage of low series resistance, is the use of a relatively low ohmic silicide of an alloy of silicon and metal in the control electrode, insulated gate and source and drain regions of the MOS transistor. An upper layer is provided. The silicide is preferably formed, for example, by a self-aligned method (salicide) with a Ti layer, which forms a silicide in contact with silicon and does not change when in contact with the oxide, and is a region of the oxide. Can be selectively removed.
According to the invention, in a method of the type mentioned at the beginning of the description,
Defining a first active region for a first MOS transistor and an active region of region 2 for a second MOS transistor on the surface of the semiconductor body;
Providing electrically insulating layers in the first and second active regions to form gate dielectric layers of the first and second MOS transistors, respectively;
Depositing a first polycrystalline or amorphous silicon layer separated by the insulating layer on the first and second active regions;
Forming a dielectric layer on the first silicon layer;
A second polycrystalline or amorphous silicon layer separated by the dielectric layer is deposited on the first silicon layer, and the thickness of the second silicon layer is at least equal to the thickness of the first silicon layer. Almost equal,
Removing the second silicon layer of the first active region;
The floating gate, the control electrode, and the insulated gate are defined from the deposited silicon layer. The problems described above can be easily solved by this method. After depositing the first poly layer, the process masks the logic area on the surface with the first poly layer, first forming the floating gate, then the source and drain regions of the memory transistor, and then The logic portion can be formed in the second processing step. This can achieve the advantages of the process described in US Pat. No. 5,395,778, the contents of which are hereby incorporated by reference.
Another important embodiment of the method according to the present invention, which can obtain a small series resistance in a simple manner, is an alloy of silicon and metal by salicide treatment in the source and drain regions, control electrodes and insulated gates of MOS transistors. An upper layer of the silicide is formed.
Hereinafter, the present invention will be described in detail with reference to the accompanying drawings and embodiments.
1 to 8 show cross sections in a manufacturing process of a semiconductor device according to the present invention.
FIG. 9 shows a variation of the device being manufactured.
A first embodiment of an integrated circuit having three layers of polycrystalline silicon, hereinafter referred to as poly A, B and C, will be described with reference to FIGS. The process starts with a silicon body having a first conductivity type, in this case a p-type surface 2 and a surface region 1 adjacent. An active region is defined in the surface region 1 by the pattern of the field oxide film 3, and two active regions are illustrated as regions 4 and 5. The active region 4 is for a memory cell, and the region 5 is for a logic MOS transistor, hereinafter referred to as MOST. The field oxide film can be formed by an ordinary method such as local oxidation of a silicon body, and has a thickness of, for example, 550 nm. After the oxidation step, the oxidation mask is removed and various ion implantations can be performed if desired, for example, n-well ion implantation for the p-channel transistor to be formed. In the next step, a gate dielectric layer 6 in the form of a silicon oxide film, for example of 12 nm thickness, is formed on the surface. Although the gate dielectric layer of this example has the same thickness in the active region, this need not be the case. Accordingly, the thickness of the gate oxide film of the MOST is different from the thickness of the gate oxide film of the memory transistor. The first polycrystalline or amorphous silicon layer 7, ie poly A, is deposited to a thickness of, for example, 150 nm. This poly layer is doped with n-type impurities during or after deposition, for example, using phosphorous at a concentration of about 1.3 × 10 ¹⁹ atoms per cm ³ . The poly layer 7 of this example is covered with a layer 8 that masks the poly layer from oxidation, and this layer 8 is composed of an oxynitride layer or a composite layer of a silicon oxide layer and a nitride. Next, a photoresist mask 9 is formed to cover the active region 5 of the logic MOST and define the floating gate of the active region 4 of the memory cell. Next, the layer 8 and the poly layer 7 are etched into a pattern, thereby forming the floating gate 10 in the active region 4. The active area 5 is kept covered with the poly layer A over its entire surface. This process is shown in FIG.
In this step, the mask 9 is removed, and n-type source and drain regions 11 and 12 of the memory transistor are formed by ion-implanting arsenic with an impurity concentration of 3 × 10 ¹⁵ per cm ² and energy of about 60 keV, for example. . If desired, for example in the case of an OTP (One Time Programmable) memory, the background concentration of boron in the vicinity of regions 11 and 12 is 10 ¹⁴ impurity concentration per cm ² as shown diagrammatically as regions 13 and 14 in FIG. Can be enhanced by ion implantation of boron with an energy of about 20 keV. These p-type regions are not shown in the next step shown in the drawing. In the case of a flash memory, a region to which an impurity having a relatively low concentration is added in the vicinity of the source region 11 instead of the p-type region 13 in this step. Next, an oxide layer 15 is grown on the side of the poly layer by thermal oxidation, while the upper side of the poly layer is masked by the layer 8 during this time. FIG. 2 shows the device in this manufacturing process.
In the next step, layer 8 is removed to form a layer 16 having a thickness of about 35 nm that constitutes an interlayer polydielectric (IPD) between the floating gate of the memory cell and the control electrode. In this example, this layer is a silicon oxynitride layer, but it can be composed of a composite oxide layer-nitride layer-oxide layer (OND) having a thickness of about 35 nm. Obviously, it can also be configured. A second poly (or amorphous) layer 17, poly B, is deposited on layer 16. This layer 17 has a thickness equal to or at least approximately equal to the thickness of the first poly layer, ie a thickness of about 150 nm. This layer 17 is doped with n-type impurities by ion implantation of phosphorus at a concentration equal to or approximately equal to the concentration of poly A. Next, the memory area 4 is masked with the photomask 18. This process is shown in FIG.
The poly-layer 17 and the layer 16 in the active region 5 that are not masked by the mask 18 are removed, and only the poly layer equal to the thickness of the poly-layer 17 is left in the active region. Next, the photomask 18 is removed. The device of this process is shown in FIG.
In the next step, a third poly layer 19, poly C, is deposited, which is doped with n-type impurities at a concentration equal to or approximately equal to the concentration of the previous poly layer. The thickness of the poly layer in this example is also 150 nm, and is equal to the thickness of the poly layers 7 and 17. On the other hand, as a modification, the thickness of the poly layer 19 can have different values, for example, the gate to be formed can be selected to have an appropriate resistance value. Next, as shown in FIG. 5, a new photomask 20 that defines the control electrode of the memory transistor in the active region 4 and the gate of the logic MOS transistor in the active region 5 is formed. Next, the unmasked poly layer is removed by etching (FIG. 6), and the control electrode 21 of the memory transistor and the insulated gate of the logic MOST are formed. Since the gates 21 and 22 are equal, or at least approximately equal in thickness, in this case the over-etch often required when etching layers of different thickness is unnecessary. Thereafter, the mask 20 is removed again.
In the next step, a photo-oxidation step is performed to cover the sides of the poly gates 21 and 22 with oxide. Next, an LDD structure is formed in the active region 5. In the next step, spacers 23 are formed on the sides of the gates 21 and 22 by a known method such as deposition of an oxide layer and etching back. In this connection, the spacers on the gate electrodes 21 and 22 are approximately the same size, which is important in the subsequent salicide process. Next, the source region and the drain regions 24 and 25 are formed by implanting arsenic ions using the spacer 23 acting as a mask. These regions are separated from the channel region of the transistor by LDD regions 24a and 25a. After removing the mask used for this and the exposed parts of the layer 16 and the silicon layer 6, a Ti layer 26 is formed on the surface, thereby obtaining the state shown in FIG. As is apparent from the drawing, the Ti layer 26 is in local contact with the silicon body 1 and the polygates 21 and 22 and in contact with the silicon oxide in the region of the spacer 23 and the field oxide film 3. This Ti forms titanium silicide on the poly gates 21 and 22 and on the source and drain regions of the transistor under heat treatment, and does not change on the field oxide film 3. At the side of the spacer 23, only the portion of the Ti adjacent to the source and drain regions and the gate electrode is converted into silicide due to silicon diffusion, and the spacer is covered with Ti for the remaining portion. Since the control electrode of the memory transistor and the gate 22 of the logic transistor are actually equal in thickness, the spacer 23 is also formed at an actually equal height and the possibility of bridging is very small. The remaining Ti is removed from the side portions of the field oxide film 3 and the spacer 23 by a selective etching process, and Ti is removed faster than the titanium silicide by the selective etching. The silicide contact 27 is obtained.
The device is then subjected to other conventional processes such as forming a conductive connection with one or several metal layers and forming a glass layer. These steps are generally known and will not be described in detail.
In the embodiment described here, the entire floating gate 10 is formed from the poly layer A and the gate 22 is partially formed, followed by the formation of two poly layers, ie the control electrodes 21 (partially). A poly layer C forming the poly layer B and the remaining portions of the control electrode 21 and the gate 22 was formed. This embodiment has the advantage that the thickness of the floating gate can be independently selected over a relatively wide range. A possible disadvantage is that the control electrode 21 and the gate 22 are formed of a composite poly layer, so that the gate is depleted by an oxide layer between the poly layers, which forms a barrier against impurities during doping. However, the impurity concentration of poly becomes too low. In order to eliminate this drawback, a modification of the above-described processing process will be described with reference to FIG. The step shown in FIG. 9 corresponds to the step shown in FIG. 7 in which the Ti layer 26 is deposited as the first process.
In this modification, the thickness of the poly layer A is about 300 nm, that is, twice the thickness of the first embodiment. As a method similar to that described above, the floating gate of the memory transistor is formed from this poly layer. The processing steps so far and the step shown in FIG. 4 are performed while the active region 5 of the logic transistor is covered with the poly layer A. The poly layer B for forming the control electrode 21 of the memory transistor is also about 300 nm thick. Next, the control electrode 21 of the memory transistor and the gate 22 of the logic transistor are formed by a mask corresponding to the mask 20 of the previous embodiment (FIG. 5). The other processing steps are the same as in the previous embodiment. Since the control electrode 21 and the gate 22 have the same thickness, the above-described problems of over-etching and bridge formation can be solved and processing can be performed in a reproducible manner. Compared to the above-described embodiment, the planar structure is lowered by making the thickness of the floating gate 10 relatively large, or the subsequent processing steps are generally only slightly difficult. On the other hand, the structure of FIG. 9 has the advantage of preventing gate depletion and the advantage that the floating gate has a large side surface, so that the capacitance between the overlapping control electrode 21 and the floating gate is reduced. It becomes relatively large.
The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention. Thus, the present invention achieves many advantages in embodiments that do not have a silicide layer. It is also possible to reverse the conductivity types of the embodiments described above. In the first embodiment of the process described above, the silicon oxynitride layer 8 can be eliminated if desired.

Claims (4)

A first MOS transistor having an insulating gate made of polycrystalline or amorphous silicon; an electrically floating polycrystalline or amorphous silicon gate; and a multi-layer which is located above the floating gate and electrically insulated from the floating gate. In manufacturing a semiconductor device having a semiconductor body made of silicon with a nonvolatile writable memory element in the form of a second MOS transistor having a control electrode of crystalline or amorphous silicon provided on the surface,
Defining a first active region for the first MOS transistor and a second active region for the second MOS transistor on a surface of the semiconductor body;
An electrically insulating layer is provided in the first active region and the second active region, and a gate dielectric layer of the first MOS transistor and a gate dielectric layer of the second MOS transistor are respectively provided. Forming,
Depositing a first polycrystalline or amorphous silicon layer separated by the insulating layer on the first active region and the second active region;
Forming a dielectric layer on the first polycrystalline or amorphous silicon layer;
A second polycrystalline or amorphous silicon layer separated by the dielectric layer is deposited on the first polycrystalline or amorphous silicon layer, and the thickness of the second polycrystalline or amorphous silicon layer is set to the thickness of the second polycrystalline or amorphous silicon layer. Equal to the thickness of the first polycrystalline or amorphous silicon layer;
Removing the second polycrystalline or amorphous silicon layer on the first active region;
The floating gate, the control electrode, and the insulated gate are defined from the deposited first and second polycrystalline or amorphous silicon layers, and the floating gate deposits the second polycrystalline or amorphous silicon layer. Defined by forming from the first polycrystalline or amorphous silicon layer, and after forming the floating gate,
The source region and the drain region of the second MOS transistor are provided by doping the first active region while masking the impurity addition by the first polycrystalline or amorphous silicon layer.
A method for manufacturing a semiconductor device. After removing the second polycrystalline or amorphous silicon layer on the first active region, a third polycrystalline or amorphous silicon layer is deposited on the first active region, and the control electrode and the 2. The method of claim 1, wherein an insulated gate is formed from a combination of the second polycrystalline or amorphous silicon layer and the third polycrystalline or amorphous silicon layer. The method of claim 1 wherein the floating gate side is covered with a silicon oxide layer by thermal oxidation prior to depositing the second polycrystalline or amorphous silicon layer. An upper layer of a silicide of an alloy of silicon and metal is formed by salicide treatment in the source region and drain region of the first and second MOS transistors, the control electrode, and the insulating gate. Item 4. The method according to any one of Items 1 to 3.

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