JPH08125009A - Planar semiconductor element and its manufacture - Google Patents
Planar semiconductor element and its manufactureInfo
- Publication number
- JPH08125009A JPH08125009A JP28150394A JP28150394A JPH08125009A JP H08125009 A JPH08125009 A JP H08125009A JP 28150394 A JP28150394 A JP 28150394A JP 28150394 A JP28150394 A JP 28150394A JP H08125009 A JPH08125009 A JP H08125009A
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- semiconductor device
- planar
- groove
- type region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000002161 passivation Methods 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000003989 dielectric material Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 4
- 229910017604 nitric acid Inorganic materials 0.000 claims description 4
- 238000003486 chemical etching Methods 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 2
- 238000007598 dipping method Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 239000011521 glass Substances 0.000 abstract description 3
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000011259 mixed solution Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はプレーナ型半導体素子お
よびその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar semiconductor device and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】プレーナ型半導体素子において、高電圧
印加時に、第２導電型領域の曲率半径の小さい部分に電
界が集中して破壊が起こる。これを、ｐｎ接合から生じ
る空乏層を横方向に伸ばす構造にして電界の集中を緩和
して高耐圧化することができる。この構造のことを、ｐ
ｎ接合の終端構造と言う。このｐｎ接合の終端構造とし
て従来は、図２に示すように、ｐ層の周囲にそって、５
〜７のようにｐ層よりなるガードリングをなん重かに形
成する構造が採用されている。この構造は、第１導電型
半導体基板１に第２導電型領域４としてｐ層を選択拡散
する工程で、同時に、ガードリング５〜７を拡散により
形成することにより得られる。ガードリング５〜７は電
気的に第２導電型領域４とは絶縁されているが、電圧印
加とは無関係に、その近傍に空乏層を有しており、高電
圧印加時において、ｐｎ接合より伸びた空乏層が、ガー
ドリング５〜７のもつ空乏層と繋がることよって、破線
矢印方向に伸び、ｐｎ接合の曲率半径の小さい部分１５
への電界の集中が緩和されて、耐圧が上昇する。またこ
の構造においては、ｐ層を選択拡散する工程で形成され
る熱酸化膜２が、拡散時のマスクの機能を果たすだけで
なく、素子として完成後もパシページョン膜として、シ
リコン表面を不純物、湿気等の外因より遮蔽する保護膜
の機能を果たす目的で存在している。2. Description of the Related Art In a planar semiconductor device, when a high voltage is applied, an electric field concentrates on a portion of the second conductivity type region having a small radius of curvature, causing breakdown. This can be made into a structure in which the depletion layer generated from the pn junction is extended in the lateral direction, so that the concentration of the electric field can be relaxed and the breakdown voltage can be increased. This structure is
This is called an n-junction termination structure. Conventionally, as a termination structure of this pn junction, as shown in FIG.
The structure in which the guard ring composed of the p-layer is formed in multiple layers as shown in FIG. This structure is obtained by simultaneously forming the guard rings 5 to 7 by diffusion in the step of selectively diffusing the p layer as the second conductivity type region 4 in the first conductivity type semiconductor substrate 1. The guard rings 5 to 7 are electrically insulated from the second-conductivity-type region 4, but have a depletion layer in the vicinity thereof regardless of the voltage application, and when a high voltage is applied, the depletion layer is closer to the pn junction. The extended depletion layer is connected to the depletion layer of the guard rings 5 to 7 so that the extended depletion layer extends in the direction of the broken arrow and has a small radius of curvature 15 of the pn junction.
The concentration of the electric field on the substrate is relieved, and the breakdown voltage increases. Further, in this structure, the thermal oxide film 2 formed in the step of selectively diffusing the p-layer not only functions as a mask at the time of diffusion, but also serves as a passivation film after the device is completed, and the silicon surface is treated as impurities and moisture. It exists for the purpose of functioning as a protective film that shields from external factors such as.
【０００３】[0003]
【発明が解決しようとする課題】この構造においては、
ガードリングの数が多い程、ｐｎ接合より伸びた空乏層
がガードリングのもつ空乏層と繋がることよって横方向
に伸び、したがって、ガードリングの数に比例して耐圧
が上昇するため、逆に、求める耐圧値に比例した数のガ
ードリングが必要となることが知られている。また、熱
酸化膜２を保護膜とするプレーナ型半導体素子の共通の
問題点としてよく知られていることであるが、シリコン
−酸化膜界面９での固定電荷や膜中のイオンが正電荷の
ため、表面の空乏層が広がりにくく、高電界強度になる
ため、高耐圧を阻止する要因となっている。以上二つの
要因により、例えばガードリングなしで８００Ｖの耐圧
がある場合、１５００Ｖ以上の耐圧をこの構造により求
めようとすれば、ガードリングの数を８本程度以上必要
とし、プレーナ型半導体素子の素子寸法がそれだけ大き
くなってしまい、コスト高となる。また、シリコンとの
界面が電気的に不安定である熱酸化膜２で覆われている
ため、シリコン−酸化膜界面９での固定電荷や膜中のイ
オンの影響で、プレーナ型半導体素子表面の電荷量が周
囲環境の変化により変動し、製造上の歩留まりの低下に
つながる。本発明の目的は、係る欠点を解消し、経済的
にして高耐圧のプレーナ型半導体素子を得ることにあ
る。In this structure,
As the number of guard rings increases, the depletion layer extending from the pn junction extends in the lateral direction by being connected to the depletion layer of the guard ring. Therefore, the breakdown voltage increases in proportion to the number of guard rings. It is known that the number of guard rings proportional to the required breakdown voltage value is required. Further, as is well known as a common problem of the planar type semiconductor device using the thermal oxide film 2 as a protective film, fixed charges at the silicon-oxide film interface 9 and ions in the film are positive charges. Therefore, the depletion layer on the surface is difficult to spread and the electric field strength is high, which is a factor to prevent high breakdown voltage. Due to the above two factors, for example, if there is a breakdown voltage of 800 V without a guard ring, and if a breakdown voltage of 1500 V or higher is to be obtained by this structure, the number of guard rings needs to be about 8 or more, and a planar semiconductor device element is required. The size becomes so large that the cost becomes high. Further, since the interface with silicon is covered with the electrically unstable thermal oxide film 2, the fixed charge at the silicon-oxide film interface 9 and the ions in the film affect the planar semiconductor device surface. The amount of charge fluctuates due to changes in the surrounding environment, leading to a reduction in manufacturing yield. An object of the present invention is to eliminate such drawbacks and to obtain a high withstand voltage planar semiconductor device economically.
【０００４】[0004]
【課題を解決するための手段】上記目的を達成するため
に、本発明は、第１導電型半導体基板表面の一部に第２
導電型領域が選択拡散により形成されたプレーナ型半導
体素子において、第２導電型領域端部を化学エッチング
または機械的加工により多数個の溝に分離し、この溝内
面に高誘電材よりなるパシページョン膜を形成するもの
である。また、製造方法として、上記多数個の溝を、フ
ッ酸硝酸混合系エッチング液を用いた化学エッチング、
またはダイシングカッターを用いた機械的加工により形
成し、この溝内面にデイップ法または塗布法により高誘
電材のパシページョン膜を形成するものである。In order to achieve the above-mentioned object, the present invention provides a second conductive film on a part of the surface of a first conductivity type semiconductor substrate.
In a planar semiconductor device in which a conductive type region is formed by selective diffusion, a second conductive type region end is divided into a number of grooves by chemical etching or mechanical processing, and a passivation film made of a high dielectric material is formed on the inner surface of the groove. Is formed. Further, as a manufacturing method, the above-mentioned many grooves are chemically etched using a hydrofluoric acid / nitric acid mixed etching solution,
Alternatively, it is formed by mechanical processing using a dicing cutter, and a passivation film of a high dielectric material is formed on the inner surface of the groove by a dip method or a coating method.
【０００５】[0005]
【作用】第２導電型領域（ｐ+層）の端部を、エッチン
グまたは機械加工による多数個の溝により分離すること
によって得られた多数個のｐ層のリングは、それぞれが
電気的に絶縁され、従来法におけるガードリングと構造
的に等しくなっているだけでなく、従来法のように拡散
によって別個に形成したものではなく、第２導電型領域
の端部を分離して得られたものであるため、拡散底部の
円弧の形状が連続しており、形状効果により、高電圧印
加時には、ｐｎ接合より延びる空乏層と、ガードリング
の持つ空乏層が繋がりやすくなる。さらに、溝の内面に
高誘電率材よりなるパシページョン膜を形成することに
より、シリコン表面での固定電荷や膜中のイオンをゲッ
タリング効果により負電荷に反転させることができる。
負電荷量が多くなるほど、空乏層がひろがりやすくなる
ため、前述の形状効果と相俟って、従来法による構造ほ
どガードリングの本数を増やさなくとも、空乏層を横方
向に延ばして、ｐｎ接合の曲率半径の小さい部分への電
界の集中を緩和させ、高耐圧化を図ることができる。A plurality of p-layer rings obtained by separating the ends of the second conductivity type region (p + layer) by a plurality of grooves formed by etching or machining are electrically insulated from each other. And is structurally equivalent to the guard ring in the conventional method, and is not separately formed by diffusion as in the conventional method, but is obtained by separating the end portion of the second conductivity type region. Therefore, the arc shape of the diffusion bottom is continuous, and due to the shape effect, the depletion layer extending from the pn junction and the depletion layer of the guard ring are easily connected to each other when a high voltage is applied. Furthermore, by forming a passivation film made of a high dielectric constant material on the inner surface of the groove, fixed charges on the silicon surface and ions in the film can be inverted into negative charges by the gettering effect.
As the negative charge amount increases, the depletion layer is more likely to expand. Therefore, in combination with the above-described shape effect, the depletion layer can be extended in the lateral direction even if the number of guard rings is not increased as in the conventional structure. It is possible to reduce the concentration of the electric field on the portion having a small radius of curvature, and to achieve a high breakdown voltage.
【０００６】[0006]
【実施例】図１に本発明に係わるプレーナ型半導体素子
の製造方法の一実施例の工程を示す。まず、図１（Ａ）
に示すような、第１導電型半導体基板１（ｎ-型）の表
面の一部に第２導電型領域４（ｐ+型）が選択拡散によ
り形成され、その上面が、前工程である熱拡散工程で形
成された熱酸化膜２で覆われた、プレーナ型半導体素子
の主構造を、従来の方法にて作成する。FIG. 1 shows steps of an embodiment of a method for manufacturing a planar semiconductor device according to the present invention. First, FIG. 1 (A)
, The second conductivity type region 4 (p + type) is formed by selective diffusion on a part of the surface of the first conductivity type semiconductor substrate 1 (n − type), and the upper surface of the second conductivity type region 4 (p + type) is formed in the previous process. The main structure of the planar type semiconductor device covered with the thermal oxide film 2 formed in the diffusion process is formed by a conventional method.
【０００７】次に、図１（Ｂ）に示すように、熱酸化膜
２にリソグラフィによりエッチング窓１１を形成し、例
えばフッ酸硝酸混合系のエッチング液１０をもちいて、
エッチングをおこなう。この際、図１（Ｃ）に示すよう
に、形成する溝１２は、第２導電型領域４を完全に分断
し第１導電型半導体基板１に到達する深さになるまでエ
ッチングする。この時、エッチングの終点をなんらかの
方法を用いて判定することは実工程上は困難であり、エ
ッチング液のレートが正確に再現されるよう、エッチン
グ液の液温を管理してやる必要がある。例えば、フッ
酸：硝酸：酢酸＝２：４：１混合液にて、１００μｍの
エッチングを行う場合は、２０℃一定で３００秒のエッ
チングを行う。Next, as shown in FIG. 1B, an etching window 11 is formed in the thermal oxide film 2 by lithography, and, for example, a hydrofluoric / nitric acid-mixed etching solution 10 is used,
Perform etching. At this time, as shown in FIG. 1C, the trench 12 to be formed is etched to a depth that completely divides the second conductivity type region 4 and reaches the first conductivity type semiconductor substrate 1. At this time, it is difficult to determine the end point of the etching using any method in the actual process, and it is necessary to control the temperature of the etching solution so that the rate of the etching solution is accurately reproduced. For example, in the case of etching 100 μm with a mixed solution of hydrofluoric acid: nitric acid: acetic acid = 2: 4: 1, etching is performed for 300 seconds at a constant temperature of 20 ° C.
【０００８】第２導電型領域４を分断する溝１２を形成
するその他の方法として、ダイシングカッターによる機
械的ダイシングをもちいてもよい。その際は、カッター
の歯の深さを制御すれば、比較的容易に所望の溝深さを
得ることができる。 ダイシング時に発生する加工歪を
エッチングにより除去する場合には、例えば、フッ酸：
硝酸：酢酸＝２：４：１混合液にて、１μｍ程度のエッ
チングを行えばよい。As another method of forming the groove 12 for dividing the second conductivity type region 4, mechanical dicing with a dicing cutter may be used. In that case, if the depth of the teeth of the cutter is controlled, the desired groove depth can be obtained relatively easily. When removing the processing strain generated during dicing by etching, for example, hydrofluoric acid:
Etching may be performed to about 1 μm with a mixed solution of nitric acid: acetic acid = 2: 4: 1.
【０００９】最後に図１（Ｄ）に示すように、溝１２の
内面にパッシベーション膜１３としてガラス膜を形成す
る。これは、従来技術であるグラシベーション法による
ガラス層の形成、または低温度処理によるＰＳＧ（リン
シリケートグラス）等の形成によりおこなう。Finally, as shown in FIG. 1D, a glass film is formed as a passivation film 13 on the inner surface of the groove 12. This is performed by forming a glass layer by a conventional glaciation method, or forming PSG (phosphosilicate glass) or the like by low temperature treatment.
【００１０】以上説明した方法により、図１（Ｄ）に示
すような、第１導電型半導体基板１（ｎ-型）表面の一
部に第２導電型領域４（ｐ+型）が選択拡散により形成
されたプレーナ型半導体素子において、第２導電型領域
４の端部に形成された溝１２により、多数個に分離され
るとともに、溝１２内面に高誘電材よりなるパシページ
ョン膜１３が形成された構造をもつプレーナ型半導体素
子を得る。By the method described above, the second conductivity type region 4 (p + type) is selectively diffused in a part of the surface of the first conductivity type semiconductor substrate 1 (n − type) as shown in FIG. 1D. In the planar type semiconductor device formed by the above method, the groove 12 formed at the end of the second conductivity type region 4 separates into a large number and the passivation film 13 made of a high dielectric material is formed on the inner surface of the groove 12. A planar semiconductor device having a different structure is obtained.
【発明の効果】本発明により、ｐｎ接合より延びる空乏
層と、ガードリングの持つ空乏層が繋がりやすくなるた
め、高電圧においても、ガードリングの本数を増やさな
くとも、空乏層を横方向に延ばして、ｐｎ接合の曲率半
径の小さい部分への電界の集中を緩和することができ、
よって、プレーナ型半導体素子の素子寸法を大きくする
ことなく高耐圧化が図ることができる。また、製造方法
として、シリコンとの界面が電気的に不安定な熱酸化膜
の代わりに、電気的に安定なパシページョン膜でシリコ
ン表面を覆うため、歩留まりよく、信頼性の高い素子を
得ることができる。According to the present invention, the depletion layer extending from the pn junction and the depletion layer of the guard ring are easily connected to each other, so that the depletion layer can be extended laterally even at a high voltage without increasing the number of guard rings. Thus, the concentration of the electric field on the portion of the pn junction having a small radius of curvature can be relaxed,
Therefore, it is possible to increase the breakdown voltage without increasing the element size of the planar semiconductor element. Further, as a manufacturing method, the silicon surface is covered with an electrically stable passivation film instead of the thermally-oxidized film whose interface with silicon is electrically unstable, so that a device with good yield and high reliability can be obtained. it can.
【図１】本発明のプレーナ素子構造の構造および製造方
法を示す断面図である。FIG. 1 is a cross-sectional view showing a structure and manufacturing method of a planar element structure of the present invention.
【図２】従来のガードリング構造の一例を示す図であ
る。FIG. 2 is a diagram showing an example of a conventional guard ring structure.
１ 第１導電型半導体基板 ２ 熱酸化膜 ４ 第２導電型領域 ５ ガードリング ９ シリコン−酸化膜界面 １０ エッチング液 １１ エッチング窓 １２ 溝 １３ パシページョン膜 1 1st conductivity type semiconductor substrate 2 Thermal oxide film 4 2nd conductivity type area 5 Guard ring 9 Silicon-oxide film interface 10 Etching liquid 11 Etching window 12 Groove 13 Passivation film
Claims (2)
電型領域が選択拡散により形成されたプレーナ型半導体
素子において、第２導電型領域端部が化学エッチングま
たは機械的加工により多数個の溝に分離され、この溝内
面に高誘電材よりなるパシページョン膜を形成したこと
を特徴とするプレーナ型半導体素子。1. A planar type semiconductor device in which a second conductivity type region is formed on a part of the surface of a first conductivity type semiconductor substrate by selective diffusion, and a large number of edges of the second conductivity type region are formed by chemical etching or mechanical processing. A planar type semiconductor device characterized in that a passivation film made of a high-dielectric material is formed on the inner surface of each groove.
チング液を用いた化学エッチング、またはダイシングカ
ッターを用いた機械的加工により、第２導電型領域端部
に多数個の溝を形成し、この溝内面にデイップ法または
塗布法により高誘電材のパシページョン膜を形成するこ
とを特徴とするプレーナ型半導体素子の製造方法。2. The method according to claim 1, wherein a plurality of grooves are formed at the end of the second conductivity type region by chemical etching using a hydrofluoric acid / nitric acid mixed etching solution or mechanical processing using a dicing cutter. A method of manufacturing a planar semiconductor device, comprising forming a passivation film of a high dielectric material on the inner surface of the groove by a dipping method or a coating method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6281503A JP3049703B2 (en) | 1994-10-21 | 1994-10-21 | Planar type semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6281503A JP3049703B2 (en) | 1994-10-21 | 1994-10-21 | Planar type semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08125009A true JPH08125009A (en) | 1996-05-17 |
| JP3049703B2 JP3049703B2 (en) | 2000-06-05 |
Family
ID=17640099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6281503A Expired - Lifetime JP3049703B2 (en) | 1994-10-21 | 1994-10-21 | Planar type semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3049703B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008047565A (en) * | 2006-08-10 | 2008-02-28 | Denso Corp | Diode |
-
1994
- 1994-10-21 JP JP6281503A patent/JP3049703B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008047565A (en) * | 2006-08-10 | 2008-02-28 | Denso Corp | Diode |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3049703B2 (en) | 2000-06-05 |
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