JPH08116492A - Solid-state image pickup device and video camera mounted with the same - Google Patents

Abstract

PURPOSE: To suppress flicker at a low cost without addition of an external circuit during electric iris operation. CONSTITUTION: The solid-state image pickup device having a CCD solid-state image pickup element 13 having an electronic shutter function is provided with a detection circuit 17 independently detecting an output signal of the CCD solid- state image pickup element 13 for each field within a flicker period, and a timing generating circuit 14 comparing a detection output for each field with a reference voltage set in common to a detection output of each field and generating a shutter pulse corresponding to the comparison result to control a shutter speed. Then each detection output is converged to a common object to control an output signal level of the CCD solid-state image pickup element 1 so as to be constant at all times for each exposure period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device,
In particular, it relates to a solid-state imaging device using a solid-state imaging device having an electronic shutter function.

[0002]

2. Description of the Related Art Some solid-state image pickup devices have a so-called electronic shutter function capable of controlling a storage time (exposure time) of signal charges in a sensor section. The basic principle is that the sensor unit accumulates electric charges only for a desired period immediately before reading out the signal charges (photoelectric charges) and sweeps out the signal charges before that to another place (for example, the substrate). . The timing chart is shown in FIG. The signal charge is read from the sensor unit to the vertical transfer register at a timing synchronized with the vertical synchronization signal VD, but at a certain time (exposure timing) traced back from the read timing, the signal charge previously accumulated in the sensor unit is, for example, a substrate. A shutter pulse is applied to the substrate to sweep it out. The period from the exposure timing to the read timing is the exposure period (exposure time).

FIG. 6 shows a conventional configuration of a video camera equipped with a solid-state image pickup device using a CCD solid-state image pickup device having this electronic shutter function. In the figure, the light from the subject is taken in by the lens 61, and the optical filter 6
After passing through 2, the light enters the image portion of the CCD solid-state image sensor 63. The CCD solid-state image sensor 63 is driven by the drive circuit 65 based on various timing signals including shutter pulses generated by the timing generation circuit 64. The CCD output signal of the CCD solid-state image pickup device 63 is derived as a video output through the signal processing circuit 66 and is also supplied to the detection circuit 67.

The detection circuit 67 temporally integrates the output signal of the CCD solid-state image pickup device 63 that has passed through the signal processing circuit 66 to obtain a detection voltage. This detected voltage is supplied to the timing generation circuit 64. The timing generation circuit 64 compares the detected voltage with a certain reference voltage, controls the timing of the shutter pulse according to the comparison result, and controls the exposure time of the CCD solid-state image sensor 63 via the drive circuit 65. Through this series of control, a constant CCD output signal determined by the reference voltage can always be obtained automatically. Hereinafter, this exposure control is called an electronic iris. The time constant of the detection circuit 67 is the CCD solid-state image sensor 63.
Is set to be sufficiently longer than the exposure cycle of.

FIG. 7 shows a conventional example of a timing generation circuit 64 for generating this shutter pulse. In FIG. 7, the detection voltage based on the CCD output signal becomes a comparison input of two comparators 71 and 72 having different reference voltages E1 and E2 (E1> E2). The comparison outputs of the comparators 71 and 72 are supplied to the decoder 73. The decoder 73 supplies the adder / subtractor 74 with data designating up / down / holding of the shutter speed based on the comparison outputs of the comparators 71 and 72.
The adder / subtractor 74 steps up, down or holds the shutter speed data by one step according to the data from the decoder 73. This shutter speed data is
It is loaded into a flip-flop (FF) 75. The final stage shutter pulse generation circuit 76 generates a shutter pulse at a timing corresponding to the shutter speed data held in the flip-flop 75.

Next, the timing generation circuit 64 having the above configuration
The circuit operation of will be described. CCD solid-state image sensor 63
The detection voltage obtained by temporally integrating the output signal of is compared with the two reference voltages E1 and E2 by the comparators 71 and 72. The decoder 73 receiving this comparison result holds the shutter speed when the detected voltage is between the two reference voltages E1 and E2, up when the detected voltage is higher than the upper reference voltage E1, and higher than the lower reference voltage E2. When it is low, it outputs to the adder / subtractor 74 data that causes it to go down.

The adder / subtractor 74 adjusts the current shutter speed data according to the data received from the decoder 73.
The calculation of 0 / + 1 / -1 is performed. The new shutter speed data updated by this calculation is latched by the flip-flop 75. Shutter pulse generation circuit 76
Controls the exposure time of the CCD solid-state image sensor 63 by generating a shutter pulse according to the shutter speed data. This series of operations is normally performed every certain period, and is continued step by step until the detected voltage falls between the two reference voltages E1 and E2.

[0008]

In the conventional solid-state image pickup device described above, there is no problem in the case of image pickup under a light source in which the brightness does not constantly change. 1 in the case of imaging under a light source that has characteristics and is not synchronized with the exposure cycle of the CCD solid-state imaging device
Taking a combination of a fluorescent lamp that emits light at 00 Hz and a CCD solid-state image sensor that performs exposure operation at 60 Hz as an example, FIG.
The flicker as shown in will occur. That is, since the light emission period of the fluorescent lamp is 10 ms and one period of the exposure operation of 60 Hz is 16.7 ms, the least common multiple of these is 50 ms, and as shown in FIG.
The relationship between the two is restored by the exposure operation once. Therefore, there are three types of exposure periods, and CC
The difference in the output signal level of the D solid-state image sensor is
This is a cause of flicker of Hz. This flicker becomes more noticeable as the shutter speed increases,
The flickering on the screen significantly deteriorates the image quality.

In the case of a combination of a 100 Hz fluorescent lamp and a CCD solid-state image pickup device (NTSC / EIA) that performs an exposure operation of 60 Hz, it is a well-known fact that an electronic shutter of 1/100 second is effective in suppressing flicker. is there. However, in this case, the exposure control using the electronic shutter becomes impossible. Further, in order to suppress flicker, a photodetector that detects ambient external light is provided, and the shutter speed is corrected according to the amount of external light accumulated to control the photocharge accumulation time in field units. A solid-state imaging device has been proposed (see Japanese Patent Laid-Open No. 2-186883).

However, in the solid-state image pickup device having such a structure, a dedicated photodetector for detecting external light must be provided, and a circuit for signal processing thereof is also required, which complicates the structure. At the same time, there was a problem that the cost increased. Furthermore, when the characteristics of the photodetector and the solid-state image sensor vary, for example, when the photodetector with extremely low sensitivity and the solid-state image sensor with high sensitivity are combined, or vice versa. , The results obtained will be completely different.

The present invention has been made in view of the above problems, and an object of the present invention is to realize a solid state which can suppress flicker at low cost without adding an external circuit while performing an electronic iris operation. An object is to provide an imaging device.

[0012]

A solid-state image pickup device according to the present invention comprises a solid-state image pickup device having an electronic shutter function, and detection means for independently detecting an output signal of the solid-state image pickup device for each field within a flicker period. Comparison means for comparing the detection output of the detection means corresponding to each field with a reference voltage commonly set for the detection output for each field, and the signal level of the video output according to the comparison result of the comparison means. And a control means for controlling.

[0013]

In the solid-state image pickup device having the above structure, the detection means has the number of detection stages corresponding to the flicker period, for example, so that the output signal of the solid-state image pickup device is independently detected for each field within the flicker period. Upon receiving the detection output for each field, the comparison means compares each detection output with a common reference voltage. Then, the control means controls, for example, the shutter speed or the gain of the variable gain amplifier according to the comparison result. By this control, each detection output converges on a common target value. as a result,
The output signal level of the solid-state image sensor is always constant during each exposure period. Therefore, flicker can be suppressed.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. In FIG. 1, the light from the subject is the lens 11
Captured by the optical filter 12 and then passed through the CC
The light enters the image portion of the D solid-state image sensor 13. This CC
The D solid-state image pickup device 13 is driven by the drive circuit 15 based on various timing signals generated by the timing generation circuit 14. FIG. 2 shows an example of the configuration of, for example, an interline transfer type CCD solid-state imaging device 13.

In FIG. 2, a plurality of sensor units 21 are arranged in a matrix in a row direction (vertical direction) and a column direction (horizontal direction) to store signal charges according to the amount of incident light,
An image pickup area (image portion) 23 is configured by a plurality of vertical transfer registers 22 which are arranged in each vertical column of the sensor portions 21 and vertically transfer the signal charges read from each sensor portion 21. In the image pickup area 23, the sensor section 21 is composed of, for example, a PN junction photodiode, and the vertical transfer register 22 is composed of a CCD.

The signal charges accumulated in the sensor section 21 are read out to the vertical transfer register 22 by applying a read pulse XSG to a read gate (not shown). The vertical transfer register 22 is transfer-driven by, for example, four-phase vertical transfer clocks φV1 to φV4. The signal charges read out to the vertical transfer register 22 are sequentially transferred in the vertical direction for each part corresponding to one scanning line in a part of the horizontal blanking period. A horizontal transfer register 24 composed of a CCD to which signal charges corresponding to one scanning line are sequentially transferred from a plurality of vertical transfer registers 22 is arranged below the imaging region 23 in the drawing.

The horizontal transfer register 24 is transfer-driven by two-phase horizontal transfer clocks φH1 and φH2.
Thereby, the signal charges for one line are sequentially transferred in the horizontal direction in the horizontal scanning period after the horizontal blanking period. At the end of the horizontal transfer register 24, for example, a charge detection unit 25 having a floating diffusion configuration is arranged, and the horizontally transferred signal charge is generated by the charge detection unit 2.
In step 5, the voltage signals are sequentially converted. Then, this voltage signal is amplified by the output amplifier 26 and then derived as a CCD output signal according to the incident amount of light from the subject.

This CCD solid-state image pickup device 13 applies a shutter pulse XSUB to the substrate and sweeps out the signal charges accumulated in each sensor unit 21 to the substrate, thereby accumulating the signal charges in the sensor unit 21 (exposure time). It has an electronic shutter function to control the time). That is, in normal operation, by biasing the substrate with a constant set voltage (substrate voltage), signal charges are accumulated in the sensor unit 21, while in the electronic shutter, the shutter pulse XSUB is added to the substrate voltage. Is added, the barrier on the substrate side is destroyed, and the signal charges accumulated in the sensor section 21 are swept out to the substrate.

Various timing signals including the above-described read pulse XSG, four-phase vertical transfer clocks φV1 to φV4, two-phase horizontal transfer clocks φH1 and φH2, and shutter pulse XSUB are generated by the timing generation circuit 14 of FIG.
Generated in CCD of CCD solid-state image sensor 13
The magnitude of the output signal changes depending on the intensity of the incident light, and is subjected to signal processing such as correlated double sampling (CDS) in the signal processing circuit 16 and then derived as a video output. It is supplied to the detection circuit 17.

The detection circuit 17 detects the magnitude of the CCD output signal of the CCD solid-state image pickup device 13 that has passed through the signal processing circuit 16 and temporally integrates it to obtain a detection voltage. It has wave stages 17a to 17c. The detection stages 17a to 17c of the three systems have, for example, a resistor R commonly provided in each stage, and a resistor R having the same capacitance value connected between the output end of the resistor R and the ground (GND).
It has an integrator circuit configuration including individual capacitors C1, C2, and C3. In addition, three stages of detection stages 17a to 17c
The changeover switches 18 and 19 for selecting which one are selected are inserted on the input and output sides of the capacitors C1, C2 and C3. These changeover switches 18 and 19 are used to change over pulses FLD1 / F generated by the timing generation circuit 14.
The detection stage to be selected is switched by LD2 / FLD3 every exposure period.

Now, the reason why the detection circuit 17 is provided with the three detection stages 17a to 17c will be described.
Taking a combination of a fluorescent lamp that emits light at 100 Hz and a CCD solid-state image sensor that performs exposure operation at 60 Hz as an example, as described above, there are three types of exposure periods, and among these, the CCD solid-state image sensor Since different levels of the CCD output signals cause the flicker, it is possible to suppress the flicker by making the levels of the CCD output signals uniform during the three types of exposure periods. Therefore, three detection stages 17a to 17c corresponding to these three types of exposure periods are provided.
This constitutes the detection circuit 17.

The three types of detection voltages output from the detection circuit 17 for each exposure period are supplied to the timing generation circuit 14. The timing generation circuit 14 independently compares these three types of detection voltages with a reference voltage that is commonly set for each detection voltage, and when the detection voltage is higher, the shutter speed becomes faster. On the contrary, when the detected voltage is lower, the timing control of the shutter pulse XSUB is performed so that the shutter speed becomes slower, and the exposure time of the CCD solid-state image sensor 13 is controlled via the drive circuit 15. Through this series of control, a constant CCD output signal determined by a common reference voltage is always obtained automatically.

FIG. 3 shows an example of the circuit configuration of only the portion for generating the shutter pulse XSUB in the timing generation circuit 14. In FIG. 3, the three types of detection voltages based on the CCD output signals are independently set to different reference voltages E1 and E2 which are commonly set for the three types of detection voltages.
Two comparators 31, 32 having (E1> E2)
It becomes the comparison input of. The respective comparison outputs of the comparators 31 and 32 are supplied to the delay circuits 33 and 34. Delay circuit 33,
Reference numeral 34 is composed of a flip-flop which uses the vertical synchronizing signal VD as a latch pulse, and latches each comparison output in synchronization with the vertical synchronizing signal VD to delay it by one field equivalent period. The decoder 35 includes delay circuits 33 and 3
Increase the shutter speed based on each delay output of 4 /
Adder / subtractor 36 for data specifying down / hold
Give to.

The adder / subtractor 36 steps up, down or holds the shutter speed data by one step according to the data from the decoder 35. This shutter speed data is loaded into the flip-flop (FF) 37. The data latched by the flip-flop 37 is directly supplied to the shutter pulse generation circuit 39, and is delayed by a delay circuit 38 composed of, for example, two stages of flip-flops by a period corresponding to two fields and then added to the adder / subtractor 36. Will be returned. The shutter pulse generation circuit 39 generates a shutter pulse XSUB at a timing corresponding to the shutter speed data latched by the flip-flop 37.

Next, regarding the circuit operation according to the first embodiment having the above-mentioned structure, the fluorescent lamp emitting light at 100 Hz and 60
A combination of CCD solid-state image pickup devices that perform exposure operation at Hz will be described as an example with reference to the timing chart of FIG. As is clear from FIG. 4, since the light emission cycle of the fluorescent lamp and the exposure cycle of the CCD solid-state image pickup device 13 are not synchronized, C of the CCD solid-state image pickup device 13 is exposed in the exposure periods A, B, and C.
CD output signal (CCD output signal before flickerless control)
Is the same as in the case of the prior art. On the other hand, in the first embodiment, three detection stages 17a to 17c are provided as the detection circuit 17, and the three detection stages 1 are provided.
7a to 17c are switched every exposure period.

That is, in response to the switching pulses FLD1 / FLD2 / FLD3 generated from the timing generation circuit 14 corresponding to each of the exposure periods A, B and C, the switching switches 18 and 19 are three stages of detection stages 17a to. 17c
By selecting either of the above, for example, the detection voltage of the exposure period A is always detected from the detection stage 17a, and the detection voltage of the exposure period B is similarly detected from the detection stage 17b.
From, the detection voltage of the exposure period C is obtained. These three types of detection voltages are supplied to the timing generation circuit 14.

In FIG. 3, the three types of detected voltages are independently compared with the two reference voltages E1 and E2 set in common for the detected voltages by the comparators 31 and 32, respectively. The respective comparison outputs of the comparators 31, 32 are supplied to the decoder 35 after being delayed by the delay circuits 33, 34 for a period corresponding to one field. The decoder 35 uses two reference voltages E for each detection voltage for three types of detection voltages.
The shutter speed is held when it is between 1 and E2, is up when it is higher than the upper reference voltage E1, and is down when it is lower than the lower reference voltage E2 to the adder / subtractor 36. Output.

The adder / subtractor 36 includes a flip-flop 3
7 and the data delayed by the delay circuit 38 for a period corresponding to 3 fields, that is, when the shutter speed is controlled based on the detection voltage in the exposure period A, the shutter speed data in the previous exposure period A is received from the decoder 35. The calculation of ± 0 / + 1 / -1 is performed according to the data. The new shutter speed data updated by this calculation is latched by the flip-flop 37. The shutter pulse generation circuit 39 generates a shutter pulse having a pulse width according to the shutter speed data latched by the flip-flop 37.

Here, the comparison outputs of the comparators 31 and 32 are delayed by the delay circuits 33 and 34 for a period corresponding to one field, and the shutter speed data based on the comparison output is latched by the flip-flop 37 for a period corresponding to one field. Since the total is delayed by a period corresponding to two fields, for example, the flickerless control based on the detection voltage in the exposure period A is performed on the shutter pulse in the next exposure period A, and the flickerless control based on the detection voltage in the exposure period B is also performed. Is the shutter pulse for the next exposure period B,
The flickerless control based on the detection voltage in the exposure period C is reflected in the shutter pulse in the next exposure period C, respectively.

As described above, the three detection stages 17a to 17c are provided as the detection circuit 17, and the three detection stages 17a to 17c are switched every exposure period.
From each of the detection stages 17a to 17c, three types of detection voltages corresponding to each of the three types of exposure periods A, B and C are always obtained. Then, these three types of detection voltages are independently compared with common reference voltages E1 and E2, respectively, and exposure periods A, B, and
By independently controlling the shutter speed corresponding to each of C, all three types of detection voltages can be converged to a common target value. As a result, the CCD output signal after flicker-less control is always constant during the three types of exposure periods A, B, and C, so that flicker can be suppressed.

By the way, in the above embodiment, the CCD
The case where the invention is applied to an electronic iris system that controls the timing of an electronic shutter speed based on the detection voltage of an output signal has been described. A system that controls the gain of an AGC amplifier, which is a variable gain amplifier, based on the detection voltage of a CCD output signal. In the case of, as in the case of the electronic iris system, the problem of flicker occurs. The problem of flicker will be described below.

FIG. 10 shows a conventional example of a video camera equipped with a CCD solid-state image pickup device of this system configuration. 6, those parts that are the same as those corresponding parts in FIG. 6 are designated by the same reference numerals, and a duplicate description thereof will be omitted. In FIG. 10, the CCD output signal of the CCD solid-state image pickup device 63 is subjected to signal processing such as amplification processing by the AGC amplifier 68 in the signal processing circuit 66, then derived as a video output, and supplied to the detection circuit 67. . Detection circuit 67
Obtains a detection voltage by temporally integrating the output signal of the AGC amplifier 68. This detected voltage is supplied to the control voltage generation circuit 69.

The control voltage generating circuit 69 compares the detected voltage with a predetermined reference voltage, and when the detected voltage is higher, the gain of the AGC amplifier 68 becomes lower. Conversely, when the detected voltage is lower, The gain control is performed so that the gain of the AGC amplifier 68 becomes high. By this series of control, it is possible to always automatically obtain the output signal of the constant level automatically determined by the reference voltage as the output signal of the AGC amplifier 68. The time constant of the detection circuit 67 is C
It is set to be sufficiently longer than the exposure cycle of the CD solid-state image sensor 63.

In this system configuration, although there is no problem in imaging under a light source in which the brightness does not constantly change, it has a periodic light emission characteristic like a fluorescent lamp and is synchronized with the exposure cycle of the CCD solid-state image sensor 63. Under the light source which is not
Flicker occurs as shown in. Where 100Hz
Fluorescent lamp that emits light at C and exposure operation at 60 Hz
The combination of the CD solid-state image sensor is taken as an example, and the time constant of the detection circuit 67 is set to be sufficiently long.
The gain of the amplifier 68 is constant in every exposure period, whereas the actual CCD output signal of the CCD solid-state image pickup device 63 is different for each exposure period, so that flicker occurs.

In the case of a combination of a 100 Hz fluorescent lamp and a CCD solid state image pickup device (NTSC / EIA) that performs an exposure operation of 60 Hz, as described above, an electronic shutter of 1/100 second is effective for flicker suppression. Is a well-known fact. However, in this case, it becomes impossible to select the electronic shutter speed, and there is a problem that the exposure control (electronic iris) using the electronic shutter cannot be performed, for example.

FIG. 12 is a block diagram showing a second embodiment of the present invention made to solve such a problem. In the figure, the same parts as those in FIG. Since it overlaps, it will be omitted. In FIG. 12, C
The CCD output signal of the CD solid-state image pickup device 13 is subjected to signal processing such as amplification processing by the AGC amplifier 41 in the signal processing circuit 16 and then derived as a video output and supplied to the detection circuit 17.

The detection circuit 17 is for detecting the magnitude of the output signal of the AGC amplifier 41 and temporally integrating it to obtain a detection voltage. For example, as in the case of the first embodiment, there are three systems, for example. Detection stages 17a to 17c. This 3
The detection stages 17a to 17c of the system are, for example, an integration including a resistor R commonly provided in each stage and three capacitors C1, C2 and C3 connected between the output end of the resistor R and the ground. It has a circuit configuration. Further, changeover switches 18 and 19 for selecting one of the three detection stages 17a to 17c are inserted on the input and output sides of the capacitors C1, C2 and C3.

The changeover switches 18 and 19 are changeover pulses FL generated from the timing generation circuit 14.
1 detection stage is selected by D1 / FLD2 / FLD3
Switch every exposure period. Three types of detection voltages output from the detection circuit 17 for each exposure period are supplied to the control voltage generation circuit 42. The control voltage generation circuit 42 has a circuit configuration including a comparator 43, and compares the three types of detection voltages with a reference voltage E0 that is set in common for each detection voltage, and A
The gain control of the GC amplifier 41 is performed.

Next, regarding the circuit operation according to the second embodiment having the above-mentioned structure, as in the case of the first embodiment, 100H
A combination of a fluorescent lamp that emits light at z and a CCD solid-state image sensor that performs an exposure operation at 60 Hz will be described as an example with reference to the timing chart of FIG. As is clear from FIG. 13, since the light emission cycle of the fluorescent lamp and the exposure cycle of the CCD solid-state image sensor 13 are not synchronized, the exposure period A,
The CCD output signal of the CCD solid-state image pickup device 13 (CCD output signal before flickerless control) differs between B and C, as in the case of the prior art. On the other hand, in the second embodiment, the detection circuit 17 includes three detection stages 17a to 17a.
7c is provided, and the detection stages 17a to 17c of these three systems are switched every one exposure period.

That is, in response to the changeover pulses FLD1 / FLD2 / FLD3 generated from the timing generation circuit 14 corresponding to each of the exposure periods A, B, and C, the changeover switches 18 and 19 have three detection stages 17a to. 17c
By selecting either of the above, for example, the detection voltage of the exposure period A is always detected from the detection stage 17a, and the detection voltage of the exposure period B is similarly detected from the detection stage 17b.
From, the detection voltage of the exposure period C is obtained. These three types of detection voltages are supplied to the control voltage generation circuit 42.

In the control voltage generation circuit 42,
The three types of detection voltages are independently compared with the reference voltage E0 common to each detection voltage by the comparator 43. This comparator 43 supplies the comparison output to the AGC amplifier 41 as a gain control voltage, and when the detected voltage is higher than the reference voltage E0, the gain of the AGC amplifier 41 becomes low, so that the detected voltage is oppositely detected. If is lower than AG, the gain of the AGC amplifier 41 is increased so that
The gain control of the C amplifier 41 is performed.

As described above, the three detection stages 17a to 17c are provided as the detection circuit 17, and the three detection stages 17a to 17c are switched every exposure period.
From each of the detection stages 17a to 17c, three types of detection voltages corresponding to each of the three types of exposure periods A, B and C are always obtained. Then, these three types of detection voltages are independently compared with the common reference voltage E0, and the gain control of the AGC amplifier 41 is independently performed corresponding to each of the exposure periods A, B, and C, so that three types of detection voltages are obtained. All the detected voltages can be converged to a common target value. As a result, the CCD output signal after flicker-less control is always constant during the three types of exposure periods A, B, and C, so that flicker can be suppressed.

In each of the above embodiments, the fluorescent lamp emitting light at 100 Hz and the CCD operating at 60 Hz are operated.
Three detection stages 17a to a combination of solid-state image pickup elements
Although the case where the detection circuit 17 is configured by 17c has been described, the number is not limited to this, and the number of detection stages is determined according to the flicker cycle, and it is not always necessary to provide a plurality of detection stages. For example, it is also possible to adopt a configuration in which the integration time constant is shortened in one detection stage, or reset and switched for each exposure period.

[0045]

As described above, according to the present invention,
In a solid-state image pickup device having a solid-state image pickup device having an electronic shutter function, the output signal of the solid-state image pickup device is detected independently for each field within the flicker cycle, and the detection output corresponding to each field is compared with a common reference voltage. However, by adopting a configuration in which the signal level of the video output is controlled according to the comparison result, each detection output converges on a common target value, and the output signal level of the solid-state image sensor is always constant during each exposure period. Therefore, even under a light source that has a periodic light emission characteristic and is not synchronized with the exposure cycle of the solid-state image sensor, the light source frequency can be obtained at low cost without adding an external circuit while performing the electronic iris operation. It will be possible to suppress flicker.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing an example of an interline transfer type CCD solid-state imaging device.

FIG. 3 is a block diagram showing an example of a configuration of a timing generation circuit according to the present invention.

FIG. 4 is a timing chart for explaining a circuit operation according to the first embodiment.

FIG. 5 is a timing chart for explaining the operation of the electronic shutter.

FIG. 6 is a configuration diagram showing a conventional example.

FIG. 7 is a block diagram showing a timing generation circuit according to a conventional example.

FIG. 8 is a timing chart for explaining a circuit operation according to a conventional example.

FIG. 9 is a timing chart showing the relationship between the light emission period of the light source and the exposure operation of the CCD solid-state imaging device.

FIG. 10 is a configuration diagram showing another conventional example.

FIG. 11 is a timing chart for explaining a circuit operation according to another conventional example.

FIG. 12 is a configuration diagram showing a second embodiment of the present invention.

FIG. 13 is a timing chart for explaining a circuit operation according to the second embodiment.

[Explanation of symbols]

 13 CCD solid-state image sensor 14 Timing generation circuit 16 Signal processing circuit 17 Detection circuit 17a, 17b, 17c Detection stage 18, 19 Changeover switch 21 Sensor part 22 Vertical transfer register 24 Horizontal transfer register 31, 32, 43 Comparator 33, 34, 38 Delay circuit 35 Decoder 36 Adder / subtractor 39 Shutter pulse generation circuit 41 AGC amplifier 42 Control voltage generation circuit

Claims (5)

[Claims] 1. A solid-state imaging device having an electronic shutter function, a detection means for independently detecting an output signal of the solid-state imaging device for each field within a flicker cycle, and a detection means for detecting the detection signal corresponding to each field. Comparing means for comparing the output with a reference voltage commonly set for the detection output for each field, and control means for controlling the signal level of the video output according to the comparison result of the comparing means. A characteristic solid-state imaging device. 2. The solid-state imaging device according to claim 1, wherein the control unit controls the shutter speed according to a comparison result of the comparison unit. 3. A variable gain amplifier for amplifying an output signal of the solid-state image pickup device, wherein the control means controls the gain of the variable gain amplifier according to a comparison result of the comparison means. The solid-state imaging device according to claim 1. 4. The solid-state imaging device according to claim 1, wherein the detection unit has a plurality of detection stages determined by a flicker cycle and switches the plurality of detection stages for each exposure period. 5. The solid-state imaging device according to claim 1, 2, 3 or 4, and an optical system for guiding incident light to an imaging region of a solid-state imaging device in the solid-state imaging device. Video camera.