JPH08115919A - Method of processing semiconductor substrate - Google Patents

Method of processing semiconductor substrate

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Publication number
JPH08115919A
JPH08115919A JP25212594A JP25212594A JPH08115919A JP H08115919 A JPH08115919 A JP H08115919A JP 25212594 A JP25212594 A JP 25212594A JP 25212594 A JP25212594 A JP 25212594A JP H08115919 A JPH08115919 A JP H08115919A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
heat treatment
pulling
atmosphere
speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25212594A
Other languages
Japanese (ja)
Inventor
Tsutomu Amai
勉 天井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP25212594A priority Critical patent/JPH08115919A/en
Publication of JPH08115919A publication Critical patent/JPH08115919A/en
Pending legal-status Critical Current

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  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

PURPOSE: To improve electric property such as the breakdown strength of an oxide film made on a semiconductor substrate, and growing single-crystal silicon at a specified pull-up speed and slicing it, using CZ method or MCZ method, so as to form a semiconductor substrate, and performing heat treatment under specified conditions in reductive or inert atmosphere. CONSTITUTION: Single-crystal silicon is grown at a pull-up speed of 1.3mm/min. or over using either CZ method or MCZ method, and it is sliced into semiconductor substrates. The semiconductor substrates are heat-treated for 30 min. or more at a temperature of 1100 deg.C or over in either reductive or inert atmosphere. Single-crystal silicon of 150mmϕ, n-type, and about 15×10<17> atoms/cm<3> in concentration of interlattice oxygen is pulled up at a speed of 1.3mm/min, to provide substrates. Moreover, the atmosphere shall be mixed gas among H2 , He, Ne, Ar, Kr, and Xe, or inert atmosphere by any one among Ne, Ar, Kr, and Xe.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体基板の処理方法に
関し、特に結晶性等のすぐれたシリコンDZ(Denuded
Zone)ウェハの製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for processing a semiconductor substrate, and particularly to a silicon DZ (Denuded) having excellent crystallinity.
Zone) wafer manufacturing method.

【0002】[0002]

【従来の技術】従来、半導体基板の電気的特性、特にシ
リコン半導体基板に形成した酸化膜の酸化膜耐圧特性及
びTDDB(Time Dependent Dielectric Breakdown)特
性などに関連する半導体基板の電気的特性の向上を図る
方法として主に以下の2つの方法が知られている。
2. Description of the Related Art Conventionally, it is necessary to improve the electrical characteristics of a semiconductor substrate, particularly the electrical characteristics of a semiconductor substrate related to the oxide film breakdown voltage characteristics of an oxide film formed on a silicon semiconductor substrate and TDDB (Time Dependent Dielectric Breakdown) characteristics. The following two methods are mainly known as methods for achieving this.

【0003】(1) 1つ目の方法は、チョクラルスキー引
上げ法(CZ法)等のシリコン単結晶の育成において、
通常の引上速度(1.0mm/min程度)よりも低速
(0.4mm/min程度)で引き上げた単結晶から形
成した半導体基板を用いる方法である。
(1) The first method is to grow a silicon single crystal such as Czochralski pulling method (CZ method).
This is a method of using a semiconductor substrate formed from a single crystal pulled at a lower speed (about 0.4 mm / min) than a normal pulling speed (about 1.0 mm / min).

【0004】(2) 2つ目の方法は、通常の引上速度によ
る単結晶から形成されたシリコン半導体基板を不活性ガ
ス又は還元性ガス中で高温(1100〜1250℃程
度)熱処理する方法である。
(2) The second method is a method of heat-treating a silicon semiconductor substrate formed of a single crystal at a normal pulling rate at a high temperature (about 1100 to 1250 ° C.) in an inert gas or a reducing gas. is there.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、この2
つの従来の方法には、以下の様な問題点がある。すなわ
ち、 (1) 1つ目の方法においては、低速引上げにより、結晶
の生産能力が著しく低下(通常引上げ結晶の場合の50
%程度にまで低下)してしまい、この結晶から作製する
半導体基板のコストが通常の半導体基板に比べて増加し
てしまうという問題点があった。
[Problems to be Solved by the Invention]
The two conventional methods have the following problems. That is, (1) In the first method, the crystal pulling capacity is remarkably reduced by the slow pulling (50% in the case of the normal pulling crystal).
%), And the cost of the semiconductor substrate manufactured from this crystal increases as compared with a normal semiconductor substrate.

【0006】(2) また、2つ目の方法においては、通常
の方法で作製された半導体基板に不活性ガス又は還元性
ガス中での高温熱処理を施すという工程を追加すること
になるために、基板のコストが増加(通常半導体基板の
1.3〜1.5倍程度にコスト増加)してしまうという
問題点があった。さらに、半導体基板の結晶学的特性
や、その上に形成した酸化膜によるMOSダイオード等
の電気的特性は完全なものでなく、まだ改善の余地があ
るという問題点があった。たとえば酸化膜耐圧特性は図
4に示すように従来品では良品率が悪いという問題があ
った。この傾向は酸化膜厚toxが厚くなるほど顕著で、
図4はtox=25nmの場合であるが、tox=55nm
では90%以下になってしまうという問題があった。
(2) Further, in the second method, a step of subjecting a semiconductor substrate manufactured by a usual method to a high temperature heat treatment in an inert gas or a reducing gas is added. However, there is a problem in that the cost of the substrate increases (usually the cost increases by about 1.3 to 1.5 times that of the semiconductor substrate). Furthermore, the crystallographic characteristics of the semiconductor substrate and the electrical characteristics of the MOS diode and the like due to the oxide film formed thereon are not perfect and there is a problem that there is still room for improvement. For example, as shown in FIG. 4, the oxide film withstand voltage characteristic has a problem that the conventional product has a poor yield rate. This tendency becomes more remarkable as the oxide film thickness tox increases,
FIG. 4 shows the case of tox = 25 nm, but tox = 55 nm.
Then, there was a problem that it would be 90% or less.

【0007】上記問題点を鑑み、本発明は、半導体基板
上に形成した酸化膜耐圧等の電気的特性を従来技術にお
ける場合以上に向上させることが可能な半導体基板を、
従来技術におけるよりも低コストで提供することを目的
とする。
In view of the above problems, the present invention provides a semiconductor substrate capable of improving electrical characteristics such as breakdown voltage of an oxide film formed on the semiconductor substrate more than in the prior art.
It aims at providing at a lower cost than in the prior art.

【0008】[0008]

【課題を解決するための手段】上記問題点を解決するた
めに、本発明はCZ法又は磁場応用チョクラルスキー引
上げ法(Magnetic-Field-Applied Czochralski Method
:以下、MCZ法という)を用い、1.3mm/mi
n以上の引上げ速度で、シリコン単結晶を成長し、この
単結晶をスライスして半導体基板(半導体ウェハ)を形
成し、この半導体基板を還元性あるいは不活性雰囲気の
いずれかの雰囲気中で、1100℃以上の温度において
30分以上熱処理を行う半導体基板の熱処理方法である
ことを特徴とする。
In order to solve the above problems, the present invention provides a CZ method or a magnetic-field-applied Czochralski method.
: Hereinafter, referred to as MCZ method), 1.3 mm / mi
A silicon single crystal is grown at a pulling rate of n or more, and the single crystal is sliced to form a semiconductor substrate (semiconductor wafer), and the semiconductor substrate is subjected to 1100 in either a reducing atmosphere or an inert atmosphere. The method is a method for heat treating a semiconductor substrate, in which heat treatment is performed for 30 minutes or more at a temperature of ℃ or more.

【0009】好ましくは、図1に示すように、析出物等
の直径に対して、析出物等の密度分布をプロットする場
合において、析出物等の直径を1nm単位で区分し、す
なわち横軸を1nm単位で見た場合、30nm(臨界直
径)以上の直径の各区分における析出物等の密度が2×
105 個/cm3 以下の半導体基板を選定して、その
後、この選定された特定の半導体基板についてのみ、熱
処理を行うことを特徴とする。すなわち直径30〜31
nmの析出物等、直径31〜32nmの析出物等、直径
32〜33nmの析出物等、……のそれぞれの密度が2
×105 個/cm3 以下の半導体基板を選定するのであ
る。
Preferably, as shown in FIG. 1, when plotting the density distribution of a precipitate or the like against the diameter of the precipitate or the like, the diameter of the precipitate or the like is divided in units of 1 nm, that is, the horizontal axis represents When viewed in units of 1 nm, the density of precipitates in each section having a diameter of 30 nm (critical diameter) or more is 2 ×
It is characterized in that a semiconductor substrate of 10 5 pieces / cm 3 or less is selected, and then heat treatment is performed only on the selected specific semiconductor substrate. That is, diameter 30 to 31
nm, etc., such as those having a diameter of 31 to 32 nm, those having a diameter of 32 to 33 nm, etc.
A semiconductor substrate of x10 5 / cm 3 or less is selected.

【0010】さらに好ましくは、還元性雰囲気はほぼ1
00%のH2 、あるいはH2 とHe,Ne,Ar,K
r,Xeのうち少なくとも一つとの混合ガスであり、ま
たは不活性雰囲気はHe,Ne,Ar,Kr,Xeのう
ちの一つの単独ガスか、これらの少なくとも2つ以上か
らなる混合ガスであることである。
More preferably, the reducing atmosphere is about 1.
00% H 2 , or H 2 and He, Ne, Ar, K
It is a mixed gas with at least one of r and Xe, or the inert atmosphere is one of He, Ne, Ar, Kr, and Xe alone, or a mixed gas including at least two of these. Is.

【0011】[0011]

【作用】本発明の特徴によれば、従来技術よりも高速度
で単結晶を引き上げ、短時間で成長することにより、光
熱費や人件費等のコストを低下させることができる。ま
た引き上げた単結晶(インゴット)中の析出物等の直径
が所定のサイズ(臨界直径)以下の密度が高いような密
度分布とすることができる。この所定のサイズ以下の析
出物等の密度が高い密度分布を有した半導体基板を選定
して熱処理することにより、効率よく半導体基板中の散
乱体密度が減少し、結晶性が向上する。
According to the features of the present invention, by pulling a single crystal at a higher speed than in the prior art and growing it in a short time, it is possible to reduce costs such as light heat and labor costs. Further, the density distribution can be such that the diameter of the precipitate or the like in the pulled single crystal (ingot) is high with a predetermined size (critical diameter) or less. By selecting and heat-treating a semiconductor substrate having a high density distribution of precipitates or the like having a predetermined size or less, the scatterer density in the semiconductor substrate is efficiently reduced, and the crystallinity is improved.

【0012】図2は、従来例の通常引上げ速度による基
板を用いて、H2 100%雰囲気中、1200℃,1時
間の熱処理を行なうことにより、どのサイズ(直径)か
らの析出物あるいは析出核がシュリンクするのかについ
て、同一基板での熱処理前後でのIRトモグラフ法を用
いた評価により調べた結果である。ほぼ直径30nmの
サイズを境にそれ以下のサイズの析出物あるいは析出核
が、急激に上記条件熱処理によりシュリンクすることが
わかる。これは、上記1200℃における熱処理に対す
る臨界直径がほぼ30nmであるためと考えられる。熱
処理温度をさらに高くすれば臨界直径は大きくなり、熱
処理温度を低くすれば臨界直径は小さくなる。したがっ
て、熱処理温度で決まる臨界直径に着目し、熱処理前に
臨界直径以下の析出物等の密度が高く含まれる密度分布
を有した半導体基板を選定し、この半導体基板を熱処理
すれば半導体基板の結晶性が大きくかつ高効率、高歩留
りで改善される。
FIG. 2 shows a precipitate or a precipitation nucleus from any size (diameter), which is obtained by performing heat treatment at 1200 ° C. for 1 hour in a 100% H 2 atmosphere using a conventional substrate at a normal pulling rate. Is a result of an examination using an IR tomography method before and after heat treatment on the same substrate. It is understood that the precipitates or the precipitation nuclei having a size smaller than the size of about 30 nm suddenly shrink due to the heat treatment under the above conditions. It is considered that this is because the critical diameter for the heat treatment at 1200 ° C. is about 30 nm. The higher the heat treatment temperature, the larger the critical diameter, and the lower the heat treatment temperature, the smaller the critical diameter. Therefore, paying attention to the critical diameter that is determined by the heat treatment temperature, select a semiconductor substrate that has a density distribution that contains a high density of precipitates and the like having a critical diameter or less before the heat treatment, and heat-treat this semiconductor substrate to crystallize the semiconductor substrate. It has high efficiency, high efficiency, and high yield.

【0013】また、CZ法において1.3mm/min
以上の高速度で引き上げれば、単結晶(インゴット)中
の臨界直径30nm以下の析出物等の密度分布が増大す
るので、この選定は容易となる。
In the CZ method, 1.3 mm / min
If the pulling speed is higher than the above, the density distribution of precipitates with a critical diameter of 30 nm or less in the single crystal (ingot) increases, so this selection becomes easy.

【0014】[0014]

【実施例】以下、図面を参照しながら、本発明の一実施
例について説明する。本実施例においては、150mm
φ、n型、格子間酸素濃度15×1017atoms/c
3 前後の単結晶を引き上げ速度1.3mm/minで
引き上げ、このCZ結晶から基板を作製した。通常引上
速度は1.0mm/minであるから、1.3倍高速で
引き上げたことになる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, 150 mm
φ, n-type, interstitial oxygen concentration 15 × 10 17 atoms / c
A single crystal of about m 3 was pulled at a pulling rate of 1.3 mm / min, and a substrate was produced from this CZ crystal. Since the pulling speed is usually 1.0 mm / min, the pulling speed is 1.3 times higher.

【0015】まず、アズ・グローン(As grow
n)結晶中の析出物あるいは析出核のサイズ及び密度
が、結晶引上げ速度の違いにより、どの様に変化するか
について、電子顕微鏡(TEM)を用いて調べた結果を
図1に示す。図1では従来例の通常引上げ速度の150
mmφ、n型、格子間酸素濃度15×1017atoms
/cm3 前後のCZ結晶から作製した基板の結果も同時
に示した。析出物あるいは析出核を球体と見なした場
合、直径が5〜20nmの範囲では、通常引上げ品に比
べ高速引上げ品の方が析出物あるいは析出核の密度が高
く、また、直径が30nm以上では逆に通常引上げ品の
方が析出物あるいは析出核の密度が高くなっていること
がわかる。
First, As grow (As grow)
n) FIG. 1 shows the results of examination using an electron microscope (TEM) to find out how the size and density of precipitates or precipitation nuclei in the crystal change due to the difference in crystal pulling rate. In FIG. 1, the normal pulling speed of the conventional example is 150.
mmφ, n-type, interstitial oxygen concentration 15 × 10 17 atoms
The results of the substrate made of CZ crystal of about / cm 3 are also shown at the same time. When the precipitate or the precipitation nucleus is regarded as a sphere, the density of the precipitate or the precipitation nucleus is higher in the high speed pulling product than in the normal pulling product in the diameter range of 5 to 20 nm, and when the diameter is 30 nm or more. On the contrary, it can be seen that the density of the precipitates or precipitation nuclei is higher in the normally pulled product.

【0016】次にこれらの基板を用いて、H2 100%
雰囲気中、1200℃、1時間の熱処理を行なう。図3
は評価を行なうために、IRトモグラフ法を用いて、赤
外散乱体密度の深さ方向プロファイル評価を行なった結
果である。参考のために従来例の基板の結果も図3に示
している。表面から深い所では高速引上げ品(本実施
例)と通常引上げ品(従来例)の散乱体密度は同じであ
るが、表層部では高速引上げ品の方が散乱体密度が少な
くなっていることがわかる。
Next, using these substrates, H 2 100%
Heat treatment is performed in an atmosphere at 1200 ° C. for 1 hour. FIG.
Is the result of evaluation of the infrared scatterer density in the depth direction profile using the IR tomography method. For reference, the results of the conventional substrate are also shown in FIG. Although the scatterer density of the high speed pulling product (this example) and the normal pulling product (conventional example) is the same at a deep place from the surface, the scatterer density of the high speed pulling product is lower in the surface layer part. Recognize.

【0017】なお、本実施例で用いた試料はn型、15
0mmφであるが、p型、200mmφへの適用もでき
る。この様に本発明の技術範囲を逸脱しない範囲で用い
る単結晶の種類、引上げ速度、熱処理雰囲気、熱処理温
度、熱処理時間などはいくらでも変形可能である。単結
晶の種類はMCZ法あるいは、連続引き上げ法によるも
のでもよく、引き上げ速度は1.3mm/min〜1.
7mm/minの間のいずれの値でもよい。2mm/m
inでもよく、速い引き上げ速度の方が望ましい。熱処
理温度は1200℃,1時間の他に1100℃,8時
間、1150℃,3時間、あるいは1250℃,40分
等としてもよい。また雰囲気はH2 とHe,Ne,A
r,Kr,Xeとの混合ガスや、Ne,Ar,Kr,X
eのうちのいずれかひとつによる不活性雰囲気でもよ
い。またHeとNeとの組み合わせ等、これらのうちの
2つ以上の組み合わせからなる混合ガスでもよい。さら
に望ましくは、所定の熱処理温度までの昇温プロセスを
Ar等の不活性ガスで行ない、所定の熱処理温度におけ
る熱処理を100%H2 等の還元性雰囲気で行うのがよ
い。
The samples used in this example are n-type and 15-type.
Although it is 0 mmφ, it can be applied to p-type and 200 mmφ. As described above, the type of single crystal used, the pulling rate, the heat treatment atmosphere, the heat treatment temperature, the heat treatment time, and the like can be modified without departing from the technical scope of the present invention. The type of the single crystal may be the MCZ method or the continuous pulling method, and the pulling rate is 1.3 mm / min to 1.
Any value between 7 mm / min may be used. 2 mm / m
In may be used, and a higher pulling rate is preferable. The heat treatment temperature may be 1200 ° C. for 1 hour, 1100 ° C. for 8 hours, 1150 ° C. for 3 hours, or 1250 ° C. for 40 minutes. The atmosphere is H 2 , He, Ne, A
Mixed gas of r, Kr, Xe, Ne, Ar, Kr, X
An inert atmosphere of any one of e may be used. A mixed gas composed of two or more of these, such as a combination of He and Ne, may be used. More preferably, the temperature rising process up to the predetermined heat treatment temperature is performed with an inert gas such as Ar, and the heat treatment at the predetermined heat treatment temperature is preferably performed in a reducing atmosphere such as 100% H 2 .

【0018】[0018]

【発明の効果】本発明の実施例による基板を用いて、M
OSキャパシタを作製した場合の良品率を従来技術と比
較したのが図4である。図4では本発明の実施例による
結果と、通常引き上げ品をH2 雰囲気中で熱処理した場
合、高速引き上げ結晶および通常引上げ結晶で熱処理し
ない場合をプロットしている。図4に示す試料の条件
は、酸化膜厚25nm、ポリシリコンゲート、面積10
mm2 のMOSキャパシタである。図4における不良の
判定は、酸化膜印加電界が8.0MV/cmのとき、ゲ
ート電流が1.0×10-5[A]以上となったものを不
良とした。H2 雰囲気中での熱処理を行なった場合、引
き上げ速度によらず、どちらの試料も90%以上の良品
率となるが、その中でも本実施例品がより良くなってい
ることがわかる。
By using the substrate according to the embodiment of the present invention, M
FIG. 4 compares the non-defective rate when the OS capacitor is manufactured with the conventional technique. FIG. 4 plots the results according to the example of the present invention and the cases where the normal pulling product is heat-treated in an H 2 atmosphere and the high-speed pulling crystal and the normal pulling crystal are not heat-treated. The conditions of the sample shown in FIG. 4 are as follows: oxide film thickness 25 nm, polysilicon gate, area 10
It is a MOS capacitor of mm 2 . In the determination of the defect in FIG. 4, when the electric field applied to the oxide film was 8.0 MV / cm, the gate current was 1.0 × 10 −5 [A] or more, and the defect was determined. When the heat treatment is performed in the H 2 atmosphere, the yield rate of both samples is 90% or more regardless of the pulling rate, and it is understood that the product of this example is better among them.

【0019】以上述べた様に、本発明によれば、半導体
基板中の散乱体密度が減少し、半導体基板上に形成した
MOSキャパシタの特性が改善される。
As described above, according to the present invention, the scatterer density in the semiconductor substrate is reduced and the characteristics of the MOS capacitor formed on the semiconductor substrate are improved.

【0020】また、本発明によれば、高速引上げ結晶
は、通常引上げ結晶よりも引上げ速度が大きい分生産効
率が高く、通常引上げ結晶よりもコストが低い。したが
って、この点を用いることにより、引上げ後に高温熱処
理工程が追加されても通常引上げ結晶から作製した基板
(熱処理無)以下のコストで本発明品の提供も可能とな
る。
Further, according to the present invention, the high-speed pulling crystal has a higher pulling speed than the normal pulling crystal and thus has higher production efficiency, and has a lower cost than the normal pulling crystal. Therefore, by using this point, even if a high temperature heat treatment step is added after the pulling, it is possible to provide the product of the present invention at a cost equal to or lower than that of a substrate (without heat treatment) usually manufactured from a pulled crystal.

【図面の簡単な説明】[Brief description of drawings]

【図1】引き上げたまま(As grown)の結晶中
の析出物等の密度分布の結晶引上げ速度による違いを示
す変化図。
FIG. 1 is a change diagram showing a difference in a density distribution of a precipitate or the like in a crystal as-grown (As grown) depending on a crystal pulling rate.

【図2】H2 100%雰囲気中、1200℃の熱処理で
シュリンクする析出物あるいは析出核のサイズ依存性を
示す図。
FIG. 2 is a diagram showing the size dependence of precipitates or precipitation nuclei shrinkable by heat treatment at 1200 ° C. in a H 2 100% atmosphere.

【図3】本実施例(高速引上げ+H2 雰囲気中熱処理
品)及び従来例(通常引上げ+H2 雰囲気中熱処理品)
における赤外光散乱体密度の深さ方向プロファイル。
FIG. 3 This example (high speed pulling + heat treatment in H 2 atmosphere) and conventional example (normal pulling + heat treatment in H 2 atmosphere)
Depth profile of infrared light scatterer density at.

【図4】本実施例(高速引上げ+H2 雰囲気中熱処理
品)、従来例(通常引上げ+H2雰囲気中熱処理品)、
熱処理をしない高速引上げ品、及び熱処理をしない通常
引上げ品を用いたMOSキャパシタの酸化膜耐圧評価結
果図。
[FIG. 4] This example (high speed pulling + heat treatment in H 2 atmosphere), conventional example (normal pulling + heat treatment in H 2 atmosphere),
FIG. 8 is a diagram showing the results of evaluation of the oxide film breakdown voltage of a MOS capacitor using a high speed pulling product without heat treatment and a normal pulling product without heat treatment.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 CZ法又はMCZ法のいずれかを用い、
1.3mm/min以上の引上げ速度で、シリコン単結
晶を成長し、該単結晶をスライスして半導体基板を形成
し、該半導体基板を還元性あるいは不活性雰囲気のいず
れかの雰囲気中で、1100℃以上の温度において30
分以上熱処理を行うことを特徴とする半導体基板の処理
方法。
1. Using either the CZ method or the MCZ method,
A silicon single crystal is grown at a pulling rate of 1.3 mm / min or more, a semiconductor substrate is formed by slicing the single crystal, and the semiconductor substrate is subjected to 1100 in either a reducing atmosphere or an inert atmosphere. 30 at temperatures above ℃
A method for treating a semiconductor substrate, characterized by performing heat treatment for not less than a minute.
【請求項2】 前記半導体基板において、析出物および
析出核(以下、析出物等という)の直径を1nm単位で
区分し、所定の直径以上の各区分における該析出物等の
密度が所定の密度以下の半導体基板を選定して、前記熱
処理を行うことを特徴とする請求項1記載の半導体基板
の処理方法。
2. In the semiconductor substrate, the diameters of precipitates and precipitation nuclei (hereinafter referred to as “precipitates, etc.”) are divided in units of 1 nm, and the density of the precipitates, etc. in each division having a predetermined diameter or more is a predetermined density. The semiconductor substrate processing method according to claim 1, wherein the following semiconductor substrate is selected and the heat treatment is performed.
【請求項3】 前記還元性雰囲気はほぼ100%の
2 、あるいはH2 とHe,Ne,Ar,Kr,Xeの
うち少なくとも一つとの混合ガスであることを特徴とす
る請求項1又は2記載の半導体基板の処理方法。
3. The reducing atmosphere is substantially 100% H 2 or a mixed gas of H 2 and at least one of He, Ne, Ar, Kr and Xe. A method for processing a semiconductor substrate as described above.
【請求項4】 前記不活性雰囲気はHe,Ne,Ar,
Kr,Xeのうちの少なくとも一つ以上から成ることを
特徴とする請求項1又は2記載の半導体基板の処理方
法。
4. The inert atmosphere is He, Ne, Ar,
The method for processing a semiconductor substrate according to claim 1 or 2, wherein the method comprises at least one of Kr and Xe.
【請求項5】 前記所定の直径は30nmで、前記所定
の密度は2×105個/cm3 であり、基板温度120
0℃で熱処理することを特徴とする請求項2記載の半導
体基板の処理方法。
5. The predetermined diameter is 30 nm, the predetermined density is 2 × 10 5 pieces / cm 3 , and the substrate temperature is 120.
The method for treating a semiconductor substrate according to claim 2, wherein the heat treatment is performed at 0 ° C.
JP25212594A 1994-10-18 1994-10-18 Method of processing semiconductor substrate Pending JPH08115919A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25212594A JPH08115919A (en) 1994-10-18 1994-10-18 Method of processing semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25212594A JPH08115919A (en) 1994-10-18 1994-10-18 Method of processing semiconductor substrate

Publications (1)

Publication Number Publication Date
JPH08115919A true JPH08115919A (en) 1996-05-07

Family

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Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH08115919A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11135511A (en) * 1997-10-29 1999-05-21 Nippon Steel Corp Silicon semiconductor substrate and manufacture thereof
JP2002527895A (en) * 1998-10-14 2002-08-27 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド Thermally annealed low defect density single crystal silicon
US6551398B2 (en) 1997-12-17 2003-04-22 Shin-Etsu Handotai Co., Ltd. Heat treatment method for a silicon monocrystal wafer and a silicon monocrystal wafer
JP2005322875A (en) * 2004-05-10 2005-11-17 Siltron Inc Silicon wafer and method for manufacturing same
JP2006315950A (en) * 1996-09-12 2006-11-24 Siltronic Ag Method for manufacturing silicon semiconductor wafer having low defect density

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006315950A (en) * 1996-09-12 2006-11-24 Siltronic Ag Method for manufacturing silicon semiconductor wafer having low defect density
JP2011042576A (en) * 1996-09-12 2011-03-03 Siltronic Ag Method of manufacturing silicon semiconductor wafer having low defect density
JPH11135511A (en) * 1997-10-29 1999-05-21 Nippon Steel Corp Silicon semiconductor substrate and manufacture thereof
US6551398B2 (en) 1997-12-17 2003-04-22 Shin-Etsu Handotai Co., Ltd. Heat treatment method for a silicon monocrystal wafer and a silicon monocrystal wafer
KR100578162B1 (en) * 1997-12-17 2006-09-18 신에쯔 한도타이 가부시키가이샤 Heat treatment method of silicon single crystal wafer and silicon single crystal wafer
JP2002527895A (en) * 1998-10-14 2002-08-27 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド Thermally annealed low defect density single crystal silicon
JP4875800B2 (en) * 1998-10-14 2012-02-15 エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド Manufacturing method of single crystal silicon wafer
JP2005322875A (en) * 2004-05-10 2005-11-17 Siltron Inc Silicon wafer and method for manufacturing same

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