JP3533238B2 - Semiconductor substrate - Google Patents

Semiconductor substrate

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Publication number
JP3533238B2
JP3533238B2 JP03869894A JP3869894A JP3533238B2 JP 3533238 B2 JP3533238 B2 JP 3533238B2 JP 03869894 A JP03869894 A JP 03869894A JP 3869894 A JP3869894 A JP 3869894A JP 3533238 B2 JP3533238 B2 JP 3533238B2
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JP
Japan
Prior art keywords
substrate
semiconductor substrate
heat treatment
average
dopant impurity
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JP03869894A
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Japanese (ja)
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JPH07249588A (en
Inventor
井 勉 天
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Toshiba Corp
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Toshiba Corp
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Publication of JPH07249588A publication Critical patent/JPH07249588A/en
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Description

【発明の詳細な説明】 【0001】 【産業上の利用分野】本発明は、半導体基板に係り、と
りわけ半導体基板の表面近傍の格子間酸素濃度を析出が
生じない程度まで低下させることができる半導体基板に
関する。 【0002】 【従来の技術】従来から、シリコン半導体デバイスに用
いられるシリコン半導体基板は、チョクラルスキー法
(CZ法)によって製造されたシリコン単結晶インゴッ
トを切り出して作成されている。このCZ法によって製
造されたインゴットを切り出して作成されたシリコン基
板には、シリコン単結晶インゴットを石英るつぼから引
き上げる際、常温で酸素が過飽和に含有される。そし
て、この過剰な酸素は半導体製造プロセス中の熱処理に
より、例えばSiO2 という形で析出される。しかしな
がら、シリコン半導体基板のデバイス作成表面近傍で、
このような酸素析出が発生すると、デバイスに悪影響を
及ぼしてしまう。 【0003】そこで、シリコン半導体基板をH2 ,Ar
等のガス雰囲気中で熱処理することにより、シリコン半
導体基板の表面近傍から過飽和の酸素を除去している。
これによってシリコン半導体基板の表面近傍における酸
素析出物やOSF(Oxidation-induced Stacking Faul
t)等の結晶欠陥を大幅に減少させ、その後積層される
酸化膜における例えば8MV/cm以下の電界での不良を
減少させている。このため、シリコン半導体基板表面の
高品質技術として、H,Ar等のガス雰囲気での熱処
理技術が注目されている。なお、H,Ar等のガス雰
囲気による熱処理は、シリコン半導体基板表面近傍の格
子間酸素の外法拡散を十分行ない、基板表面の高品質化
の効果を十分ならしめるため、1100℃以上の温度で
行なわれている。 【0004】 【発明が解決しようとする課題】しかしながら、110
0℃以上の温度でH2 ,Ar等のガスによる熱処理を行
なった場合、シリコン半導体基板の表面近傍において抵
抗率が高くなってしまうことがある。これは、H,A
r等のガス雰囲気による熱処理中に表面近傍の格子間酸
素の外方拡散が行なわれるが、これと同時に、図4に示
すように表面近傍のドーパント(不純物)も外方へ拡散
するためと考えられている。このため、H,Ar等の
ガス雰囲気中で熱処理を行なったシリコン半導体基板
を、特に高集積度のデバイス(DRAM,EPROM
等)に用いる場合、次の様な問題を生ずる。 【0005】すなわち、(1)素子間分離を半導体基板
の抵抗率を利用して行なっている場合、抵抗率が高くな
る分だけトランジスタのドレイン及びソースの空乏層を
広がりやすくするため、パンチスルーが生じやすくな
る。 【0006】(2) 抵抗率が高くなる分、ドレイン、
ソース等の素子、well部等、他の抵抗部分との抵抗
率差が大きくなり、その分ラッチアップが生じやすくな
る。 【0007】(3) 半導体基板の表面近傍の高抵抗率
化を考慮して、上記(1)、(2)の問題点をなくすよ
うデバイス設計を行う場合、個々の半導体基板及び半導
体基板の表面における抵抗率の変化は、熱処理前よりも
熱処理後の方がかなり大きくなることが予想され、デバ
イス設計をより困難なものにしてしまう。 【0008】本発明はこのような点を考慮してなされた
ものであり、H,Ar等のガス雰囲気中で熱処理を行
なうことにより表面近傍の高品質化を図ることができ、
かつ表面近傍の高抵抗率を防ぐことができる半導体基板
を提供することを目的とする。 【0009】 【課題を解決するための手段】本発明はシリコン半導体
において、深さ50μm以上の基板内部の平均格子間酸
素濃度が、深さ3μm以下の基板表面の平均格子間酸素
濃度の5倍以上で、前記基板表面の平均格子間酸素濃度
が2×1017atoms/cm3 以下であり、かつ基板内部の平
均ドーパント不純物濃度と基板表面の平均ドーパント不
純物濃度の差が基板内部の平均ドーパント不純物濃度に
対して5%以下であることを特徴とするシリコン半導体
基板である。 【0011】 【作用】本発明によれば、半導体基板表面の平均格子間
酸素濃度が2×1017atms/cm3 以下であり、また基板
内部の平均格子間酸素濃度が基板表面の平均格子間酸素
濃度の5倍以上なので、半導体製造プロセス中の熱処理
において、酸化物が析出してデバイスに影響を与えるこ
とはない。また基板内部と基板表面のドーパント不純物
濃度の差が基板内部の平均ドーパント不純物濃度に対し
て5%以下であるので、表面における抵抗率上昇を防ぐ
ことができる。 【0013】 【実施例】以下、図面を参照して、本発明の実施例につ
いて説明する。まずチョクラルスキー法(CZ法)によ
り育成したドーパントがP(リン)のN型20〜30Ω
・cmのシリコンインゴットを製造する。次にシリコンイ
ンゴットを所定の厚さに切り出し、片面の鏡面加工およ
び洗浄等を行ない、シリコン半導体基板10(図5)を
作成する。次にこのシリコン半導体基板10に対して、
熱処理炉内において7ppm程度のPH3 を含有するH
2 ガス雰囲気中で、1200℃、1時間の熱処理(アニ
ール)を行なう。 【0014】本発明による熱処理を施した後の半導体基
板10の酸素濃度プロファイルおよびドーパント不純物
プロファイルを図3に示し、従来例のPH3 を含まない
2 ガス雰囲気中で1200℃、1時間の熱処理をした
後の半導体基板10の酸素濃度プロファイルおよびドー
パント不純物プロファイルを図4に示す。図3に示す本
発明では、ドーパント不純物濃度が、半導体基板10の
表面10a近傍で低下しておらず略一定であるのに対
し、図4に示す従来例ではドーパント不純物濃度が表面
近傍で低下する。 【0015】このように、H2 ガス雰囲気中でシリコン
半導体基板に対して熱処理を施すことにより、半導体基
板10の表面10a近傍の酸素原子を外方に拡散するこ
とができ、これによってシリコン半導体基板10の表面
10a近傍での酸素濃度を低下させることができる。 【0016】また、H2 ガス中にPH3 を混合させるこ
とにより、熱処理中に半導体基板10内部へP(リン)
の導入を行うことができる。このため熱処理中に半導体
基板10内部から外方拡散していくP(リン)の不足分
を補うことができ、半導体基板10の表面10a近傍の
P(リン)の濃度低下を防止して、表面10a近傍の抵
抗率の上昇を防ぐことができる。 【0017】H2 ガスに含有されるPH3 の濃度は、熱
処理前の基板10の抵抗率と、熱処理後の基板10の抵
抗率が同一になるように適正な値に定められ、同様に熱
処理濃度も熱処理前後の基板10の抵抗率が同一になる
よう定められる。 【0018】図3に示すように、本実施例によれば、深
さ50μm以上の基板10内部の平均格子間酸素濃度は
1.6×1018atms/cm3 となり、深さ3μm以下の基
板10の表面10aの平均格子間酸素濃度は1.8×1
17atms/cm3 となる。このため両者の比は8.8:1
となる。また、基板10内部の平均ドーパント不純物濃
度は7×1014atms/cm3 であり、基板10の表面10
aの平均ドーパント不純物濃度も同様に7×1014atms
/cm3 となる。 【0019】なお、基板表面の平均格子間酸素濃度が2
×1017atms/cm3 以下であり、また基板内部の平均格
子間酸素濃度が、基板表面の平均格子間酸素濃度の5倍
以上であれば、半導体製造プロセス中の熱処理において
デバイスに影響を与えることはない。また基板内部と基
板表面のドーパント不純物濃度の差が基板内部の平均ド
ーパント不純物濃度に対して5%以下であれば、表面の
抵抗率上昇を防止することができる。 【0020】図3に示すように本実施例によれば、上記
のようなデバイスに影響を与えない基準を満しているこ
とがわかる。 【0021】本実施例ではPH3 の含有量を7ppmと
し、熱処理濃度を1200℃とした例を示したが、これ
に限らずH2 ガス雰囲気中のPH3 含有量を2〜10p
pmとすれば、半導体基板10の表面10a近傍におい
てドーパント不純物濃度の低下を防ぐことができ、図3
に示す結果と略同様の結果を得ることができる。またP
3 を含有するH2 ガス雰囲気中の熱処理温度は120
0℃に限らず、1100℃〜1250℃であればよい。
さらにH2 ガスの代わりにArガスを用いてもよい。 【0022】またドーパントがBoronのP型シリコ
ン基板を熱処理する場合は、1〜5ppm、好ましくは
3.5ppmのB2 6 をH2 ガス中に含有させ、12
00℃で熱処理することにより、図3に示す結果と略同
様の結果を得ることかできる。 (具体例) 次に本発明によるPH3 ガスを含むH2 ガス中で120
0℃、1時間加熱する熱処理方法により得られたシリコ
ン半導体基板と、PH3 を含まないH2 ガス中で120
0℃、1時間熱処理した従来例のシリコン半導体基板
と、H2 ガス中での熱処理を行なわない比較例のシリコ
ン半導体基板を用いて半導体デバイスを作成した。次に
各々の半導体基板に対してパンチスルーとラッチアップ
の各々の発生率を調べた。その結果を図1に示す。 【0023】図1に示すように、半導体デバイスにおけ
るパンチスルーおよびラッチアップの発生率は、 【0024】 【数1】 となり、本発明によるPH3 を含むH2 ガス中での熱処
理の場合、PH3 を含まない従来の場合に比べ、大幅な
改善か見られる。また、上記3種のシリコン半導体基板
を用いて、20nmのゲート酸化膜(SiO2 膜)を90
0℃のO2 酸化で形成した。その後ゲート電極を形成し
てMOS型キャパシタを作成し、これを用いてゲート酸
化膜の絶縁耐圧の測定を行った。この結果を図2に示
す。図2に示すように8MV/cm以下での酸化膜絶縁耐
圧不良率は、 【0025】 【数2】 となり、1200℃の温度で1時間にわたるH2 ガス中
での熱処理を行うことにより、酸化膜絶縁耐圧が大幅に
改善されることがわかる。 【0026】以上のように本実施例によれば、ドーパン
トを含む分子を含有するH,Ar等のガス雰囲気で熱
処理を行うことにより、良好な酸化膜特性等シリコン基
板の高品質化を図ることができ、かつ熱処理による基板
10の表面10a近傍の高抵抗化という問題を防止する
ことができる。これによってラッチアップ、パンチスル
ーという半導体デバイスの特性劣化を防ぐことができ
る。 【0027】 【発明の効果】以上説明したように本発明によれば、半
導体製造プロセスの熱処理中に、酸化物が析出してデバ
イスに影響を与えることはない。また基板表面における
抵抗率の上昇を防止することができる。このため精度の
高い半導体基板を得ることができる。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate, and more particularly to a semiconductor capable of reducing the interstitial oxygen concentration in the vicinity of the surface of a semiconductor substrate to such an extent that precipitation does not occur. Regarding the substrate. 2. Description of the Related Art Conventionally, a silicon semiconductor substrate used for a silicon semiconductor device has been manufactured by cutting out a silicon single crystal ingot manufactured by the Czochralski method (CZ method). When a silicon single crystal ingot is pulled up from a quartz crucible, oxygen is supersaturated at room temperature when the silicon substrate produced by cutting out the ingot manufactured by the CZ method. Then, this excess oxygen is deposited in the form of, for example, SiO 2 by heat treatment during the semiconductor manufacturing process. However, near the device fabrication surface of the silicon semiconductor substrate,
The occurrence of such oxygen precipitation adversely affects the device. Therefore, a silicon semiconductor substrate is made of H 2 , Ar
By performing heat treatment in such a gas atmosphere, supersaturated oxygen is removed from the vicinity of the surface of the silicon semiconductor substrate.
As a result, oxygen precipitates and OSF (Oxidation-induced Stacking Failure) near the surface of the silicon semiconductor substrate
Crystal defects such as t) are greatly reduced, and defects in an oxide film to be subsequently laminated are reduced, for example, in an electric field of 8 MV / cm or less. For this reason, a heat treatment technique in a gas atmosphere of H 2 , Ar, or the like has attracted attention as a high quality technique for a silicon semiconductor substrate surface. The heat treatment in a gas atmosphere of H 2 , Ar, or the like is performed at a temperature of 1100 ° C. or higher in order to sufficiently perform the external diffusion of interstitial oxygen near the surface of the silicon semiconductor substrate and sufficiently enhance the effect of improving the quality of the substrate surface. It is done in. [0004] However, 110
When heat treatment with a gas such as H 2 or Ar is performed at a temperature of 0 ° C. or higher, the resistivity may increase near the surface of the silicon semiconductor substrate. This is H 2 , A
It is thought that interstitial oxygen near the surface diffuses outward during heat treatment in a gas atmosphere such as r, but at the same time, dopants (impurities) near the surface also diffuse outward as shown in FIG. Have been. For this reason, a silicon semiconductor substrate that has been heat-treated in a gas atmosphere of H 2 , Ar, or the like can be used, in particular, for highly integrated devices (DRAM, EPROM).
) Causes the following problems. [0005] (1) When the isolation between elements is performed by using the resistivity of the semiconductor substrate, the depletion layers of the drain and the source of the transistor are easily spread by the increase of the resistivity. It is easy to occur. (2) As the resistivity increases, the drain,
An element such as a source, a resistance difference from a well part such as a well part becomes large, and latch-up is easily caused accordingly. (3) When a device is designed to eliminate the problems (1) and (2) in consideration of the increase in resistivity near the surface of the semiconductor substrate, the individual semiconductor substrate and the surface of the semiconductor substrate are designed. Is expected to be much greater after heat treatment than before heat treatment, making device design more difficult. The present invention has been made in view of the above points, and by performing heat treatment in a gas atmosphere of H 2 , Ar, etc., it is possible to improve the quality near the surface,
It is another object of the present invention to provide a semiconductor substrate capable of preventing high resistivity near the surface. According to the present invention, in a silicon semiconductor, the average interstitial oxygen concentration inside a substrate having a depth of 50 μm or more is five times the average interstitial oxygen concentration on the surface of a substrate having a depth of 3 μm or less. As described above, the average interstitial oxygen concentration on the substrate surface is 2 × 10 17 atoms / cm 3 or less, and the difference between the average dopant impurity concentration inside the substrate and the average dopant impurity concentration on the substrate surface is the average dopant impurity inside the substrate. A silicon semiconductor substrate characterized in that the concentration is 5% or less with respect to the concentration. According to the present invention, the average interstitial oxygen concentration on the surface of the semiconductor substrate is 2 × 10 17 atms / cm 3 or less, and the average interstitial oxygen concentration in the substrate is lower than the average interstitial oxygen concentration on the substrate surface. Since the oxygen concentration is five times or more, the oxide does not precipitate during the heat treatment during the semiconductor manufacturing process and does not affect the device. Further, since the difference between the dopant impurity concentration in the substrate and the dopant impurity concentration in the substrate surface is 5% or less with respect to the average dopant impurity concentration in the substrate, an increase in resistivity on the surface can be prevented. Embodiments of the present invention will be described below with reference to the drawings. First, the dopant grown by the Czochralski method (CZ method) is an N-type of P (phosphorus) 20 to 30Ω.
・ Production of cm silicon ingot. Next, the silicon ingot is cut into a predetermined thickness, mirror-polished on one side, washed, and the like, to produce a silicon semiconductor substrate 10 (FIG. 5). Next, for this silicon semiconductor substrate 10,
H containing about 7 ppm PH 3 in the heat treatment furnace
Heat treatment (annealing) is performed at 1200 ° C. for one hour in a two- gas atmosphere. FIG. 3 shows an oxygen concentration profile and a dopant impurity profile of the semiconductor substrate 10 after the heat treatment according to the present invention. The heat treatment at 1200 ° C. for 1 hour in a conventional H 2 gas atmosphere containing no PH 3 is shown. FIG. 4 shows the oxygen concentration profile and the dopant impurity profile of the semiconductor substrate 10 after the above. In the present invention shown in FIG. 3, the dopant impurity concentration does not decrease near the surface 10a of the semiconductor substrate 10 and is substantially constant, whereas in the conventional example shown in FIG. 4, the dopant impurity concentration decreases near the surface. . As described above, by subjecting the silicon semiconductor substrate to a heat treatment in an H 2 gas atmosphere, oxygen atoms near the surface 10a of the semiconductor substrate 10 can be diffused outward, thereby allowing the silicon semiconductor substrate 10 to be diffused. The oxygen concentration in the vicinity of the surface 10a can be reduced. Further, by mixing PH 3 in H 2 gas, P (phosphorus) is introduced into the semiconductor substrate 10 during the heat treatment.
Can be introduced. Therefore, the shortage of P (phosphorus) that diffuses outward from the inside of the semiconductor substrate 10 during the heat treatment can be compensated for, and a decrease in the concentration of P (phosphorus) near the surface 10a of the semiconductor substrate 10 can be prevented. An increase in resistivity near 10a can be prevented. The concentration of PH 3 contained in the H 2 gas is set to an appropriate value so that the resistivity of the substrate 10 before the heat treatment is equal to the resistivity of the substrate 10 after the heat treatment. The concentration is also determined so that the resistivity of the substrate 10 before and after the heat treatment becomes the same. As shown in FIG. 3, according to the present embodiment, the average interstitial oxygen concentration in the substrate 10 having a depth of 50 μm or more is 1.6 × 10 18 atms / cm 3 , and the substrate having a depth of 3 μm or less is provided. The average interstitial oxygen concentration on the surface 10a of the sample 10 is 1.8 × 1
0 17 atms / cm 3 . Therefore, the ratio between the two is 8.8: 1.
It becomes. The average dopant impurity concentration inside the substrate 10 is 7 × 10 14 atms / cm 3 ,
The average dopant impurity concentration of a is also 7 × 10 14 atms
/ Cm 3 . The average interstitial oxygen concentration on the substrate surface is 2
× is the 10 17 atms / cm 3 or less, the average interstitial oxygen concentration in the substrate is equal to or more than 5 times the average interstitial oxygen concentration of the substrate surface, affecting the device in the heat treatment in the semiconductor manufacturing process Never. When the difference between the dopant impurity concentration in the substrate and the dopant impurity concentration in the substrate surface is 5% or less of the average dopant impurity concentration in the substrate, an increase in the surface resistivity can be prevented. As shown in FIG. 3, according to the present embodiment, it is understood that the above-described criteria that do not affect the device are satisfied. In this embodiment, the PH 3 content is set to 7 ppm and the heat treatment concentration is set to 1200 ° C. However, the present invention is not limited to this, and the PH 3 content in the H 2 gas atmosphere is set to 2 to 10 p.
pm, it is possible to prevent a decrease in the dopant impurity concentration in the vicinity of the surface 10a of the semiconductor substrate 10;
Can be obtained. Also P
The heat treatment temperature in an H 2 gas atmosphere containing H 3 is 120.
The temperature is not limited to 0 ° C. and may be 1100 ° C. to 1250 ° C.
Further, Ar gas may be used instead of H 2 gas. When a P-type silicon substrate having a boron dopant is heat-treated, 1 to 5 ppm, preferably 3.5 ppm, of B 2 H 6 is contained in H 2 gas,
By performing the heat treatment at 00 ° C., a result substantially similar to the result shown in FIG. 3 can be obtained. (Specific Example) Next, in H 2 gas containing PH 3 gas according to the present invention, 120
0 ° C., and the silicon semiconductor substrate obtained by the heat treatment method of heating 1 hour, with H 2 gas containing no PH 3 120
Semiconductor devices were fabricated using a conventional silicon semiconductor substrate heat-treated at 0 ° C. for 1 hour and a comparative silicon semiconductor substrate not heat-treated in H 2 gas. Next, the occurrence rates of punch-through and latch-up were examined for each semiconductor substrate. The result is shown in FIG. As shown in FIG. 1, the occurrence rates of punch-through and latch-up in a semiconductor device are as follows: Thus, in the case of the heat treatment in the H 2 gas containing PH 3 according to the present invention, a remarkable improvement can be seen as compared with the conventional case not containing PH 3 . Further, a gate oxide film (SiO 2 film) having a thickness of 20 nm is
It was formed by O 2 oxidation at 0 ° C. Thereafter, a gate electrode was formed to form a MOS capacitor, and the dielectric breakdown voltage of the gate oxide film was measured using the MOS capacitor. The result is shown in FIG. As shown in FIG. 2, the oxide film dielectric strength failure rate at 8 MV / cm or less is given by: It can be seen that the heat treatment in H 2 gas at a temperature of 1200 ° C. for one hour greatly improves the oxide withstand voltage. As described above, according to the present embodiment, the heat treatment is performed in a gas atmosphere containing molecules including a dopant, such as H 2 or Ar, thereby improving the quality of the silicon substrate such as good oxide film characteristics. In addition, it is possible to prevent the problem of increasing the resistance near the surface 10a of the substrate 10 due to the heat treatment. As a result, it is possible to prevent the characteristic degradation of the semiconductor device such as latch-up and punch-through. As described above, according to the present invention, oxides do not precipitate during the heat treatment in the semiconductor manufacturing process and do not affect the device. Further, an increase in resistivity on the substrate surface can be prevented. Therefore, a highly accurate semiconductor substrate can be obtained.

【図面の簡単な説明】 【図1】半導体デバイスでのパンチスルー、ラッチアッ
プの発生率を本発明と従来例と比較例とを比較して示す
図。 【図2】8MV/cm以下での酸化膜絶縁耐圧不良率を本
発明と従来例と比較例とを比較して示す図。 【図3】本発明におけるドーパント不純物濃度と格子間
不純物濃度の基板表面からの深さ方向の分布図。 【図4】従来例におけるドーパント不純物濃度と格子間
不純物濃度の基板表面からの深さ方向の分布図。 【図5】半導体基板を示す図。 【符号の説明】 10 半導体基板 10a基板表面
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing the occurrence rates of punch-through and latch-up in a semiconductor device in comparison with the present invention, a conventional example, and a comparative example. FIG. 2 is a diagram showing the oxide film dielectric strength failure rate at 8 MV / cm or less, comparing the present invention, a conventional example, and a comparative example. FIG. 3 is a distribution diagram of a dopant impurity concentration and an interstitial impurity concentration in a depth direction from a substrate surface in the present invention. FIG. 4 is a distribution diagram of a dopant impurity concentration and an interstitial impurity concentration in a depth direction from a substrate surface in a conventional example. FIG. 5 illustrates a semiconductor substrate. [Description of Signs] 10 Semiconductor substrate 10a Substrate surface

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/22 H01L 21/322 H01L 21/324 ──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/22 H01L 21/322 H01L 21/324

Claims (1)

(57)【特許請求の範囲】 【請求項1】シリコン半導体において、深さ50μm以
上の基板内部の平均格子間酸素濃度が、深さ3μm以下
の基板表面の平均格子間酸素濃度の5倍以上で、前記基
板表面の平均格子間酸素濃度が2×1017atoms/cm3
下であり、かつ基板内部の平均ドーパント不純物濃度と
基板表面の平均ドーパント不純物濃度の差が基板内部の
平均ドーパント不純物濃度に対して5%以下であること
を特徴とするシリコン半導体基板。
(57) Claims 1. In a silicon semiconductor, the average interstitial oxygen concentration inside a substrate having a depth of 50 µm or more is at least 5 times the average interstitial oxygen concentration on a substrate surface having a depth of 3 µm or less. Wherein the average interstitial oxygen concentration on the substrate surface is 2 × 10 17 atoms / cm 3 or less, and the difference between the average dopant impurity concentration inside the substrate and the average dopant impurity concentration on the substrate surface is the average dopant impurity concentration inside the substrate. 5% or less of the silicon semiconductor substrate.
JP03869894A 1994-03-09 1994-03-09 Semiconductor substrate Expired - Lifetime JP3533238B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03869894A JP3533238B2 (en) 1994-03-09 1994-03-09 Semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03869894A JP3533238B2 (en) 1994-03-09 1994-03-09 Semiconductor substrate

Publications (2)

Publication Number Publication Date
JPH07249588A JPH07249588A (en) 1995-09-26
JP3533238B2 true JP3533238B2 (en) 2004-05-31

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JP (1) JP3533238B2 (en)

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Publication number Priority date Publication date Assignee Title
JP5625239B2 (en) * 2008-12-25 2014-11-19 信越半導体株式会社 Manufacturing method of bonded wafer

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