JPH08115890A - Formation of electrode on semiconductor substrate - Google Patents

Abstract

PURPOSE: To reduce the electric resistance of an electrode, improve the uniform ity of electric resistance, and effectively erode and eliminate interstitial transi tion loops, by employing a highly reducible metal as first metal to be removed after heat treatment. CONSTITUTION: A LOCOS oxide film 3 is formed on a Si substrate 1, and a region where an electrode is to be formed is defined and a n<+> -region 6 is formed there. A Ti film 7 as first metal highly reducible is formed by RF sputtering on the entire surface of the substrate. Heat treatment is performed at low temperature to form a TiSi2 layer 8. The unreacted Ti film 7 is removed from the LOCOS oxide film 3, and heat treatment is performed at high temperature to remove the TiSi2 layer 9. A Co film 10 as second metal is formed by sputtering on the entire surface of the Si substrate 1, and heat treatment is performed at low temperature to form an unreacted CoSi2 layer 11. The Co film 10 remaining on the LOCOS oxide film 3 is removed, and then heat treatment is performed at high temperature to form a CoSi2 layer 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improved method for forming electrodes on a semiconductor substrate in a semiconductor device or a semiconductor integrated circuit device, in particular, a method for forming metal silicide, and more specifically, defects in source junction or drain junction. And a method of forming an electrode on a semiconductor substrate for the purpose of reducing the increase in electric resistance due to the residual oxide film at the interface between the electrode metal and the semiconductor substrate.

[0002]

2. Description of the Related Art FIGS. 6 and 7 are schematic explanatory views of a conventional method for forming an electrode on a semiconductor substrate, and FIGS. 6A to 6H show respective steps. In this figure, 21 is a Si substrate, 22 is a Si ₃ N ₄ stripe mask, and 23 is a LOC.
An OS oxide film, 24 is a protective film, 25 is As, 26 is an n ⁺ region, 27 is a Co film, 28 is an unreacted CoSi ₂ layer, and 29 is a CoSi ₂ layer. With reference to this figure, a process of forming a CoSi ₂ electrode on an n ⁺ region such as a source region and a drain region in a conventional LSI will be described.

First step (see FIG. 6A) (001) Si is formed on the entire surface of the Si substrate 21.₃N_FourShape the membrane
Formed and patterned to form Si₃N_Four
A stripe mask 22 is formed, and this Si₃N _FourStra
The silicon substrate surface is wiped with the ip mask 22 as an oxidation resistant mask.
Etching is performed to form a LOCOS oxide film 23. That
Later Si₃N_FourStripe mask 22 is removed.

Second step (see FIG. 6B) After forming a thin protective film 24 of SiO ₂ or the like on the entire surface, through the protective film 24, As 25 which is an n-type impurity.
Is ion-implanted. In this case, the acceleration voltage of As ⁺ ions is set to 30 keV and the dose amount is (2 to 5) × 10 ¹⁵ / c.
m ^-2 .

Third step (see FIG. 6C) Rapid thermal annealing (RTA) is performed at 850 ° C. for 30 seconds to activate the implanted impurities (As) to form the n ⁺ region 26.

Fourth step (see FIG. 6D) The thin protective film 24 such as SiO ₂ is removed by an HF solution.

Fifth Step (see FIG. 7E) The Si substrate 21 having the LOCOS oxide film 23 and the n ⁺ region 26 formed therein is introduced into an RF sputtering apparatus to deposit a Co film 27.

Step 6 (see FIG. 7 (F)) Heat treatment (RT) at 650 ° C. for 30 seconds in Ar atmosphere
A) is applied to react the Co film 27 with the Si substrate 21,
Unreacted CoSi ₂ layer 28 containing Co ₂ Si, CoSi, etc.
To form. The unreacted CoSi ₂ layer 28 has a lattice constant different from that of the Si substrate 21, has random crystal directions, and is inferior in flatness.

Seventh step (see FIG. 7G) The Co film 27 remaining on the LOCOS oxide film 23 is removed by etching with, for example, a mixed solution of H ₂ O ₂ + HCl.

Eighth step (see FIG. 7H) CoSi having a flat interface and a low electric resistance is subjected to a heat treatment by RTA at 750 ° C. for 30 seconds in an Ar atmosphere.
_Two layers 29 are formed.

[0011]

Various metal silicides are used as electrode materials in Si-ULSI, and particularly TiSi ₂ and CoSi ₂ having low resistance are put to practical use. In addition, CoSi ₂ has a smaller grain size than TiSi ₂ , and is attracting attention as a narrow electrode material due to future miniaturization. By the way, the conventional Co silicide formation method has the following problems.

One of them is Si that sputters Co.
Since the residual oxide film exists on the surface of the substrate, Co is easily oxidized, and C is present at the interface between the Co silicide film and the Si substrate.
o Oxide is nonuniformly formed, causing high resistance and nonuniformity of electrode resistance.

The other one is an activation process of impurities by heat treatment performed after ion implantation of impurities, and when impurities are ion-implanted, S generated in a deep portion of a damaged layer of a crystal.
Interstitial semiconductor atoms such as i and Ge condense to form a lattice defect called a dislocation loop, and if the dislocation loop is formed near the source junction or the drain junction, the leak current increases and the junction characteristics deteriorate. May cause.

The present invention effectively removes the oxide remaining on the substrate surface in the step after ion implantation to reduce the electric resistance of the electrode and improve the uniformity of the electric resistance in the plane of the semiconductor substrate. Another object of the present invention is to provide means for effectively eroding and eliminating interstitial dislocation loops, reducing the leak current of the source junction and the drain junction, improving the reliability of the electrode, and improving the yield. To do.

[0015]

In the method of forming an electrode on a semiconductor substrate according to the present invention, a step of depositing a first metal having a reducing ability on the semiconductor substrate, the semiconductor substrate and the semiconductor substrate by heat treatment. A step of forming a reaction product with a first metal; a step of removing a reaction product of the semiconductor substrate and the first metal; a step of removing the reaction product of the semiconductor substrate and the first metal; A step of depositing a second metal having a reducing ability lower than that of the first metal after removing the reaction product, and a step of forming a reaction product of the semiconductor substrate and the second metal by heat treatment. Adopted.

In this case, it is possible to reduce the number of steps for transferring the reaction device by carrying out all the steps in one vacuum device to prevent oxidation due to exposure to the atmosphere.

In this case, silicon (Si), germanium (Ge) or a mixed crystal of silicon and germanium can be used as the semiconductor substrate.

Further, in these cases, the first reducing ability is high.
Ti, Zr, and Hf can be used as the metal, and Co, V, Nb, Ta, C, Mo, W, or Y can be used as the second metal.

[0019]

FIG. 1 is an explanatory view of the principle of the method of forming an electrode on a semiconductor substrate according to the present invention, and (A) to (D) show respective steps. In these figures, 1 is the Si substrate, 3 is the LO substrate
COS oxide film, 6 n ⁺ region, 7 Ti film, 8 C49
Phase TiSi ₂ layer, 9 is C54 phase TiSi ₂ layer, 10
Is a Co film, 11 is an unreacted CoSi ₂ layer, and 12 is CoSi
_{There are two} layers.

The principle of the method for forming an electrode on a semiconductor substrate according to the present invention will be described with reference to this principle explanatory diagram.

First step (see FIG. 1A) A LOCOS oxide film 3 is formed on a Si substrate 1 to define a region for forming an electrode, and a thin protective film such as SiO ₂ is formed on the region. , As is ion-implanted through this protective film,
The implanted As is activated to form the n ⁺ region 6. After removing this protective film, a Ti film 7 is deposited on the entire surface by RF sputtering as a first metal having a high reducing ability, and is subjected to a heat treatment at a relatively low temperature of about 700 ° C. in an Ar atmosphere to form a Ti film 7. C49 phase TiSi is reacted with the Si substrate 1.
_Two layers 8 are formed.

Second step (see FIG. 1B) After the unreacted Ti film 7 on the LOCOS oxide film 3 is removed by chemical etching, 85 in an Ar atmosphere.
A TiSi ₂ layer 8 is formed by heat treatment at a relatively high temperature of about 0 ° C.
And Si substrate 1 are further reacted to produce C54 phase TiSi ₂
A layer 9 is formed and this C54 phase TiSi ₂ layer 9 is removed by chemical etching.

Third Step (see FIG. 1C) After removing the C54 phase TiSi ₂ layer 9, a Co film 10 is formed as a second metal on the entire surface of the Si substrate 1 by a sputtering method, and 650 is formed. The Co film 10 and the Si substrate 1 are reacted with each other by applying a heat treatment at a relatively low temperature of about deg.
Co ₂ Si, CoSi only in the region inside the OS oxide film 3
An unreacted CoSi ₂ layer 11 including the above is formed.

Fourth Step (see FIG. 1D) After the Co film 10 remaining on the LOCOS oxide film 3 is removed by chemical etching, heat treatment at a relatively high temperature of about 750 ° C. is applied to the CoSi ₂ layer. 12 is formed.

In the third step, the unreacted CoSi ₂ layer 11 formed at a relatively low temperature does not lattice-match with the Si substrate 1 and has a random crystal direction and poor flatness.
In-process CoSi ₂ layer 1 reacted at relatively high temperature
No. 2 has lattice matching with the Si substrate 1, has a flat interface with the Si substrate 1, has low electric resistance, and has good characteristics as an electrode.

In the present invention, by using Ti, Hf, Zr or the like having a high reducing ability as the first metal to be removed after the heat treatment, oxides such as Si and Ge remaining on the surface of the semiconductor substrate after the ion implantation are changed to C49. Phase TiSi ₂ layer 8 and C
A process in which 54-phase TiSi ₂ layer 9 can be absorbed and effectively removed, and in the silicidation reaction of Ti, Hf, Zr, etc., semiconductor atoms such as Si, Ge, etc. diffuse to the first metal side. Since the reaction is rate-controlled, a large number of atomic vacancies are generated at the interface between the first metal and the semiconductor substrate, and interstitial semiconductor atoms are trapped in the atomic vacancies, so that an interstitial dislocation loop is effective. Can be eroded and eliminated.

[0027]

Embodiments of the present invention will be described below. (First Embodiment) FIGS. 2, 3, 4, and 5 are process explanatory diagrams of an electrode forming method on a semiconductor substrate of the first embodiment.
(A)-(M) has shown each process. In these figures, 1 is a Si substrate, 2 is a Si ₃ N ₄ stripe mask, 3 is a LOCOS oxide film, 4 is a protective film, 5 is As, 6
Is an n ⁺ region, 7 is a Ti film, 8 is C49 phase TiSi
₂ layers, 9 is a C54 phase TiSi ₂ layer, 10 is a Co film, 1
Reference numeral 1 is an unreacted CoSi ₂ layer, and 12 is a CoSi ₂ layer.

A method of forming an electrode on a semiconductor substrate, which is applied to the case of forming the CoSi ₂ electrode on the n ⁺ region of the Si substrate according to the present invention, will be described with reference to the process explanatory drawings.

First Step (See FIG. 2A) (001) After forming a Si ₃ N ₄ film on the entire surface of the Si substrate 1 and patterning the Si ₃ N ₄ film, a Si ₃ N ₄ stripe mask 2 is formed. , This Si ₃ N ₄ stripe mask 2
Is used as an anti-oxidation mask to wet-oxidize the surface of the Si substrate. After that, the Si ₃ N ₄ stripe mask 2 is removed and a LOCOS oxide film 3 is formed.

Second step (see FIG. 2 (B)) After forming a thin protective film 4 such as SiO ₂ on the entire surface thereof, ions of As 5 which is an n-type impurity is ion-implanted through the protective film 4. In this case, the acceleration voltage of As ⁺ ions is set to 3
The dose is (2-5) × 10 ¹⁵ / cm ^-2 with 0 keV.
And

Third step (see FIG. 2C) Rapid thermal annealing (RTA) is performed at 1000 ° C. for 30 seconds to activate the implanted impurities (As) to form the n ⁺ region 6.

Fourth step (see FIG. 2D) The thin protective film 4 such as SiO ₂ is removed with an HF solution.

Fifth step (see FIG. 3E) Si substrate 1 on which LOCOS oxide film 3 and n ⁺ region 6 are formed
Is introduced into the RF sputtering apparatus to deposit the Ti film 7.

Step 6 (see FIG. 3F) In Ar atmosphere, the first stage heat treatment is performed at 700 ° C. for 30 seconds to react the Ti film 7 with the Si substrate 1 and stabilize in this temperature range. Forming a C49 phase TiSi ₂ layer 8.
The C49 phase TiSi ₂ layer 8 has a high resistance of about 65 μΩcm and a grain size of 0.05 to 0.2 μm.
And small.

Seventh step (see FIG. 3G) The unreacted Ti film 7 is formed by, for example, NH ₄ OH + H ₂ O ₂ + H.
It is removed by chemical etching with a mixed solution of ₂ O or the like.

Eighth step (see FIG. 3H) In the Ar atmosphere, the second stage heat treatment by RTA is performed at 850 ° C. for 30 seconds to further react the TiSi ₂ layer 8 and the Si substrate 1 with each other. C54 phase T stable in temperature range
The iSi ₂ layer 9 is formed. The C54 phase TiSi ₂ layer 9 has a low resistance of about 5 μΩcm and a large grain size of 2 μm or more.

Ninth Step (see FIG. 4I) The C54 phase TiSi ₂ layer 9 is removed by chemical etching using, for example, a dilute HF aqueous solution. in this way,
When the C54 phase TiSi ₂ layer 9 is chemically etched using a dilute HF solution, H in the dilute HF solution terminates the dangling bonds of the Si substrate 1 and stabilizes the effect.

Step 10 (see FIG. 4 (J)) A Co film 10 as a second metal is formed by sputtering on the entire surface of the Si substrate 1 after removing the C54 phase TiSi ₂ layer 9.

Eleventh step (see FIG. 4 (K)) By performing RTA at 650 ° C. for 30 seconds, Co
The film 10 and the Si substrate 1 are reacted to form an unreacted CoSi ₂ layer 11 containing Co ₂ Si, CoSi, etc. only in the region inside the LOCOS oxide film 3.

Twelfth step (see FIG. 5L) The Co film 10 remaining on the LOCOS oxide film 3 is removed by chemical etching using, for example, H ₂ SO ₄ + H ₂ O ₂ .

Step 13 (see FIG. 5M) CoS is performed by performing RTA at 750 ° C. for 30 seconds.
The i ₂ layer 12 is finally formed. As a result, a low resistance and uniform electrode can be obtained, and the problem of junction leakage due to defects can be solved.

(Second Embodiment) This embodiment is characterized in that all the steps of the first embodiment are carried out consistently in a vacuum apparatus. In the vacuum device used in this example,
It is possible to perform sputtering of a metal film on a Si substrate, selective dry etching of silicide, and heating of a wafer.

According to this embodiment, it is possible to avoid exposing the Si substrate to the atmosphere during the whole process.
Oxidation of the surface of the i substrate can be prevented, and the manufacturing cost can be reduced by omitting the step of transferring the Si substrate between the CVD device, the etching device, the sputtering device, the heating device, and the like.

(Third Embodiment) In this embodiment, Zr is used as the first metal for silicidation, and then Zr silicide is removed to form a CoSi ₂ layer in the same manner as in the first embodiment. The same effect as the example was obtained.

Fourth Embodiment In this embodiment, Hf was used as the first metal for silicidation, and then the Hf silicide was removed to form a CoSi ₂ layer in the same manner as in the first embodiment. The same effect as the example was obtained.

(Fifth Embodiment) In this embodiment, V, Nb, Ta, C, Mo, W or Y is used as the second metal.
Was used, the same effect as in the first embodiment was obtained.

[0047]

As described above, according to the present invention,
By using Ti, Zr or Hf having a high reducing ability as the first metal, the oxide remaining on the substrate surface can be effectively removed in the step after ion implantation, and the electric resistance of the electrode within the wafer surface can be effectively removed. This has the effect of significantly improving the uniformity.

Further, in the silicidation reaction of Ti, Zr or Hf, the reaction is rate-determined in the process of diffusion of semiconductor atoms such as Si to the metal side, and a large amount of atomic voids generated in the process of diffusion of semiconductor atoms to the metal side. Since the holes capture the interstitial semiconductor atoms, the interstitial dislocation loops can be effectively eroded and eliminated, and as a result, the leak current at the source junction and the drain junction can be significantly reduced. Produce an effect. Due to these effects, the present invention can improve the reliability of the electrode and significantly improve the manufacturing yield.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of an electrode forming method on a semiconductor substrate according to the present invention, in which (A) to (D) show respective steps.

FIG. 2 is a process explanatory view (1) of the electrode forming method on the semiconductor substrate of the first embodiment, and (A) to (D) show each process.

FIG. 3 is a process explanatory view (2) of the electrode forming method on the semiconductor substrate of the first embodiment, and (E) to (H) show each process.

FIG. 4 is a process explanatory view (3) of the electrode forming method on the semiconductor substrate of the first embodiment, and (I) to (K) show each process.

FIG. 5 is a process explanatory diagram (4) of the electrode forming method on the semiconductor substrate of the first embodiment, and (L) and (M) show each process.

FIG. 6 is a schematic explanatory diagram (1) of a conventional method for forming an electrode on a semiconductor substrate, in which (A) to (D) show respective steps.

FIG. 7 is a schematic explanatory view (2) of a conventional method for forming an electrode on a semiconductor substrate, in which (E) to (H) show respective steps.

[Explanation of symbols]

1 Si substrate 2 Si ₃ N ₄ stripe mask 3 LOCOS oxide film 4 protective film 5 As 6 n ⁺ region 7 Ti film 8 C40 phase TiSi ₂ layer 9 C54 phase TiSi ₂ layer 10 Co film 11 unreacted CoSi ₂ layer 12 CoSi ₂ layer

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/316 29/43 8418-4M H01L 21/94 A 29/46 T

Claims (5)

[Claims] 1. A step of depositing a first metal having a reducing ability on a semiconductor substrate, a step of forming a reaction product of the semiconductor substrate and the first metal by heat treatment, and the semiconductor substrate. A step of removing a reaction product of the first metal, and a step of removing a reaction product of the semiconductor substrate and the first metal of the semiconductor substrate, and having a reducing ability lower than that of the first metal. A method of forming an electrode on a semiconductor substrate, comprising: a step of depositing a second metal; and a step of forming a reaction product of the semiconductor substrate and the second metal by heat treatment. 2. The method for forming an electrode on a semiconductor substrate according to claim 1, wherein all the steps are performed in a vacuum apparatus. 3. Si, Ge or Si as a semiconductor substrate
3. The method for forming an electrode on a semiconductor substrate according to claim 1, wherein a mixed crystal of Ge and Ge is used. 4. Ti, Zr or Hf as the first metal
The method for forming an electrode on a semiconductor substrate according to claim 1, wherein the electrode is used. 5. Co, V, Nb, T as the second metal
The method for forming an electrode on a semiconductor substrate according to any one of claims 1 to 5, wherein a, C, Mo, W or Y is used.