JPH0810978Y2 - Status signal reading circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial application field> The present invention relates to a status signal reading circuit used for an input circuit of a sequencer, and more specifically, a circuit for recognizing a status signal such as a contact signal. The present invention also relates to a status signal reading circuit capable of recognizing a status signal that changes in a short time.

<Prior Art> FIG. 3 is a block diagram showing an example of a conventional status signal reading circuit of this type. In the figure, reference numeral 1 is a filter for inputting a read status signal IN, and a filter for removing a single pulse contained therein, and 2 is a read signal RE applied with a signal from the filter 1 at a constant scan cycle.
It is a gate to take in by AD.

Filter 1 includes flip-flops 11 to 13 and gates 14 and 15
It is configured to remove a single pulse that does not correspond to the status signal.

FIG. 4 is a time chart showing the operation.
(B) shows a status signal IN including a single pulse applied to the D terminal of the flip-flop 11, and (d) shows a clock pulse CP applied to each flip-flop 11, 12. The gate 14 takes the logic of the Q output from each flip-flop 11, 12 and sets the flip-flop 13 by its output. Further, the gate 15 takes the logic of the <Q> output (the sign of <> indicates an inverted output) IN 'from each of the flip-flops 11 and 12, and resets the flip-flop 13 by its output.

As a result, a single pulse having a short width is removed as shown in (c) and this is output to the gate 2. The gate 2 reads the status signal OUT as shown in (e) by the read signal READ applied at a constant scan cycle as shown in (a).

<Problems to be Solved by the Invention> According to the conventional circuit configured as described above, the status signal having a time width smaller than the scan cycle T of the read signal READ as shown in (c) of FIG. As shown in part (e), there is a problem that it disappears and the change in status cannot be recognized.

Inability to recognize a status signal having a time width smaller than the scan cycle T requires that the sequencer, which is the main controller of the production line, perform detailed control in order to improve productivity in recent years, increasing the number of program steps and scan cycle. This is a big problem when considering that the time width (pulse width) of the status of the signal from the sensor (contact) tends to become shorter.

The present invention has been made in view of such a point, and a status of a short time width that cannot be recognized until now, such as "1,0,1" completed during a scan cycle of a read signal. An object of the present invention is to provide a status signal reading circuit that can surely recognize a signal.

<Means for Solving the Problems> In the present invention for achieving such an object, a filter for removing a single pulse contained in an input signal and a signal from this filter are applied at a predetermined scan cycle. In a status signal reading circuit having a gate for reading by a read signal, a signal from the filter is input, latch means for latching the rising or falling thereof, and a read signal applied in the scan cycle are input,
A reset signal output means for outputting a reset signal synchronized with the read signal at a timing delayed to the reset terminal of the latch means, an output of the filter and an output from the latch means are input and the output is applied to the gate. It is configured with an OR gate.

<Operation> When the status of the signal output from the filter changes to rising or falling during the scan cycle, the latch means latches it and holds it for the scan cycle.

The ORATE takes the OR of both the signal from the latch means and the filter, and the gate at the final stage outputs the output of the OR gate by the read signal.

<Embodiment> An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a configuration block diagram showing an embodiment of the present invention. In the figure, the same components as those of the circuit of FIG. 3 are designated by the same reference numerals and the description thereof will be omitted.

In the figure, 3 is a latch means for inputting the signal IN1 from the filter 1 and latching its rising or falling, and a flip-flop is used, and the signal from the filter 1 is applied to the clock terminal. Reference numeral 4 is a reset signal output means for inputting a read signal READ applied in a scan cycle and outputting a reset signal <RESET> which is synchronized with the falling timing of the read signal. The reset signal generated here is the latch means 3 Applied to the reset terminal of. Reference numeral 5 is an OR gate for inputting the output IN1 of the filter 1 and the output OUT1 from the latch means 3 and applying the output to the gate 2.

The operation of the circuit thus configured will be described below.

FIG. 2 is a time chart showing the operation of this circuit. Input signal IN shown in (b) applied to filter 1
, The single pulse is removed, and the status signal IN1 as shown in (c) is output from the output terminal (Q output of the flip-flop 13). This operation is similar to that of FIG.

The latch means (flip-flop) 3 receives the status signal IN1 and latches the rising edge indicated by (1) as shown in (e).

The reset signal output means 4 receives a read signal READ that arrives at a constant scan period T as shown in (a), and shows a reset signal <RESET> which is at a low level for a certain time at its trailing edge, in (g). To output. Then, this reset signal <RESET> is applied to the reset terminal <R> of the latch means 3. The information held in the latch means 3 is reset by receiving this reset signal. That is, this reset operation is performed immediately after the read signal READ is applied to the gate 2 and the reading is completed.

The OR gate 5 is the output OUT1 of the latch means 3 and the filter 1.
Takes both ORs of the status signal IN1 from and outputs it to the gate 2 at the final stage. The gate 2 outputs the output of the OR gate 5 by the read signal READ. That is, gate 2
When the read signal READ is applied to the OR gate 5, if there is a rising edge as shown in (c) during the scan cycle T, the <Q> output of the latch means 3 becomes as shown in (f), and the OR gate 5 And is output via the gate 2. Also (c)
Similarly, the status signal indicated by (3) is output via the OR gate 5 and the gate 2 when the read signal is applied.

<Effect of the Invention> As described in detail above, the present invention is configured so that the latch means holds the status change generated during the read scan cycle, which cannot be recognized by the conventional circuit. It is also possible to recognize and read an impulse status signal having a short time width. Therefore, according to the present invention, it is possible to provide a status signal reading circuit capable of handling a sensor signal having a short pulse width.

[Brief description of drawings]

 FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the circuit shown in FIG. 1, FIG. 3 is a block diagram showing an example of the conventional circuit, and FIG. 4 is its operation. 2 is a time chart showing. 1 ... Filter 2 ... Gate 3 ... Latch means 4 ... Reset signal output means 5 ... OR gate

Claims (1)

[Scope of utility model registration request] 1. A filter (1) for removing a single pulse contained in an input signal, and a gate (2) for reading a signal from the filter by a read signal applied at a predetermined scan cycle. In a status signal reading circuit, a signal from the filter (1) is input and a latch means (3) that latches the rising or falling of the signal is input, and a reading signal applied in the scan cycle is input to the reading signal. A reset signal output means (4) for outputting a reset signal synchronized with the delayed timing to the reset terminal of the latch means (3), an output of the filter and an output from the latch means are inputted and the output thereof is supplied to the gate ( A status signal reading circuit provided with an OR gate (5) to be applied to 2).