JPH08107150A - Gate array automatic pin disposing device - Google Patents

Abstract

PURPOSE: To accurately prevent the layout patterns of buffers from overlapping each other by a method wherein at least one of layout elements is so modified as to eliminate overlapping if the layout patterns of the buffers happen to overlap each other. CONSTITUTION: When the data of a pin arrangement and working buffers designated by a designer happen to make the layout patterns of buffers like buffers 2 and 3 overlap each other, data that a buffer 5 small in layout pattern region is required to be adopted in place of the buffer 5 taking a layout pattern region into consideration so as to eliminate overlapping is provided. When an unused region 4 is present, data that an overlapping buffer is capable of being moved is provided. Or, taking the unused region 4 into consideration, data that the buffer 2 can be replaced with another buffer larger in output current and layout pattern region area than the buffer 2 is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a gate array automatic pin placement device, and more particularly, a gate array design, when a designer decides the pin placement, provides placement information satisfying various restrictions or conditions regarding the pin placement. The present invention relates to a gate array automatic pin arrangement setting support device.

[0002]

2. Description of the Related Art In a gate array design, when deciding the pin arrangement, the layout pattern size differs depending on the buffer used, so it is confirmed whether it can be arranged on the chip master or whether the number of simultaneous changes in the output buffer is satisfied. It is necessary to confirm whether. The conventional device performs only this confirmation. With such a device, it was possible to obtain the minimum information that the pin layout had to be changed, but there was no information on how to change the pin arrangement, and pins that met various restrictions or conditions were For the placement, it was not possible to obtain more efficient pin placement information.

[0003]

SUMMARY OF THE INVENTION A first object of the present invention is to provide an apparatus for providing information capable of appropriately eliminating the overlap of layout patterns among a plurality of buffers.

A second object of the present invention is to provide an apparatus for providing information that can more accurately eliminate the overlap of layout patterns among a plurality of input / output buffers.

A third aspect of the present invention has an object to provide an apparatus which provides information capable of more appropriately eliminating the overlap of layout patterns among a plurality of input / output buffers.

A fourth object of the present invention is to provide an apparatus for providing information capable of accurately avoiding the duplication of layout patterns among a plurality of input / output buffers.

A fifth aspect of the present invention has an object of providing an apparatus for providing information capable of more accurately avoiding overlapping of layout patterns among a plurality of input / output buffers.

A sixth object of the present invention is to provide an apparatus for providing information capable of more accurately avoiding the overlap of layout patterns among a plurality of input / output buffers.

A seventh object of the present invention is to provide an apparatus for providing information capable of more accurately eliminating or avoiding overlap of layout patterns among a plurality of input / output buffers.

An eighth object of the present invention is to obtain an apparatus for providing accurate information for lowering the sum of noise parameter values of an output buffer which changes simultaneously with a power supply buffer and a ground buffer.

A ninth object of the present invention is to obtain an apparatus for providing more accurate information for reducing the sum of noise parameter values of an output buffer having a noise-related relationship with a power supply buffer and a ground buffer.

A tenth aspect of the present invention aims to obtain an apparatus for providing more accurate information for reducing the sum of noise parameter values of output buffers associated with a power supply buffer and a ground buffer.

An eleventh aspect of the invention is to provide an apparatus which provides more accurate information for reducing the sum of noise parameter values of an output buffer having a noise-related relationship with a power supply buffer and a ground buffer.

A twelfth aspect of the invention is to obtain a device capable of effectively utilizing the margin up to the upper limit of the sum of the noise parameter values of the output buffer associated with the power supply buffer and the ground buffer.

A thirteenth aspect of the invention is to provide a device capable of more effectively utilizing the margin up to the upper limit of the sum of the noise parameter values of the output buffers associated with the power supply buffer and the ground buffer.

It is an object of the fourteenth invention to obtain an apparatus which provides more accurate information for lowering the sum of the noise parameter values of the output buffer in consideration of the existence of the additional power supply buffer.

A fifteenth aspect of the invention is to obtain an apparatus for providing more accurate information for lowering the sum of noise parameter values of an output buffer having a noise-related relationship with a power supply buffer and an additional ground buffer.

A sixteenth aspect of the present invention is to provide an apparatus capable of obtaining a netlist file having accurate contents.

A seventeenth aspect of the invention is to provide an apparatus capable of obtaining a pin arrangement information file having an accurate content.

[0020]

According to a first aspect of the present invention, when the layout patterns of buffers are duplicated on the layout, information is provided to change at least one of the layout elements so as to eliminate the duplication.

In the second invention, when the layout patterns of the input / output buffers overlap in the layout, information for changing the size of at least one of the input / output buffers is provided so as to eliminate the overlap.

In the third invention, when the layout patterns of the input / output buffers overlap in the layout, information for changing at least one layout arrangement of the input / output buffers is provided so as to eliminate the overlap.

In the fourth aspect of the invention, when the layout patterns of the input / output buffers overlap, if there are unused pins and areas for arranging the input / output buffers on the layout, those unused pins and areas are not used. Provide information that the exists and is available.

According to the fifth aspect of the invention, when the layout patterns of the input / output buffers overlap, if there are unused pins and areas for arranging the input / output buffers on the layout, the overlapping input / outputs are used. Information is provided that at least one of the buffers can be placed in the unused area.

In the sixth invention, when there is an unused pin and area for arranging the input / output buffer on the layout, information that at least one size of the input / output buffer can be increased is provided. To do.

In the seventh aspect of the present invention, the presence or absence of the overlap with the power supply buffer or the ground buffer is also taken into consideration when determining the overlap or use of the layout pattern of the input / output buffer.

In the eighth aspect of the present invention, the upper limit of the sum of the noise parameter values of the output buffer is provided with change information for lowering the sum of the noise parameters when the pin arrangement of the user exceeds the upper limit value.

In the ninth invention, when a power supply buffer, a ground buffer, and an output buffer having a noise relationship with these are arranged on the gate array chip, the upper limit of the sum of the noise parameter values of the output buffer is: When the user's pinout exceeds this upper limit, the double output buffer is converted to a single output buffer to reduce the sum of noise parameters, and information is provided to prevent the upper limit from being exceeded.

In the tenth aspect of the present invention, by moving the output buffer, the sum of the noise parameters is lowered so that the upper limit value is not exceeded.

In the eleventh invention, for the unused area,
By arranging the power supply or the ground, the sum of the noise parameters of the output buffer is lowered and the information that the upper limit value is satisfied is provided.

In the twelfth aspect of the invention, when the power supply buffer, the ground buffer, and the output buffer having a noise relationship with them are arranged on the gate array chip, the sum of the noise parameter values of the output buffer is higher than the upper limit value. If it is small and there is a margin up to the upper limit value, information that the change can be made within the range satisfying the upper limit value is provided.

In a thirteenth aspect of the invention, when a master fixed fixed power supply buffer of the same power supply system, a ground buffer, and an output buffer having a noise relationship with these are arranged on the gate array chip, noise parameters of the output buffer are arranged. When the sum of the values is smaller than the upper limit value and there is a margin to the upper limit value, the information that the driving capability of the signal buffer can be increased within the range satisfying the upper limit value is provided.

In the fourteenth invention, the information is provided in consideration of the existence of the additional power source.

In the fifteenth invention, information is provided in consideration of the existence of the additional ground buffer.

In the sixteenth invention, the netlist file in consideration of the changed contents is edited and output in accordance with the buffer conversion and the pin arrangement change.

In the seventeenth aspect, the pin arrangement information file in consideration of the contents of the change is edited and output according to the conversion of the buffer and the change of the pin arrangement.

[0037]

In the first aspect of the invention, when the layout patterns of the input / output buffers overlap, information for changing at least one of the layout elements is provided so as to eliminate the overlap.

In the second invention, when the layout patterns of the input / output buffers overlap, information for changing the size of at least one of the input / output buffers is provided so as to eliminate the overlap.

In the third invention, when the layout patterns of the input / output buffers overlap, information for changing the layout arrangement of at least one of the input / output buffers is provided so as to eliminate the overlap.

In the fourth invention, when the layout patterns of the input / output buffers overlap, if there are unused pins and areas for arranging the input / output buffers on the layout, they are not used. Provide information that something exists and is available.

In the fifth aspect of the present invention, when the layout patterns of the input / output buffers overlap, if there are unused pins and areas for arranging the input / output buffers on the layout, the overlapping input patterns are used. Information is provided that at least one of the output buffers can be placed in the unused area.

In the sixth aspect of the present invention, when there are unused pins and areas for arranging the input / output buffers on the layout, information indicating that at least one size of the input / output buffers can be increased is provided. provide.

In the seventh invention, the presence or absence of the overlap with the fixed power supply or the ground buffer is taken into consideration when determining the overlap or use of the layout pattern of the input / output buffer.

According to the eighth aspect of the present invention, the upper limit of the sum of the noise parameter values of the output buffer is provided with the change information for lowering the sum of the noise parameters when the pin arrangement of the user exceeds the upper limit value.

In the ninth invention, with respect to the upper limit of the sum of the noise parameter values of the output buffer, when the user's pin arrangement exceeds this upper limit value, the double output buffer outputs a single output in order to lower the sum of the noise parameters. It provides information to convert to a buffer so that the upper limit is not exceeded.

In the tenth invention, the sum of noise parameters is lowered by moving the output buffer,
Provide information to the effect that the upper limit will not be exceeded.

In the eleventh invention, by arranging the power supply buffer or the ground buffer in the unused area, information that the sum of the noise parameters of the output buffer is lowered and the upper limit value is satisfied is provided.

In the twelfth aspect, when the sum of the noise parameter values of the output buffer is smaller than the upper limit value and there is a margin up to the upper limit value, information is provided that the change can be made within the range satisfying the upper limit value. It

In the thirteenth aspect, when the sum of the noise parameter values of the output buffer is smaller than the upper limit value and there is a margin up to the upper limit value, it is possible to increase the driving capability of the output buffer within a range satisfying the upper limit value. Information is provided to that effect.

In the fourteenth invention, when the sum of the noise parameter values of the output buffer exceeds the upper limit value, the sum of the noise parameters is lowered to satisfy the upper limit value in consideration of the existence of the additional power supply buffer. Information will be provided.

In the fifteenth aspect of the invention, when the sum of the noise parameter values of the output buffer exceeds the upper limit value, the presence of the additional ground buffer is taken into consideration, and the sum of the noise parameters is lowered to satisfy the upper limit value. Information will be provided.

In the sixteenth invention, the netlist file in consideration of the changed contents is edited and output according to the conversion of the buffer and the change of the pin arrangement.

In the seventeenth aspect, the pin arrangement information file is edited and output in consideration of the contents of the change in accordance with the conversion of the buffer and the change of the pin arrangement.

[0054]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is an input / output buffer arrangement area on the gate array chip, 2 is an input / output buffer, and 3 is an input current that has a larger output current than the buffer 2 and has a layout pattern area three times as large as the buffer of the buffer 2. The output buffers 4 are unused areas. P is a pin corresponding to each buffer.

When the pin layout and the information on the used buffer designated by the designer are duplicated in the respective layout pattern areas like the buffer 2 and the buffer 3 in FIG. 1,
The layout pattern area is taken into consideration so that the buffer 3 does not overlap, and the information that the buffer 5 having a small layout pattern area in FIG. This provides information to change the size of the buffer, which is one of the layout elements.

Example 2. In addition, when there is an unused area 4 in FIG. 1, as shown in FIG. 3, information is provided that the overlapping buffers can be moved. This provides information to the effect that the layout layout of the buffer, which is one of the layout elements, will be changed. At this time, regarding the change of the buffer and the movement of the pin arrangement, the overlap with the gate array chip fixed power supply and / or the ground buffer is considered.

Example 3. Next, considering the unused area 4 of FIG. 2, provision of information that the buffer 2 of FIG. 2 can be changed like the buffer 6 of FIG. 4 having a larger output current and a larger layout pattern area than the buffer 2. I do.

Example 4. Next, in FIG. 5, 7 is a buffer arrangement area on the gate array chip, and 8 is an input / output buffer. Reference numerals 9 and 10 denote buffers having a larger output current than the buffer 8 and a larger noise parameter than that of the buffer 8. Reference numeral 11 denotes a gate array chip fixed power supply buffer (hereinafter abbreviated as primary VDD). Reference numeral 12 denotes a gate array chip fixed ground. Buffer (hereinafter primary G
(Abbreviated as ND), 7 indicates an unused area.

At this time, the noise of the buffer arranged in the area sandwiched between the primary VDD 11 and the primary GND 12 is simultaneously changed in association with the primary VDD 11 and the primary GND 12, and the noise is changed for each series of gate array chip masters. An upper limit for the sum of the parameter values is set.

When the sum of the noise parameters of the buffers 8, 9 and 10 in FIG. 5 exceeds the upper limit, the sum of the noise parameters is taken into consideration, and the buffer 9 has a smaller noise parameter than the buffer 9 as shown in FIG. It is converted into 13 and the information to prevent the upper limit value from being exceeded is provided.

Example 5. Further, as shown in FIG. 7, by moving the buffer 8 to the outside between the primary VDD 11 and the primary GND 12, the value of the sum of the noise parameters between the primary VDD 11 and the primary GND 12 is reduced so that the upper limit value is not exceeded. Will be provided.

Example 6. Further, as shown in FIG. 8, by arranging an additional power supply buffer (hereinafter abbreviated as additional VDD) or an additional ground buffer (hereinafter abbreviated as additional GND) 16 in the unused area 7 of FIG. 5, the primary VDD and the primary GND The sum of the noise parameters of the buffer sandwiched between is reduced, and information is provided so that the upper limit value is not exceeded. Here, 15 indicates a primary VDD, and 17, 18, and 19 indicate buffers. The primary GND 20 is arranged as shown in FIG.

Example 7. Next, in FIG. 10, 33 is an unused area, 22, 23, 24 are buffers, 21 is a primary VDD, and 25 is an additional GND.

When the sum of the noise parameter values of the buffers 22, 23, 24 arranged between the primary VDD 21 and the additional GND 25 exceeds the upper limit value, the arrangement of the additional GND 25 is changed to the unused area 33 as shown in FIG. By doing so, information is provided so that the sum of the noise parameter values of the buffer arranged between the primary VDD 21 and the additional GND 26 is lowered and the upper limit value is not exceeded.

Example 8. Next, in FIG. 12, 27 is a primary VDD or additional VDD, 28 is a primary GND or additional GND, and 34 is an unused area. If the sum of the noise parameter values of the buffers 29, 30 and 31 arranged between the primary VDD (or additional VDD) 27 and the primary GND (or additional GND) 28 has a margin with respect to the upper limit value, the margin value, Considering the size of the unused area 34 and the like, the buffer 31 of FIG.
The buffer 32 having a large noise parameter value in FIG.
Provide information that can be changed to.

The conversion of the buffer and the change of the pin arrangement described above can be carried out not only by taking the measures individually but also by using them in combination.

Example 9. Further, when the above-mentioned buffer conversion and pin arrangement change are performed, it is possible to output the change information of the used buffer of the netlist file and the changed netlist file in accordance with the change and change contents.

Example 10. In addition, the pin layout file created by the designer can be edited to output the modified pin layout file.

As described above, according to the embodiment of the present invention, there are various restrictions in determining the gate array pin arrangement.
Since it is configured to check the conditions and output the conversion / change content information, there is an effect that the pin arrangement can be efficiently determined.

[0070]

According to the first aspect of the present invention, it is possible to obtain an apparatus for providing information capable of accurately eliminating the overlap of layout patterns among a plurality of buffers.

According to the second aspect of the present invention, it is possible to obtain an apparatus that provides information that can more accurately eliminate the overlap of layout patterns among a plurality of input / output buffers.

According to the third aspect of the present invention, it is possible to obtain an apparatus that provides information that can more appropriately eliminate the overlapping of layout patterns between a plurality of input / output buffers.

According to the fourth aspect of the present invention, it is possible to obtain an apparatus that provides information that can avoid duplication of layout patterns among a plurality of input / output buffers.

According to the fifth aspect of the present invention, it is possible to obtain an apparatus for providing information that can more accurately avoid the duplication of layout patterns among a plurality of input / output buffers.

According to the sixth aspect of the present invention, it is possible to obtain an apparatus for providing information that can more accurately avoid the duplication of layout patterns among a plurality of input / output buffers.

According to the seventh aspect of the present invention, it is possible to obtain an apparatus for providing information capable of more accurately eliminating or avoiding the overlap of layout patterns among a plurality of input / output buffers.

According to the eighth aspect of the present invention, it is possible to obtain a device that provides accurate information for reducing the sum of the noise parameter values of the output buffer that changes simultaneously with the power supply buffer and the ground buffer.

According to the ninth invention, it is possible to obtain an apparatus for providing more accurate information for lowering the sum of the noise parameter values of the output buffer having a noise-related relationship with the power supply buffer and the ground buffer.

According to the tenth aspect of the present invention, it is possible to obtain a device that provides more accurate information for reducing the sum of the noise parameter values of the output buffers associated with the power supply buffer and the ground buffer.

According to the eleventh aspect of the present invention, it is possible to obtain a device that provides more accurate information for lowering the sum of the noise parameter values of the output buffers that are associated with the power supply buffer and the ground buffer regarding noise.

According to the twelfth aspect of the invention, it is possible to obtain a device which can effectively use the margin up to the upper limit of the sum of the noise parameter values of the output buffers associated with the power supply buffer and the ground buffer.

According to the thirteenth aspect of the present invention, it is possible to obtain a device that can more effectively use the margin up to the upper limit value of the sum of the noise parameter values of the output buffers associated with the power supply buffer and the ground buffer.

According to the fourteenth invention, it is possible to obtain an apparatus for providing more accurate information for lowering the sum of the noise parameter values of the output buffer in consideration of the existence of the additional power supply buffer.

According to the fifteenth aspect of the present invention, it is possible to obtain a device that provides more accurate information for lowering the sum of the noise parameter values of the output buffer having a noise relation with the power supply buffer and the additional ground buffer.

According to the sixteenth invention, it is possible to provide an apparatus capable of obtaining a netlist file having accurate contents.

According to the seventeenth aspect of the present invention, it is an object of the present invention to provide an apparatus capable of obtaining a pin arrangement information file having accurate contents.

[Brief description of drawings]

FIG. 1 is a perspective view of a buffer arrangement region on a gate array chip showing an embodiment of the present invention.

FIG. 2 is a perspective view of a buffer arrangement region on a gate array chip showing another embodiment of the present invention.

FIG. 3 is a perspective view of a buffer arrangement area on a gate array chip showing still another embodiment of the present invention.

FIG. 4 is a perspective view of a buffer arrangement region on a gate array chip showing still another embodiment of the present invention.

FIG. 5 is a perspective view of a buffer arrangement region on a gate array chip showing still another embodiment of the present invention.

FIG. 6 is a perspective view of a buffer arrangement region on a gate array chip showing still another embodiment of the present invention.

FIG. 7 is a perspective view of a buffer arrangement area on a gate array chip showing still another embodiment of the present invention.

FIG. 8 is a perspective view of a buffer arrangement region on a gate array chip showing still another embodiment of the present invention.

FIG. 9 is a perspective view of a buffer arrangement area on a gate array chip showing still another embodiment of the present invention.

FIG. 10 is a perspective view of a buffer arrangement region on a gate array chip showing still another embodiment of the present invention.

FIG. 11 is a perspective view of a buffer arrangement area on a gate array chip showing still another embodiment of the present invention.

FIG. 12 is a perspective view of a buffer arrangement area on a gate array chip showing still another embodiment of the present invention.

FIG. 13 is a perspective view of a buffer arrangement region on a gate array chip showing still another embodiment of the present invention.

[Explanation of symbols]

1 buffer arrangement area on gate array, 2-3 input / output buffer, 4 unused area, 5-6 input / output buffer, 7 unused area, 8-10 input / output buffer, 11
Gate array chip fixed power supply buffer (Primary V
DD), 12 gate array chip fixed ground buffer (primary GND), 19 unused area, 21 gate array chip fixed power buffer (primary VD)
D) 22 to 24 input / output buffer, 25 additional ground buffer (additional GND), 27 primary VDD or additional VDD, 28 primary GND or additional GND, 29 to 32 input / output buffer, 34 unused area.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 27/04 21/822 H01L 21/82 MC 27/04 E

Claims (17)

[Claims] 1. In pin arrangement in a gate array design, a plurality of buffers each having a predetermined layout pattern area are allocated to a buffer arrangement area on a gate array chip, and when the pin arrangement is performed, the buffers on the layout are A gate array automatic pin placement device, which provides information for changing at least one of the layout elements so as to eliminate the overlap when the layout patterns overlap. 2. In the pin arrangement in the gate array design, a plurality of input / output buffers each having a predetermined layout pattern area are allocated to the buffer arrangement area on the gate array chip, and when the pin arrangement is performed, the layout is made. When the layout patterns of the input / output buffers overlap, information for changing the size of at least one of the input / output buffers is provided so as to eliminate the overlap. 3. In the pin arrangement in the gate array design, a plurality of input / output buffers each having a predetermined layout pattern area are allocated to the buffer arrangement area on the gate array chip, and when the pin arrangement is performed, the layout is performed. A gate array automatic pin placement device, which provides information for changing layout layout of at least one of the input / output buffers when the layout patterns of the input / output buffers are overlapped. 4. In a pin arrangement in a gate array design, a plurality of input / output buffers each having a predetermined layout pattern area are allocated to a buffer arrangement area on a gate array chip, and when the pin arrangement is performed, an input / output buffer is provided. If the layout patterns of the above are duplicated, and if there are unused pins and areas for arranging the I / O buffers on the layout, provide information that there are unused pins and areas available for these. A gate array automatic pin placement device characterized by: 5. In a pin arrangement in a gate array design, a plurality of input / output buffers each having a predetermined layout pattern area are allocated to a buffer arrangement area on a gate array chip, and when the pin arrangement is performed, an input / output buffer is provided. If the layout patterns overlap with each other, and there are unused pins and areas for arranging the input / output buffers on the layout, at least one of the overlapping input / output buffers is arranged in the unused area. A gate array automatic pin placement device characterized by providing information that it is possible. 6. In the pin arrangement in the gate array design, a plurality of input / output buffers each having a predetermined layout pattern area are allocated to the buffer arrangement area on the gate array chip, and when the pin arrangement is performed, a layout is performed. When there is an unused pin and area for arranging the input / output buffer, information for increasing the size of at least one of the input / output buffers is provided. . 7. The method according to claim 1, wherein in determining the duplication or utilization of the layout pattern of the input / output buffer, the presence / absence of duplication with the power supply buffer or the ground buffer is also taken into consideration. Gate array automatic pin placement device. 8. In a pin arrangement in a gate array design, when a power supply buffer, a ground buffer, and an output buffer related to these with respect to noise are arranged on a gate array chip, the sum of noise parameter values of the output buffers. Regarding the upper limit of the above, when the user's pin arrangement exceeds this upper limit value, a gate array automatic pin arrangement device is provided which provides change information for lowering the sum of noise parameters. 9. In a pin arrangement in a gate array design, when a power supply buffer, a ground buffer, and an output buffer related to these with respect to noise are arranged on a gate array chip, the sum of noise parameter values of the output buffers. Regarding the upper limit of the above, when the user's pin layout exceeds this upper limit value, in order to reduce the sum of noise parameters, the double output buffer is converted to a single output buffer and information is provided so as not to exceed the upper limit value. A gate array automatic pin placement device characterized by the above. 10. The information for reducing the sum of noise parameters so that the upper limit value is not exceeded is provided by moving the output buffer.
Gate array automatic pin placement device as described in. 11. An automatic pin arrangement for a gate array, characterized in that by arranging a power supply or a ground in an unused area, information that the sum of noise parameters of the output buffer is lowered and the upper limit value is satisfied is provided. apparatus. 12. In a pin arrangement in a gate array design, when a power supply buffer, a ground buffer, and an output buffer having a noise relationship with these are arranged on a gate array chip, the sum of noise parameter values of the output buffers. Is smaller than the upper limit value, and when the upper limit value has a margin, it provides information that the change can be made within a range satisfying the upper limit value. 13. In a pin arrangement in a gate array design, when a master fixed fixed power supply buffer of the same power supply system, a ground buffer, and an output buffer causing a simultaneous change of these are arranged on the gate array chip, an output buffer is provided. When the sum of the noise parameter values of is smaller than the upper limit value and there is a margin up to the upper limit value, it provides information that it is possible to increase the driving capability of the signal buffer within a range that satisfies the upper limit value. Gate array automatic pin placement device. 14. The gate array automatic pin placement device according to claim 8, wherein the information is provided in consideration of the presence of an additional power supply. 15. The automatic gate array pin placement device according to claim 8, wherein the information is provided in consideration of the presence of an additional ground buffer. 16. The netlist file according to any one of claims 1 to 15, wherein the netlist file is edited in consideration of the changed contents in accordance with the conversion of the buffer and the change of the pin arrangement. Gate array automatic pin placement device. 17. The pin layout information file in consideration of the contents of modification is edited and output according to the conversion of the buffer and the modification of the pin layout, according to any one of claims 1 to 16. Gate array automatic pin placement device.