JP2620150B2 - Wiring layout method in semiconductor integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a wiring layout method applied to a semiconductor integrated circuit device.

<Prior Art> Hereinafter, a gate array device will be described as an example of a semiconductor integrated circuit device.

In the gate array device, a large number of basic cells including elements such as transistors are formed in advance, and a macro cell having a specific function such as a NAND gate is formed by connecting the basic cells, and the macro cells are connected to each other. In this way, the required functions are exhibited.

In such a gate array device, wiring for connecting inside or between basic cells for forming a macro cell;
Wiring for connecting the macro cells to each other is required.

The latter wiring is performed so as to pass through a channel region as a wirable region provided in the macro cell in advance.

<Problems to be Solved by the Invention> Even in the case of macro cells having the same function, the number or position of the channel region may be different depending on other macro cells formed around. In such a case, wiring layout must be performed according to the number, position, and the like of the channel regions.

The present invention has been made in view of the above circumstances, and a wiring layout method in a semiconductor integrated circuit device that can perform wiring layout by the same method even if the number, position, and the like of channel regions are different in a macro cell. It is intended to provide.

<Means for Solving the Problems> A wiring layout method in a semiconductor integrated circuit device according to the present invention is directed to a method for determining whether or not a planned channel region to be a channel region through which wiring interconnecting macrocells passes is formed in the macrocell. This is a wiring layout method to which the same cell layout can be applied regardless of the above.

A wiring layout method in such a semiconductor integrated circuit device includes a step of determining whether to provide a channel region in a macro cell, and a step of determining whether to provide a channel region.
A step of determining the number of channel regions to be provided in the macro cell; a step of determining the number of planned channel regions in accordance with the number of channel regions to be provided; a grid on the determined planned channel region as a virtual grid; There is a step of associating other grids with a macro cell grid having no virtual grid, and a step of performing the same cell layout regardless of the presence or absence of the virtual grid.

<Operation> It is determined whether to provide a channel region in the macro cell,
When it is determined that a channel region is provided, the number of channel regions to be provided in the macro cell is determined. After that, the number of planned channel regions is determined according to the number of channel regions to be provided.

A grid on the determined channel scheduled area is set as a virtual grid, and grids other than the virtual grid are made to correspond to grids of a macro cell having no virtual grid. Then, the same cell layout is performed regardless of the presence or absence of the virtual grid.

Embodiment An embodiment according to the present invention will be described below with reference to the drawings.

FIG. 1 is a flowchart of a wiring layout method in a semiconductor integrated circuit device according to one embodiment of the present invention, FIG. 2 is an explanatory diagram of a basic cell provided with a planned channel region, and FIG. 3 is provided with a planned channel region. FIG. 4 is an explanatory diagram of a basic cell that is not provided.

According to the wiring layout method in the semiconductor integrated circuit device according to the present embodiment, whether or not _two planned channel regions A ₁ and A _{2 that} are to be channel regions through which wiring for interconnecting macro cells pass are formed in the basic cell 100 The same cell layout can be applied regardless of whether or not the cell layout is used.

The basic cells 100 are allocated to a plurality of grids indicated by “•” and “z” in FIG. In the following description, a specific grid will be indicated by the (X, Y) coordinates shown in FIGS. 2 and 3.

A case where the wiring layout method in the semiconductor integrated circuit device according to the present embodiment is applied to the basic cell 100 will be described.

First, it is determined whether a channel region is necessary for the macro cell constituted by the basic cell 100 (first example).
See Figure S _1).

If the channel region is judged to be necessary, the number of the channel region, to determine the position or the like (see FIG. 1 S _2). The number of the channel region determined in the previous step S ₂ to a basic cell 100,
The number of the channel region where according to the position or the like, to determine the position or the like (see FIG. 1 S _3). Here, the basic cell 10
It is assumed that 0 has two planned channel regions A ₁ and A ₂ .

The grids (X _{1 to} X ₅ , A ₁ ) and (X _{1 to} X ₅ , A ₂ ) in the portions selected as the planned channel regions A ₁ and A ₂ are represented by virtual grids (“z” in FIG. ₂ ). Has been done). The virtual grids (X _{1 to} X ₅ , A ₁ ) and (X _{1 to} X ₅ , A ₂ ) are grids that are ignored when laying out the wiring inside the basic cell 100 and the wiring for forming the macro cell. Virtual grid _{(X 1 ~X 5, A 1} ) and _{(X 1 ~X 5, A 2} ) other than the grid _{(X 1 ~X 5, Y 1} ~Y 14) , and basic cell as shown in FIG. 3 , That is, the planned channel areas A ₁ and A ₂
Grid of the basic cell 200 (X _1-
X _5, Y ₁ to correspond to the to Y ₁₄₎ (see FIG. 1 S _4).

In this state, wirings for constituting the basic cell 100 in the wiring or the macro cell, i.e. macro cell layout performed (see FIG. 1 S _5). The layout of the wiring, since carried out a grid _{(X 1 ~X 5, Y 1} ~Y 14) as the basic unit, the virtual grid _{(X 1 ~X 5, A 1} ) and (X ₁ ~
X ₅ , A ₂ ) are equal to those that do not exist during the layout of this wiring. That is, the layout of internal wiring or the like of the basic cell 100, a virtual grid _{(X 1 ~X 5, A 1} ) and _{(X 1 ~X 5, A 2} ), i.e. the channel region where A _1, A ₂ has no basic cells This can be done with the same layout as 200.

If said step is determined that it is not necessary to provide the channel region in the S _1, jump to step S _5, the normal macro cell layout with respect to the channel region where A _1, A ₂ basic cells 200 no is performed.

<Effect of the Invention> According to the wiring layout method in the semiconductor integrated circuit device according to the present invention, the same macro cell layout can be performed regardless of the presence or absence of the channel region. Therefore, as long as the macro cells have the same function, even if the number, the position, and the like of the channel regions are different, the wiring layout can be performed by the same method, so that the manufacturing efficiency of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is a flowchart of a wiring layout method in a semiconductor integrated circuit device according to one embodiment of the present invention, FIG. 2 is an explanatory diagram of a basic cell provided with a planned channel region, and FIG. 3 is provided with a planned channel region. FIG. 4 is an explanatory diagram of a basic cell that is not provided. 100 ...... basic cell 200 ...... channel region is no basic cells _{(X 1 ~X 5, A 1} ), (X 1 ~X 5, A 2) ...... virtual grid _{(X 1 ~X 5, Y 1} ~Y ₁₄₎ ...... grid a ₁ other than the virtual grid, a ₂ ... channel scheduled region

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-55-163859 (JP, A) JP-A-64-82546 (JP, A) JP-A-61-283143 (JP, A) JP-A-3-3 262144 (JP, A)

Claims (1)

(57) [Claims] 1. A wiring layout in a semiconductor integrated circuit device to which the same cell layout can be applied irrespective of whether or not a planned channel region to be a channel region through which wiring for interconnecting macrocells passes is formed in the macrocell. In the method, a step of determining whether to provide a channel region in the macro cell, a step of determining the number of channel regions to be provided in the macro cell when determining to provide a channel region, Determining the number of planned channel regions by using a virtual grid as a grid on the determined channel planned region, and associating a grid other than the virtual grid with a grid of a macro cell having no virtual grid. And a step of performing the same cell layout regardless of Wiring layout method in a semiconductor integrated circuit device according to.