JPH08102729A - Automatic adjustment method/device for clock timing - Google Patents

Abstract

PURPOSE: To automatically adjust the timing errors and to eliminate the labor and time needed for the timing adjustment by reading the data out of a memory with change of the clock delay time to detect the errors for each delay time and defining a clock of a small error rate as the optimum delay time to apply it to the fetching of the following data. CONSTITUTION: An automatic clock timing adjustment device 'add' fetches the last data given from a data line 1 into an F/F 3. A delay circuit 10 placed at the clock line side has the output lines 11 to 18, and these data lines have different delay times. A selector 19 successively selects the outputs of lines 11 to 18 in a test mode to give these outputs to the F/F 3 and latches data to store them in a memory 9 via a data line 8. Then the data are read out of the memory 9 for each delay value and then judged for detection of the error rates. The optimum delay value of the smallest error rate is calculated to each delay value among those repetitively detected error rates. The selector 19 is fixed to the relevant delayed clock, and a clock having the optimum delay value is selected and the data are latched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock timing automatic adjusting method and a clock timing automatic adjusting apparatus, in which a data transmitter transmits data and a clock for synchronizing the data to a data receiver. In this case, the present invention relates to a clock timing automatic adjustment method and a clock timing automatic adjustment apparatus that are suitable for adjusting the timing and eliminating the deviation that occurs during transfer.

[0002]

2. Description of the Related Art In a system for handling data, a device for transmitting data and a device for receiving data are often connected by a cable or the like. Especially, digital data is transmitted by a data line and a clock line while synchronizing with a clock. Need to do. In such a case, a timing shift may occur due to variations in characteristics such as the cable length of the clock line and the data line and the difference in cable material.

In order to cope with such a timing deviation, the conventional timing adjusting method observes the waveforms of the clock and the data on the receiving device side, or displays the transferred data on a monitor or a printer. While outputting, the clock was adjusted by sequentially delaying it with a delay circuit or the like.

A technique for automatically adjusting such timing deviation is disclosed in "Automatic delay adjusting method" described in Japanese Patent Laid-Open No. 3-85939.

[0005]

The above prior art requires a device for observing the waveforms of clocks and data, and a device for displaying and outputting data, and it is extremely difficult to adjust the timing using the device. There was a problem that it took time and effort.

Further, in the technique described in Japanese Patent Laid-Open No. 3-85939, such a problem does not occur, but a synchronization signal indicating the start of serial data signal data is necessary in order to recognize a data shift. However, there is a problem in that a new cable is required for that purpose. Further, a reference timing generation circuit for generating an internal reference timing is required, which causes a problem that the device becomes complicated.

The present invention has been made in order to solve the above problems, and an object thereof is to provide a data receiving device between a data transmitting device and a data receiving device in which data and a clock for synchronizing the data are provided. When transmitted, clock timing that automatically adjusts the timing deviation that occurs between them, eliminates the need for data observation equipment, display equipment, and adjustment work, and does not require a new cable or timing circuit. An object is to provide an automatic adjustment method and a clock timing automatic adjustment device.

[0008]

In order to achieve the above object, the configuration of the invention relating to the automatic clock timing adjusting method of the present invention is a data transmitting apparatus capable of repeatedly transmitting data and a clock, and a data transmitting apparatus therefor. In a clock timing automatic adjustment method in the case of transferring the data in synchronization with the clock with a data receiving device that receives the data, the data receiving device delays the data, and delays the clock. Delay means for delaying a clock having a plurality of delay times, means for selecting a clock delay time of the delay means for delaying the clock, a memory, and fetching the data at the rise or fall of the clock, Means for storing in memory, means for reading data from the memory, processing and And a means for fixing the clock delay time with respect to the clock delay time selecting means, and (1) a procedure for delaying the data by the delay means for delaying the data, (2) A step of delaying the clock by delay means for delaying the clock; (3) a step of storing the data in the memory by the means for fetching the data and storing it in the memory at the rising or falling edge of the clock; 4) A procedure for reading the data from the memory, a procedure for reading the data stored in the memory, and (5) a means for processing and computing the data matches the read data with the transmitted data. To detect the error,
(6) A procedure for calculating an error rate for each delay time in which the clock is delayed by means for processing and calculating the data, (7) a clock for the means for selecting the delay time of the clock, The means for fixing the delay time has a procedure of setting the delay time of the clock so that the clock is delayed to the delay time of the portion with a low error rate, and (1) and (2) 3) Perform the procedure (L)
Then, by changing the delay time of the clock,
This procedure (L) is performed a plurality of times, and then the procedures (4) to (7) are performed in this order.

More specifically, in the above-mentioned automatic clock timing adjustment method, when the calculated error rates are arranged in the order of the magnitude of the delay time of the clock, the delay corresponding to the center of the lowest error rate is delayed. The time is set to the delay time set in the procedure (7).

In order to achieve the above object, the configuration of the invention relating to the automatic clock timing adjusting apparatus of the present invention is a data transmitting apparatus capable of repeatedly transmitting data and a clock, and receives the data. A clock timing automatic adjusting device for automatically adjusting clock timing when transferring the data in synchronization with the clock with a data receiving device, in the data receiving device side, delay means for delaying the data, Delay means for delaying a clock having a plurality of delay times for delaying the clock, means for selecting a delay time of the clock of the delay means for delaying the clock, memory, and rise or fall of the clock, Means for fetching the data and storing it in the memory, and reading the data from the memory And means, and means for processing the data, and calculates, with respect to means for selecting the delay time of the clock, and means for fixing the delay time of the clock,
The means for fetching the data and storing it in the memory stores the data delayed by the means for delaying the data in the memory at the rising or falling edge of the clock delayed by the means for delaying the clock, Means for reading data from the memory, reading the data stored in the memory, processing the data, means for computing, match the read data and the transmitted data, to detect an error, The means for processing and computing the data calculates an error rate for each delay time after the clock is delayed, and a means for fixing the clock delay time with respect to a means for selecting the clock delay time. Also, the clock delay time is set so that the clock is delayed to the delay time of the low error rate part. It is.

More specifically, in the above automatic clock timing adjustment device, when the calculated error rates are arranged in the order of the magnitude of the clock delay time, the delay at the center of the lowest error rate is delayed. The time is a delay time set by means for fixing the delay time of the clock.

[0012]

The optimum clock delay time is grasped during the test, and during the normal transfer, the clock is delayed by the optimum clock delay time found by the test and the data is taken in, thereby eliminating the timing deviation. it can.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to FIGS. First, a system configuration to which the clock timing automatic adjusting method according to this embodiment is applied will be described with reference to FIG. FIG. 2 is a system configuration diagram of a system including a host computer and peripheral devices to which the clock timing automatic adjustment method according to the present embodiment is applied.

In this system, as shown in FIG. 2, a host computer 40 is connected with a CRT device 41, a keyboard 42 and a printer device 45 as peripheral devices.

The printer device 45 comprises a printer control device 43 and a printer body 44. Also,
The host computer 40 and the printer control device 43 are
It is connected by a cable 46, and transfers the test data used in the present embodiment at the time of test and the print data to the printer main body 44 via the printer control device 43 at the time of printer operation such as hard copy. . The clock timing automatic adjustment device adj according to the present embodiment described below includes the printer control device 4
Built in 3.

Next, the clock timing automatic adjusting method according to the present invention will be outlined with reference to FIGS.
FIG. 1 is a block diagram showing the circuit configuration of the automatic clock timing adjustment apparatus according to the present embodiment. FIG. 3 is a flowchart showing the procedure of the clock timing automatic adjustment method according to this embodiment.

The present invention is applicable, for example, when it is necessary to transfer data in synchronization with a clock from a data transmitting device such as the host computer 40 of FIG. 1 to a data receiving device such as a printer device 45. , A method for adjusting the synchronization of data and clock.

For that purpose, the test data to be sent is determined, and this is sent to the receiving device side together with the clock signal.
On the receiving device side, a delay is generated between the transmitted data and the clock, the delay of the clock is variously changed, and the data generated at that time and the test data are matched on the receiving device side, and there is no difference in the data clock. Is adjusted as the desired clock.

Hereinafter, this will be described in the order of FIG. 3 with reference to FIG. First, the automatic clock timing adjustment device adj takes in the test data coming from the data line 1 to the input terminal D of the F / F (flip-flop) 3 (step 1).

The delay circuit 10 on the clock line side is set to 1
It has output lines 1 to 18, and the delay time is different for each data line.

In the test mode, the selector 19 sequentially selects the outputs from 11 to 18 and supplies them to the F / F 3 to latch the data. Then, the data is stored in the memory 9 via the data line 8 (step 2).

Next is a process of verifying the stored data.

First, the data stored in the memory 9 is read for each delay value (step 3).

Next, by comparing with the test data, data judgment is performed and the error rate for each delay value is detected (step 4). That is, the data different from the test data is determined as an error.

Repeat steps 3 and 4 for all de
Repeat for the lay value (step 5).

According to the above judgment, a desired clock is set. For that purpose, an optimum delay value that gives the lowest detected error rate is obtained (step 6),
In the fixed mode thereafter, the selector 19 is fixed (step 7) so that the delayed clock operates.
Select the clock with the optimum delay value and latch the data.

Next, the operation of the automatic clock timing adjustment device adj according to this embodiment will be described in detail with reference to FIGS. 1 and 4. FIG. 4 shows the dela according to this embodiment.
3 is a logic circuit diagram of a y circuit 10. FIG.

The microcomputer 33 controls the entire clock timing automatic adjusting device adj, and the ROM (Read
According to the program stored in (Only Memory) 38,
The clock timing automatic adjusting method of the present invention is executed. The microcomputer 33 utilizes the address line 28 to write the data into the memory 9 by using the selector control circuit 32, the address generation circuit 21, and the address line 2.
2. The address is given to the memory 9 through the path of the selector 23. Further, when reading data to the memory 9, an address is given to the memory 9 via the selector 23 using the address line 29.

The delay circuit has a del circuit on the data line 1 side.
The delay circuit 10 exists on the side of the ay circuit 34 and the clock line 2. The delay circuit 10 on the clock line 2 side has a plurality of output lines 11 to 18, and outputs signals to the output lines with different delay times. This d
The elay circuit 10 can be configured by the circuit shown in FIG. 4, for example.

The delay circuit 34 on the data line 1 side is for appropriately delaying the data according to the value delayed by the delay circuit 10 on the clock line 2 side. In the selector control circuit 32, the selector 19 is controlled by the selector control line 27 and the selector 23 is controlled by the selector control line 30. According to the control of the selector control circuit 32,
The selector 19 selects the signals of the output lines 11 to 18 of the delay circuit and gives them to the F / F 3.

As described above, the data given to the F / F 3 from the data line 35 is latched at this timing and written to the memory 9 via the data line 8.

The memory 9 is capable of both reading and writing, and at the time of reading, the R / W terminal has "
"L" is input, and "H" is input at the time of writing.
The Din terminal is a terminal for writing data in the memory 9, and the Dout terminal is a terminal for reading data from the memory 9. In addition, when accessing, CS (Chip Selec
t) The circuit 26 inputs "H" to the CS terminal.

The data in the memory 9 is selected by the microcomputer 33 to the printer control device 43 by the signal line 36, stored in the buffer 37, and transferred, so that the printer main body 44 can print the data.

Finally, based on the above,
5 to FIG. 8 in addition to FIG. 3 and FIG. 3, the clock timing automatic adjusting method according to the present invention will be described based on specific data. FIG. 5 is a timing chart showing the relationship between the delay and advance of data and clock in comparison. FIG. 6 shows the delay circuit 10
It is a timing chart figure which compared and showed each output delay value. FIG. 7 is a diagram in which the contents of the memory address and the error portion thereof are pointed out.

A situation in which the present invention can be applied is a situation in which data and a clock are sent to a data receiving device from a data transmitting device such as the host computer 40 shown in FIG. Here, for example, data is supposed to be transferred in synchronization with the rising timing of the clock.

However, there is a case where the data and the clock are deviated at the time of transfer due to variations in the characteristics of the cable line on the way, and in such a case, it causes a data error. FIG. 5 is a timing chart showing such a case, where (a) is the center of data delayed by ΔT1 with respect to the rising edge of the clock, and (b) is
The case where the center of data is advanced by ΔT2 with respect to the rising edge of the clock is shown. That is, the desirable situation is that the center of the data and the rising edge of the clock coincide and the difference between them becomes zero.

According to the present invention, in the test stage, various clocks are changed on the receiver side to find the optimum clock delay time so as to minimize such a shift, and the data error is reduced. It is a method of adjusting the timing of the clock.

Here, the clock timing automatic adjustment device adj shown in FIG.
1, D2, D3, D4, D5, D6, D7, D8, D
9, D10} are repeatedly transferred bit by bit in synchronization with the clock. This specific data is D1 = 1, D2 = 0, D3 = 1, D4 = 0, D5 =
1, D6 = 0, D7 = 1, D8 = 0, D9 = 1, D10
= 0, and these are repeated 80 times (80
Let's assume the situation where it is sent. Note that this test data needs to be recognized by the data receiving side in order to compare the data.

First, the clock timing automatic adjusting device a
dj is one bit of this data coming from the data line 1,
The data is taken into the input terminal of the F / F (flip-flop) 3 (step 1).

The delay circuit 10 on the clock side is 11
It has output lines from 1 to 18, and delays each data line. This delay is 6 ns from the top
It should be done one by one. FIG. 6 shows the timing chart. Output line n (n = 11 to 1
The clock output from 8) is also described as the delay value n.

The selector 19 delays the clock received from the delay circuit 10 with delay values 11, 12, 13, 1.
One is selected from 4, 15, 16, 17, and 18 and is output to the signal line 20. The F / F 3 latches the data coming from the data line 35 at the rising timing of this signal 20, and this data is written in the memory 9 via the data line 8 (step 2).

Here, the selector control circuit is the selector 1
Whenever the clock of 9 is counted 100 times,
It is assumed that the y value 11 to the delay value 18 are sequentially switched and the output line 20 is controlled to output. In this way, the data sent from the data transmitter will be
Each delay value is sequentially stored in the memory 9 by 100 bits.

The delay circuit 34 on the data side is
The signal on the data line 1 is delayed by 27 ns and output to 35.
This is for adjusting the center of the data to the vicinity of the rising edge of the delay value 14 or 15 shown in FIG. 6 in consideration of the fact that the delay on the clock side is 6 ns each.

In the above situation, if the T input to the F / F3 selected by the selector has a delay value of 14, the output to the data line 8 of the F / F3 is the test data sent. Is expected to be the same as. However, the T input to F / F3 was delayed.
Delay value 11 or del that is significantly different from the value 14
When the ay value of 18 is adopted, the D input of F / F3 is 1
However, a so-called "data garbled" phenomenon may occur in which the Q output becomes 0, or conversely, the Q output becomes 1 even when the D input is 0. This is a natural consequence of the large shift between the data center and the clock.

Therefore, in the data stored in the memory 9, the pattern of the test data is not stored repeatedly, but a portion where the patterns do not match occurs. FIG. 7 shows the data stored in the memory 9 in this way, and the data surrounded by circles are data in which the pattern does not match the test data, that is, erroneous data.

Here, the data stored in the addresses 0 to 99 corresponds to the delay value 11, and the data stored in the addresses 700 to 799 corresponds to the delay value 18.

Next, the process proceeds to the step of verifying the correctness of the data thus stored. First, as shown in FIG. 7, the data stored in the memory 9 is read for each delay value (step 3). That is, specifically, the delay values 11, 12, 13, 14, 15, 1 from the memory 9 are
Data of every 100 bits corresponding to 6, 17, and 18 are read out through the data line 31. The read operation of the microcomputer 33 at this time has already been described.

Next, the read data is verified to detect the error rate for each delay value (step 4). Specifically, the read data and the value of the test data are subjected to pattern matching, the areas that do not match are counted, and the number of erroneous areas may be divided by the total number. For example, if the delay value is 11, and there are 24 errors in 100, the error rate is 24%.

Here, it is assumed that the error rate thus obtained for each delay value is as shown in Table 1 below.

[0050]

[Table 1]

Next, according to the above result, an optimum delay value that gives the lowest detected error rate is obtained (step 6). In the results shown in Table 1, delay
Since the error rate of the values 12, 13, 14, 15, 16 is 0%, the optimum delay value may be the delay value 14 which is the center of the distribution.

The test is finished up to this point, and after that, the selector 19 is fixed so as to operate with the clock having the delay value of the optimum delay value 14 (step 7), and the delay value is held. The data is latched by the clock.

This is the end of the work of adjusting the deviation of the data with respect to the clock.

The procedure of the series of data storage, reading, error rate determination, and setting of the optimum delay value in the selector 19 is stored in the ROM and the microcomputer 33 interprets the procedure. It can be executed by executing.

As described above, by transferring the test data from the data transmitting device side and judging the error of the data at the receiving device side, the data delay with respect to the clock,
Since the advance can be automatically adjusted to the optimum position, accurate data will be stored in the memory 9 after the adjustment.

Since the present invention can automatically adjust the timing deviation due to the individual difference of the clock and data on the transmitter side and the difference in the cable length, it is effective when the transmitter is replaced or the cable length is changed by relocation to the field. . It is also effective when the clock frequency is high and the margin between the clock and data is small.

[0057]

According to the present invention, when data and a clock for synchronizing with the data are transmitted to the data receiving device between the data transmitting device and the data receiving device,
Clock timing automatic adjustment method and clock timing that automatically adjusts the timing deviation that occurs between them, eliminates the need for data observation equipment, display equipment, and adjustment work, and does not require a new cable or timing circuit An automatic adjustment device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a clock timing automatic adjustment device according to an embodiment.

FIG. 2 is a system configuration diagram of a system including a host computer and peripheral devices to which the automatic clock timing adjustment method according to the present embodiment is applied.

FIG. 3 is a flowchart showing a procedure of a clock timing automatic adjustment method according to the present embodiment.

FIG. 4 is a logic circuit diagram of the delay circuit 10 according to the present embodiment.

FIG. 5 is a timing chart showing the relationship between delay and advance of data and clock in comparison.

FIG. 6 is a timing chart showing, in comparison, each delay value output by the delay circuit.

FIG. 7 is a diagram showing the contents of a memory address and an error portion thereof.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hiroshi Suzuki 5-2-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Process Computer Engineering Co., Ltd. No. 1 in Hitachi Process Computer Engineering Co., Ltd. (72) Inventor Shuichi Nakamichi No. 2-5-1, Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi Process Computer Engineering Co., Ltd. (72) Inventor Koji Masui Hitachi City, Ibaraki Prefecture 5-2-1 Omika-cho, Ltd. Omika Factory, Hitachi Ltd.

Claims (4)

[Claims] 1. An automatic clock timing for transferring the data in synchronization with the clock between a data transmitting device capable of repeatedly transmitting data and a clock and a data receiving device receiving the data. In the adjusting method, the data receiving device sets a delay unit that delays data, a delay unit that delays a clock having a plurality of delay times that delay the clock, and a clock delay time of the delay unit that delays the clock. Means for selecting, memory, means for fetching the data at the rising or falling of the clock and storing it in the memory, means for reading the data from the memory, means for processing and computing the data, Means for fixing the clock delay time with respect to the means for selecting the clock delay time And (1) a step of delaying the data by the delay means for delaying the data, (2) a step of delaying the clock by the delay means for delaying the clock, and (3) taking in the data and storing it in the memory. Means for storing data in the memory at the rising or falling of the clock, (4) a procedure for reading data from the memory by the means for reading data stored in the memory,
(5) The means for processing and computing the data matches the read data with the transmitted data,
An error detection procedure, (6) an error rate calculation procedure for each delay time in which the clock is delayed by the means for processing and computing the data, (7) a means for selecting the clock delay time On the other hand, the means for fixing the delay time of the clock, the delay time of the portion with a low error rate,
And a step of setting a clock delay time so that the clock is delayed, and when the step (3) after (1) and (2) is (L), the clock delay time is Differently, the procedure (L) is performed a plurality of times, and then the procedures (4) to (7) are performed in this order in this order. 2. When the calculated error rates are arranged in the order of the magnitude of the delay time of the clock, the delay time at the center of the lowest error rate is (7)
2. The clock timing automatic adjusting method according to claim 1, wherein the delay time is set by the procedure of. 3. A clock timing automatic control when transferring the data in synchronization with the clock between a data transmitting device capable of repeatedly transmitting data and a clock and a data receiving device receiving the data. In the automatic clock timing adjustment device for adjusting, on the data receiving device side, delay means for delaying data, delay means for delaying a clock having a plurality of delay times for delaying the clock, and delaying the clock A means for selecting a clock delay time of the delay means; a memory; a means for fetching the data at the rising or falling of the clock and storing it in the memory; a means for reading the data from the memory; A means for processing and computing, and a means for selecting the delay time of the clock. And a means for fixing a clock delay time, wherein the means for fetching the data and storing the data in the memory causes the data to be stored in the memory at the rising or falling edge of the clock delayed by the means for delaying the clock. Stores the data delayed by the means for delaying, the means for reading the data from the memory reads the data stored in the memory, the means for processing the data, the arithmetic means, the read data And the transmitted data are matched, an error is detected, the data is processed, and an error rate is calculated for each delay time in which the clock is delayed by the calculating means, and the delay time of the clock is selected. The means for fixing the clock delay time is configured to delay the clock to the delay time of the portion having a low error rate. Clock timing apparatus for automatically adjusting and setting the delay time of the clock so that. 4. When the calculated error rates are arranged in order of magnitude of the delay time of the clock, the delay time at the center of the lowest error rate is fixed to the delay time of the clock. 4. The automatic clock timing adjusting device according to claim 3, wherein the delay time is set by the means for adjusting.