JPS60252280A - Logic analyzer - Google Patents

Abstract

PURPOSE:To distinguish easily a high-speed logic signal group and a low-speed logic signal group from each other by dividing signals to both groups and dividing boundary parts by time bases to display them. CONSTITUTION:A high-speed probe 7A takes out a high-speed logic signal from a circuit 5 to be tested and inputs this signal to a high-speed signal taking-in circuit 1A. The circuit 1A judges that the level of the logic signal is a prescribed high logical level or low logical level, and the circuit 1A receives high-speed clocks from a clock source 1G to normalize the high-speed logical signal, and the normalized output is supplied to a high-speed memory 1C, and the high-speed logic signal is written in the memory 1C. A low-speed logic signal taken out from the circuit 5 by a low-speed probe 7B is written in a low-speed memory 1D in the same manner. Waveform data taken into memories 1C and 1D are transferred to a video memory 9A through a microcomputer 3, and logical waveforms are displayed on a CRT9C. At this time, write or read speeds of memories 1C and 1D are selected properly to match both of high-speed and low-speed logic signals to proper time bases, and they are displayed divisionally.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a logic analyzer used to analyze the operating status of various circuits operated by digital signals.

``Prior art'' Traditionally, the waveforms of various parts of a logic circuit, etc. are captured, the waveforms are displayed, and the timing relationship between the displayed waveforms is used to determine whether the circuit is operating correctly. There is a circuit testing device called Therefore, this logic analyzer displays multiple logic waveforms on the display screen.

By the way, the circuit under test often has a relatively high frequency, that is, a part that operates at high speed and a part that operates at low speed. As a result, if a high-speed logic signal and a low-speed logic signal are captured and displayed at the same time, and the time axis is set so that the high-speed logic signal can be properly viewed, the time axis for the low-speed logic signal will be expanded too much and it will simply be displayed as a single horizontal line. It will only be done. On the other hand, if the inter-axes are set so that the low-speed logic signals can be properly viewed, the high-speed logic signals will be compressed and displayed, making it impossible to see the timing of their falling and rising edges.

For this reason, conventionally, high-speed logic signals and low-speed logic signals are separately fetched into memory, and by converting the speed at which they are fetched into the memory or the speed at which they are read from the memory, it is possible to display both with appropriate waveforms.

"Problem to be solved by the invention" When high-speed logic signals and low-speed logic signals are respectively captured into memory, their time axes are shifted by changing the capture speed or readout speed, and both are displayed on a display. , it is necessary to identify which waveforms are fast logic signals or slow logic signals.

Conventionally, the drawing required the operator to make judgments based on the setting status of signal acquisition, etc., which had the drawback of poor efficiency.

According to the present invention, high-speed logic signals and low-speed logic signals are divided into groups and displayed, and a display is projected on the boundary between the groups.

For example, time 1 is a specific method of dividing the classification into Table 7
1i111 can be a hot wire.

Embodiment FIG. 1 shows the overall configuration of a circuit testing device equipped with a pattern generator. In the figure, 1 is a data acquisition device, 2 is a pattern generator, and 3 is a microcomputer. These data acquisition device 1 and pattern generator 2 are connected to a microcomputer 3K by a path line 4, and the data acquisition device 1 and pattern generator 2 are operated under the control of the microcomputer 3.

The pattern generator 2 uses a pattern memory 2A, a microcoat sequencer 2B that determines the reading address of the two pattern memories, and pattern data read from the pattern memory 2A to generate a pattern signal having an NRZ waveform. Signal generator 2c and signal generator 2
The driver group 2D amplifies the pattern signal output from the driver C to a signal having a predetermined level.

A pattern signal of, for example, 64 channels is outputted from the driver group 2D color, and this pattern signal is applied to the output globe 6A.A pattern signal of an appropriate channel is selected from the output probe 6A and the pattern signal is applied to the circuit under test 5. Reference numeral 6B indicates an input probe that receives an external control signal from the circuit under test 5.

A signal indicating that the circuit under test 5 has reached, for example, a state is taken in as an external control signal by this person's turn probe 6B, and this external control signal is sent to the microcoat sequencer 2BKi to perform an operation to change the conditions for pattern generation. .

Data acquisition device 1i71, high-speed signal acquisition circuit 1 person, low-speed signal acquisition [1) 1 path IB, high-speed memory l)], C, low-speed memo IJID, and low-speed memory IJ for these high-speed memories 1. A memory control 101 circuit 1E that controls writing and reading D, a word detector 1F that detects that the captured word is a preset word, and a capture circuit 1A and IB.
and a clock source 1G that supplies a clock to the clock.

7A is a high-speed probe for capturing high-speed signals; 7B is a low-speed globe for capturing low-speed signals.

It is assumed that the high-speed globe 7A has a capacity of, for example, 16 channels, and the low-speed probe 7B has a capacity of, for example, 48 channels.

The high-speed probe 7A extracts a high-speed logic signal from the circuit under test 5 and inputs it to the high-speed signal acquisition circuit IA. High-speed signal acquisition channel] A compares and determines whether the level of the input logic signal is at a predetermined T (logic level and L logic level) and a high-speed clock selected at an appropriate frequency from the clock source IG. , the high-speed logic signal is normalized at high speed, the normalized output is given to the high-speed memory +11.C, and the high-speed logic signal 1 is loaded into the high-speed memory IJ]-C.

The low-speed probe 7B extracts a low-speed logic signal from the circuit under test 5 and inputs it to the low-speed signal acquisition circuit IB. The low-speed signal acquisition circuit 1B has a novelty of the input logic signal at a predetermined level (
It compares and determines the logic level and whether it is L logic l/bell, receives a low-speed clock with an appropriate frequency from the clock source 1G, normalizes the low-speed logic signal at a relatively low speed, and then Low speed memo IJ for ilE normalized output
IDK-'5 Write low-speed logic signal to low-speed memory IJ ID.

The word detector IF detects that the signal to be taken in corresponds to a predetermined word, starts writing the memo January C9ID from the time of detection, and performs control to detect the end word and end the writing. .

The microcomputer 3 is composed of a central processing unit 3A, a read-only memo 113B, and a writable/readable memory 3c, and the central processing unit 3A controls the operation of each part according to a program stored in the read-only memo IJ 3B.

9 indicates a display device. This display 9 is a video memo IJ 9
A, a CRT control circuit 9B, and a CRT display 9C. D
The waveform data captured in the video memo IJ 9A is transferred to the video memo IJ 9A via the microcomputer 3.
By repeatedly reading A, logical waveforms for up to 16 channels can be displayed on the CRT 9C. At this time, high speed memo IJIc and low speed memo IJ1. By appropriately selecting the write speed or read speed of D, both the high speed logic signal and the low speed logic signal can be displayed aligned with the appropriate time axis.

11 indicates an input means. The pattern generation conditions of the pattern generator 2 and the data acquisition device 1 are determined by this manual means 11.
Enter and set the data import conditions, etc.

1.11') A communication interface for receiving pattern generation conditions, data acquisition conditions, etc. from section 1.11') is shown.

(Main Point of the Invention) In this invention, the high-speed logic signal and the low-speed logic signal taken into the high-speed memory IJ], C and the low-speed memory ID are displayed on the display 9.
, high-speed logic signals and low-speed logic signals are divided into groups and displayed.

This division is performed by the microcomputer 3. When the number of the channel to be displayed is inputted from the switching input means 11, the logic signal data of that channel number is read out from the high speed memo II IC and the low speed memo IJ], D, and transferred to the video memo 119A.

At this time, the logic signal data read from the high speed memory IC is written to the upper address side of the video memory IJ 9A, for example, and the logic signal data read from the low speed memory IC 11] and D is written to the lower address of the video memory IJ 9A. do. All logic signals to be displayed are high-speed memo IJ], C
If it is a logic signal read out from the video memory 9
All 1 high-speed logic signals are input using A from the upper address to the lower address. If all the logic signals to be displayed are the logic signals read from the low-speed memory IJ ID, the low-speed logic signals to be displayed are written using the upper to lower addresses of the video memo IJ 9A.

When a channel to be displayed is set in the microcomputer 3, the channels are searched and transferred in descending order of channel number, for example, and are written from the upper address to the lower address in the video memory 9A in accordance with the transfer order.

Figure 2 shows a state in which only one of the logical signals read from the high-speed memory IJIc (hereinafter referred to as the A group) or the logical signals read from the low-speed memory IJID (hereinafter referred to as the T'B group) is displayed. .

In this state, the scale line LM representing the division is displayed at the bottom.

FIG. 3 shows an example in which group A and group B are displayed on one screen. This example shows a case where the A group is displayed for 4 channels and the B group is displayed for 2 channels. A scale line LM is displayed at the boundary between the A group and the B group.

Where the scale line LM is displayed is determined by the microcomputer 3. FIG. 4 shows a flowchart of a program for making this determination. A at step ■
and group B are on the same time axis. A
If groups B and B are set to be imported and read out on the same time axis, the scale line L is displayed at the bottom in step ■.
Display M.

If groups A and B are not on the same time axis, step ■
It is determined whether all the channels to be displayed are only in group A. If there is only group A, a scale line LM is displayed at the bottom in step (2).

If all the channels are in group A, the process moves to step (2) and it is determined whether the only channels to be displayed are in group B. If there is only group B, a scale line LM is displayed at the bottom in step ①.

If all the channels to be displayed are not in the B group, the process proceeds to step (2), where the number of screen display channels of the A group is detected, and the scale line LM is displayed on the next level of the number of channels detected in step (2), and the process ends.

This series of operations is executed by the microcomputer 3.

"Effects" As described above, according to the present invention, among the plurality of logical waveforms displayed on the display 9, those having different time axes are divided into groups, and the grouping is divided by, for example, drawing a scale line LM. Since the signals are displayed on the display screen, it is possible to identify that the signals have different time axes. Therefore, we provide an easy-to-use analyzer that is easy to use.

[Modified Embodiment] In the above description, the scale image LM was used as a means to represent grouping, but it will be easily understood that other display methods can be adopted.

In the above, there are two groups, A and B, but it is easy to understand that they can be divided into three or more groups.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are waveform diagrams for explaining the display results when this invention is applied, and FIG. 4 is a diagram showing the main part of the invention. It is a flowchart for explaining operation. 1: Data acquisition device, 1A: High-speed signal acquisition circuit, IB:
Low-speed signal capture path, IC: high-speed memory, ID: low-speed memory IJ, ], E: memory control circuit, IF: word detector, 1G = clock source, 2: pattern generator, 3: microcomputer, 4 : bus line, 5: circuit under test,
6A: Output globe, 6B: Input probe that takes in external control signals, 7A-, 7B: Input probe, 9: Display,
11: Input means, 12: Communication interface. Patent Applicant: Takeda Riken Kogyo Co., Ltd. Representative: Takuki Kusano 4th Procedural Amendment (Voluntary) 1980, t'6 days (-・( Commissioner of the Japan Patent Office, 1 ■ Patent Application 1982- :l08921, Title of the invention Relationship with the case of the person making the amendment to Logic Analyzer 3 Patent applicant Takeda Riken Kogyo Co., Ltd. 5, Subject of the amendment Detailed explanation column of the invention in the specification and content of the amendment to the drawing 6 (1) Specification Page 6 lines 14-15 [Detect...start (2
) In the same book, page 9, lines 11-12, "14 channels" is corrected to "6 channels." (3) Correct figure 4 in the drawing as shown in the attached figure. Figure 4

Claims (1)

[Claims] (])A. B. a plurality of memories for capturing the response outputs of the test target in groups according to crosslink signals of different frequencies; A display device for displaying signal waveforms for each group read out from the plurality of memories, and C. A means for adding a display indicating division to the displayed waveforms of each group when signals of groups having different captured frequencies are displayed simultaneously. A logic analyzer consisting of and.