JPH08102523A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To obtain a semiconductor integrated circuit for which a latch-up protective countermeasure is taken and in which a latch-up protective circuit being reset automatically upon ending latch-up is provided while simplifying the circuitry. CONSTITUTION: A P channel transistor 50 utilizing ON resistance is provided between a power supply Vdd and a circuit body 10 and an N channel transistor 60, having gate connected with a point P, is provided between the circuit body 10 and the ground.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit provided with a latch-up protection measure.

[0002]

2. Description of the Related Art Conventionally, it has been known that a phenomenon called latch-up occurs in a semiconductor integrated circuit. If the latch-up phenomenon occurs, not only a malfunction of the circuit but also a large current flows to melt a metal wiring. This may cause damage to the semiconductor integrated circuit. Measures for avoiding this destruction have been conventionally considered.

FIG. 3 is a circuit block diagram showing a conventional latch-up protection circuit. Electric power is supplied to the circuit body 10 via the transistor 20. This transistor 20 is normally kept in the ON state. When a latch-up occurs in the circuit body 10, a large current flows from the power supply V _dd to the circuit body 10, so that the voltage drop due to the on-resistance of the transistor 20 increases, and the voltage drop is detected by the detection circuit 30. When the detection circuit 30 detects that latch-up has occurred due to the voltage drop, the detection signal is transmitted to the single pulse generation circuit 40, and the single pulse generation circuit 40 causes the transistor 20 to change.
Is applied to the transistor 20 by sending out a pulse signal that turns off for a predetermined time. As a result, the circuit body 10
The current flowing into the circuit is cut off, the latch-up phenomenon ends, and when the transistor 20 next shifts to the ON state, the circuit body resumes normal operation. With such a circuit configuration, it is possible to prevent the circuit body 10 from being broken at the time of latch-up.

FIG. 4 is a circuit block diagram showing another conventional latch-up protection circuit. As in the example shown in FIG. 3, electric power is supplied to the circuit body 10 via the transistor 20. When latchup occurs in the circuit body 10 and a large amount of power starts to flow, the voltage at the point A drops, the output of the inverter 31 shifts to the “H” level, and the transistor 20
To the off state. Further, in the steady state, the capacitor 32 is charged, so that one input terminal 32a of the NAND gate 32 is kept at the “H” level,
When the output of the inverter 31 shifts to the'H 'level, the signal is transmitted to the other input terminal 32b of the NAND gate 32, the output of the NAND gate 32 becomes the'L' level and the signal is transmitted to the input terminal of the inverter 31. To be done.
Therefore, once the transistor 20 transits to the off state, that state is maintained and no electric power is supplied to the circuit body 10.

In the case of this example, the electric power is _resupplied to the circuit body 10 by once turning off the power supply V _dd and then turning on the power supply V _dd again. When the power source V _dd is turned on, immediately after the power source is turned on, no charge is stored in the capacitor 33, and one input terminal of the NAND gate 32 until the charge is stored in the capacitor 33 via the resistor 34. 32
a is at the'L 'level, therefore NAND gate 3
2 output terminal, that is, the gate of the transistor 20 is "L"
At the level, therefore, the transistor 20 is turned on, and power is supplied to the circuit body 10. After that, even if the electric charge is accumulated in the capacitor 33 and the input terminal 32a of the NAND gate 32 becomes the “H” level, at that time, the output terminal of the inverter 31, that is, the NAND gate 3 is already present.
The other input terminal 32b of 2 is at the'L 'level,
The output terminal of the NAND gate 32, that is, the input terminal of the inverter 31 remains at the'H 'level.

[0006]

Conventionally, as a protection circuit at the time of latch-up, the circuit as described above has been considered, but all of them have a complicated circuit structure and a large chip area for latch-up protection. There is a problem that requires. Further, in the case of the circuit configuration shown in FIG. 4, after the latch-up occurs, the automatic recovery is not performed, and it is necessary to turn off the power supply and then turn it on again.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor integrated circuit having a simple circuit configuration and further including a latch-up protection circuit that automatically recovers after latch-up ends.

[0008]

A semiconductor integrated circuit of the present invention that achieves the above-mentioned object is a circuit main body that performs a required circuit operation, and between the circuit main body and a power supply and between the circuit main body and the ground. It is characterized in that it is provided with a resistor and a transistor which shifts to an on state or an off state according to the potential of a connection point between the resistor and the circuit body, which is arranged on one side and the other side, respectively.

Here, in the semiconductor integrated circuit of the present invention, the resistor may be a transistor wired so as to always maintain an on state.

[0010]

According to the semiconductor integrated circuit of the present invention, in addition to the circuit body, a latch-up protection circuit is composed of one resistor and one transistor. Moreover, after the latch-up phenomenon ends, the circuit body automatically Power is supplied.

[0011]

Embodiments of the present invention will be described below. FIG. 1 is a circuit diagram of an embodiment of the semiconductor integrated circuit of the present invention. A P-channel transistor 50 is arranged between the circuit body 10 and the power supply V _dd, and an N-channel transistor 60 is arranged between the circuit body 10 and the ground.

Here, the gate of the P-channel transistor 50 is connected to the ground, and the P-channel transistor 50 is always kept in the ON state.
The on-resistance of the channel transistor 50 causes
It plays the role of a resistor in the present invention. On the other hand, the gate of the N-channel transistor 60 is connected to the connection point P between the P-channel transistor 50 and the circuit body 10.

In a normal state, the current flowing into the circuit body 10 is not so large, the potential at the point P is close to the potential of the power source V _dd , the N-channel transistor 60 is in the ON state, and power is supplied to the circuit body 10. To be done. Circuit body 10
When latch-up occurs, a large current flows into the circuit body 10 via the P-channel transistor 50, the potential at the point P drops, and the voltage applied to the gate of the N-channel transistor 60 drops. The threshold value of the N-channel transistor 60 maintains the ON state at the P point potential when the circuit body 10 is in a normal operating state, and the circuit body 1
It is adjusted to a level at which the latch-up occurs at 0 and the potential at the P point drops abnormally to the off state. Therefore, when the latch-up occurs in the circuit body 10, the N-channel transistor 60 is turned off due to the abnormal drop in the potential at the point P, and the current flowing into the circuit body 10 is cut off. This ends the latch-up. When the latch-up ends, the potential at point P rises again and the circuit body 10
Is powered.

FIG. 2 is a circuit diagram of another embodiment of the semiconductor integrated circuit of the present invention. In this embodiment, the gate of the N-channel transistor 60 is connected to the power supply V _dd to
The channel transistor 60 is always maintained in the ON state, and the ON resistance of this N-channel transistor functions as the resistor in the present invention. On the other hand, the gate of the P-channel transistor 50 is connected to the connection point Q between the circuit body 10 and the N-channel transistor 60. The potential at this point Q is close to the ground potential when the circuit body 10 is operating normally, the P-channel transistor 50 is on, and power is supplied to the circuit body 10.

When latch-up occurs in the circuit body 10, a large current flows in the circuit body 10 and the large current also flows in the N-channel transistor 60, so that the potential at the point Q rises.
The voltage applied to the gate of the P-channel transistor 50 increases. The threshold value of the P-channel transistor 50 remains on at the Q point potential when the circuit body 10 is in a normal operating state, and is off when the circuit body 10 latches up and the Q point potential rises abnormally. The level has been adjusted to move to. Therefore, if latch-up occurs in the circuit body 10, the potential at the Q point rises abnormally and P
The channel transistor 50 transitions to the off state, and cuts off the current flowing into the circuit body 10. This ends the latch-up. When the latch-up ends, Q again
The potential at the point drops and power is supplied to the circuit body 10.

Next, the effectiveness of the present invention will be considered by taking the circuit configuration shown in FIG. 1 as an example. The power consumption of the circuit body 10 is assumed to be 0.5 W, assuming a general circuit. When the power supply voltage is 5V, the current flowing through the circuit body 10 is 0.5W / 5V = 0.1A. That is, when the circuit body 10 is in a normal operating state, the power source line has about 0.1
A is flowing.

Assuming that the on-resistance of the P-channel transistor 50 is 1Ω, the voltage drop ΔE due to the P-channel transistor 50 is ΔE = 1Ω × 0.1A = 0.1V The on-resistance (1Ω) of the P-channel transistor 50.
The electric power W consumed by is W = (0.1) ² × 1 = 0.01W.

The power supply voltage is allowed to vary by about 10%,
A fluctuation in the range of 4.5V to 5.5V is expected, but P
The voltage drop due to the channel transistor 50 is 0.1
V and power consumption are about 0.01 W, and there is no problem. When the threshold value V _TH of the N-channel transistor 60 is set to V _TH = 2.0V, the latch-up occurs in the circuit body 10 and when a voltage of 3.0 A or more flows, the N-channel transistor 60 transitions to the off state. The current flow to the main body 10 stops.

Further, when the power supply voltage V _dd is 3 V ± 0.3 V, when a current of 1.0 A or more flows into the circuit main body 10, N
The channel transistor 60 shifts to the off state. As described above, in the circuit of FIG. 1, it is possible to discriminate between the normal state and the latch-up state with a margin after suppressing an increase in power consumption and the like within an allowable range.

[0020]

As described above, according to the present invention,
A circuit that can protect the circuit from damage due to latch-up with a simple circuit and that automatically recovers after the end of latch-up is configured.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is a circuit diagram of another embodiment of the semiconductor integrated circuit of the present invention.

FIG. 3 is a circuit block diagram showing a conventional latch-up protection circuit.

FIG. 4 is a circuit block diagram showing another conventional latch-up protection circuit.

[Explanation of symbols] 10 circuit body 50 P-channel transistor 60 N-channel transistor

Claims (2)

[Claims] 1. A circuit body for executing a required circuit operation, and a resistor and said resistor arranged respectively on one side and the other side between the circuit body and a power source and between the circuit body and ground. A semiconductor integrated circuit, comprising: a transistor that transits to an on state or an off state according to a potential of a connection point with the circuit body. 2. The semiconductor integrated circuit according to claim 1, wherein the resistor is a transistor wired so as to always maintain an on state.