JPH08101253A - Semiconductor tester - Google Patents

Abstract

PURPOSE: To automatically compensate an error for each connection model, improve measurement accuracy, and at the same time facilitate the control of a device by providing a plurality of switches inside a tester and a tester head, switching each switch and measuring the frequency characteristics of each part, and calculating the compensation coefficient of a signal generator and a signal measuring instrument. CONSTITUTION: A switch A20 is provided at a tester 18 and switches B21, C22, D23, and E24 are provided at a test head 19. First, only the switch A20 is closed and other switches are opened, the amplitude of, for example, 2MHz signal from a signal generator 11 is measured 17, and the measurement value is stored 25 as S1 (Vpp). Similarly, amplitudes S2-S4 of 2MHz signal are measured 17 and stored 25 and then the compensation coefficients of the generator 11 and the measuring instrument 17 are subjected to operation. Further, after obtaining the compensation coefficients of 3, 3.5, 4, and 5MHz, a DUT 14 is connected and the characteristics of a band-pass filter with its center at 3.5MHz are measured, thus judging to be nonconforming when the measurement values exceeds set upper and lower limits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor testing device used for testing semiconductors, printed circuit boards and the like.

[0002]

2. Description of the Related Art FIG. 3 shows the configuration of a conventional semiconductor test apparatus. In FIG. 3, reference numeral 31 is a signal generator that generates a sine wave signal. Reference numeral 32 denotes a connection cable, which supplies the output signal from the signal generator 31 to the input buffer 33. Reference numeral 34 denotes a DUT which is a semiconductor to be measured, and when a signal from the input buffer 33 is input, it outputs a response signal peculiar to this semiconductor. An output buffer 35 is a DUT
Buffer the signal under test from 34. Reference numeral 36 denotes a connection cable, which supplies the signal from the output buffer 35 to the signal measuring instrument 37. Signal generator 31 and signal measuring device 3
A tester 38 is composed of the input buffer 33 and the DU.
A test head 39 is composed of T34 and the output buffer 35.

Next, the operation of the above conventional example will be described. In this example, a band pass filter having a center frequency of 3.5 MHz is assumed as the DUT 34, and the DUT
34, 2MHz, 3MHz, 3.5MHz, 4M
The characteristics of the band pass filter of the DUT 34 are determined by applying a sine wave signal of Hz and 5 MHz and measuring the output.

First, in FIG. 3, a sine wave signal of 3.5 MHz and 1 Vpp is generated from a signal generator 31, and this signal is D through a connection cable 32 and an input buffer 33.
Apply to UT34. The signal under measurement output from the DUT 34 is transmitted to the signal measuring instrument 37 via the output buffer 35 and the connection cable 36. In the signal measuring device 37, 3.5M
Measure the amplitude of the Hz component signal.

Next, the frequency of the output signal of the signal generator 31 is sequentially changed to 2 MHz, 3 MHz, 4 MHz and 5 MHz, and the signal measuring instrument 37 measures the amplitude of the corresponding frequency. The amplitude value corresponding to each frequency thus obtained is compared with the upper limit value and the lower limit value, the pass / fail of the DUT 34 is determined, and the result is notified to the DUT carrier.

[0006]

However, in the above-mentioned conventional semiconductor test apparatus, the signal measurement for the output signal of the signal generator 31 is performed by the insertion loss of the connection cables 32 and 36 and the frequency characteristics of the input buffer 33 and the output buffer 35. There is a problem that the measurement accuracy of the instrument 37 deteriorates.
In addition, in order to avoid the above problem, the connection cables 32, 3
There is also proposed a test apparatus that guarantees the applied and measured signal level frequency characteristics at the input and output ends of 6, and corrects the frequency characteristics of the input buffer 33 and the output buffer 35 on the measurement program. However, when measuring the same type of DUT with a plurality of test devices, a plurality of test heads 39 are required, and an error occurs between these test heads. In order to absorb this error, it is necessary to perform complicated operation management due to frequency measurement and change of measurement program for each test head, or there is no choice but to perform measurement with the error of each test head included. There was a problem that I could not get it.

The present invention solves the above-mentioned conventional problems, and automatically corrects the error for each connection model such as the frequency characteristics of the connection cable and the test head, thereby obtaining a highly accurate measurement result. It is an object of the present invention to provide an excellent semiconductor test apparatus that can be easily managed and operated even if the machine difference due to aging changes.

[0008]

In order to achieve the above object, the present invention provides a signal generator for generating a plurality of types of signals of a predetermined level at a predetermined frequency, and a signal for measuring the frequency and amplitude of a measurement signal. To the tester section, a tester section comprising a measuring instrument and a first switch means for opening and closing between the output end of the signal generator and the input end of the signal measuring instrument, and a signal input terminal from the tester section and the tester section. Second switch means for opening / closing between the signal output terminal and the signal output terminal, third switch means for opening / closing between the signal input terminal and the input terminal of the semiconductor under test, the signal output terminal and the semiconductor under test. A switch head for opening and closing the output terminal of the semiconductor device, and a fifth switch means for opening and closing the input terminal and the output terminal of the semiconductor to be measured, a test head portion, the tester portion, and the tester portion. With test head part It is characterized in that a connecting cable to be connected.

[0009]

Therefore, according to the present invention, the difference in the frequency characteristics generated between the test heads, that is, the machine difference is automatically calibrated even when the semiconductors to be measured of the same type are measured by a plurality of test devices. As a result, all test equipment can be operated with the same measurement program, and there is no need to modify the measurement program due to changes in machine differences due to aging, resulting in highly accurate test results and easy operation of test equipment. Have.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows the configuration of the semiconductor test apparatus in this embodiment. In FIG. 1, 11 is a signal generator for generating a sine wave signal. This signal generator 1
No. 1 is calibrated by an external calibrator so that the signal level does not vary depending on the frequency of the generated signal. Reference numeral 12 is a connection cable A, which supplies the output signal from the signal generator 11 to the input buffer 13. 14 is a semiconductor to be measured D
It is a UT, and when a signal from the input buffer 13 is input, it outputs a response signal peculiar to this semiconductor. An output buffer 15 buffers the signal under measurement from the DUT 14. Reference numeral 16 is a connection cable B, which supplies the signal from the output buffer 15 to the signal measuring device 17. The connection cables 12 and 16 connect the tester unit 18 and the test head unit 19, respectively.

Reference numeral 20 denotes a switch A, which is a signal generator 11
The output terminal and the signal input terminal of the signal measuring device 17 are opened and closed. 21 is a switch B, which is the test head unit 1
The input terminal 9 (the connection point between the connection cable 12 and the input buffer 13) and the output terminal of the test head unit 19 (the connection point between the output buffer 15 and the connection cable 16) are opened and closed. A switch C 22 opens and closes the input terminal of the test head unit 19 and the input terminal of the DUT 14. Two
A switch D 3 opens and closes between the output terminal of the DUT 14 and the output terminal of the test head unit 19. A switch E 24 opens and closes an input terminal of the DUT 14 and an output terminal of the DUT 14. Reference numeral 25 is a memory, and 26 is a calculation unit. The correction coefficient and the like of the signal generator 11 and the signal measuring device 17 calculated by the calculation unit 26 are stored in the memory 25.

Next, the operation of the above embodiment will be described. In the present embodiment, the first operation for obtaining the correction coefficient and the second operation for testing the semiconductor under test are performed. The first operation is, prior to the test, the signal measuring device 17, the connecting cables 12 and 16, the input buffer 13, the output buffer 1.
The frequency coefficient of No. 5 is measured, and a correction coefficient for applying and measuring an appropriate signal to the input terminal and the output terminal of the DUT 14 is calculated for each frequency with respect to the signal generator 11 and the signal measuring device 17. The frequencies used for the test are 2 MHz, 3 MHz, 3.5 MHz, 4 MHz, as in the conventional example.
There are 5 types of 5 MHz.

The first operation will be described. First, the signal generator 11 is set to generate a sine wave signal having a frequency of 2 MHz and 1 Vpp. Next, only the switch A20 is closed and all other switches are opened, the signal from the signal generator 11 is used to measure the amplitude of frequency 2 MHz by the signal measuring device 17, and the measured value is stored in the memory 25 as S1 (Vpp). To do. Next, only the switch B21 is closed and all the other switches are opened, and the signal from the signal generator 11 is measured by the signal measuring device 17 for the amplitude of frequency 2 MHz.
2 (Vpp) and stored in the memory 25. Next, only the switch C22 and the switch E24 are closed and all the other switches are opened, and the signal from the signal generator 11 is measured by the signal measuring device 17 for the amplitude of frequency 2 MHz.
3 (Vpp) and stored in the memory 25. Next, only the switch D23 and the switch E24 are closed and all the other switches are opened, and the signal from the signal generator 11 is measured by the signal measuring device 17 for the amplitude of frequency 2 MHz.
4 (Vpp) and stored in the memory 25.

The S1 to S4 measured in this way are calculated by the calculation unit 26 according to the following (Equation 1) and the correction coefficient (K _{s (2M)} ) of the signal generator 11 and the correction of the signal measuring device 17 at a frequency of 2 MHz. The coefficient (K _{m (2M)} ) is calculated and stored in the memory 25.

[0015]

[Equation 1]

[0016]

[Equation 2]

Further, the frequency of the signal generator 11 is set to 3M.
Hz, 3.5 MHz, 4 MHz, 5 MHz are sequentially changed, and the correction coefficients of the signal generator 11 and the signal measuring device 17 corresponding to the respective frequencies are calculated in the same manner as above and stored in the memory 25.

Next, the second operation, that is, the operation of testing the semiconductor under test will be described. In this embodiment,
Assuming a band pass filter having a center frequency of 3.5 MHz for the DUT 14, 2 MH is used for the DUT 14.
The sine wave signals of z, 3 MHz, 3.5 MHz, 4 MHz and 5 MHz are applied and measured to determine the characteristics of the band pass filter.

Connect the DUT 14 and open all switches. Signal generator 1 using the correction factor (K _{s (3.5M)} )
1, a 3.5 MHz, 1 Vpp sine wave signal is transmitted through the connection cable A12 and the input buffer 13 to the DUT14.
Applied to the input terminal of. The applied voltage has a value shown in (Equation 3) below.

Applied voltage (Vpp) = K _{s (3.5M)} × 1 (Vpp) (3) The measured signal generated from the DUT 14 is output to the output buffer 1
5, transmitted to the signal measuring device 17 via the connection cable B16. The signal measuring device 17 measures the amplitude of the signal of the 3.5 MHz component, and by using the correction coefficient (K _{m (3.5M)} ),
The signal value at the output terminal of the DUT 14 is corrected.

Measured value after correction = K _{m (3.5 M)} × measured value (4) Next, the frequencies of the signal generator 11 are 2 MHz, 3 MHz,
Change to 4MHz and 5MHz sequentially, measure with the same correction, compare the obtained amplitude value with the upper and lower limit values, judge the pass / fail of DUT14, and send the judgment result to the handler (not shown). .

The graph shown in FIG. 2 is a comparison between the above embodiment and the conventional example. The results are obtained by using two semiconductor testers having the configuration shown in FIG. 1 and using a DUT 14 which has been confirmed to operate normally and which has to pass the test as a semiconductor to be measured. In this embodiment, the above-described correction operation is performed, but in the conventional example, no correction is performed.

In FIG. 2, the horizontal axis represents the applied frequency and the left vertical axis represents the relative amplitude ratio based on the amplitude measurement level at 3.5 MHz. The graph shown by the solid line is the present embodiment, and the graph shown by the broken line is the conventional example. Also,
The range shown by the vertical line for each frequency represents the upper and lower limit values for determining the pass / fail of the test. What deviates from this judgment area is the 4 MHz measured value of the first example of the conventional example, and the conventional example 2
It is a 3 MHz measured value of the formula. That is, the two expressions of the conventional example are both unacceptable, and the two expressions of this embodiment are both acceptable at all frequencies.

Furthermore, the input terminal and output terminal of the DUT 14 of the semiconductor tester are short-circuited, and the frequency characteristics of the test head 19 and the connecting cables 12 and 16 are measured. It is a measured value. From this, it can be seen that the frequency characteristic in the conventional example is not flat, but in the present embodiment, it is calibrated so as to have a flat frequency characteristic.

As described above, according to the above-described embodiment, when the semiconductor DUTs 14 to be measured of the same type are measured by a plurality of test devices, the difference in the frequency characteristics generated between the test heads,
In other words, by automatically calibrating machine differences, all test equipment can be operated with the same measurement program, and there is no need to modify the measurement program for changes in machine differences due to aging, resulting in highly accurate test results. It is possible to operate various test equipment.

[0026]

As is apparent from the above-described embodiment, the present invention, when measuring semiconductors of the same type with a plurality of test devices, produces a difference in frequency characteristics between test heads, that is, a machine difference. By automatically calibrating, all test equipment can be operated with the same measurement program, and there is no need to revise the measurement program for changes in machine differences due to aging, so highly accurate test results and easy test equipment It has an effect that it can be operated.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor test apparatus according to an embodiment of the present invention.

FIG. 2 is a frequency characteristic diagram in the example.

FIG. 3 is a block diagram of a conventional semiconductor test device.

[Explanation of symbols]

 11 signal generator 12 connection cable A 14 semiconductor under test (DUT) 16 connection cable B 17 signal measuring instrument 18 tester section 19 test head section 20 switch A 21 switch B 22 switch C 23 switch D 24 switch E

Claims (1)

[Claims] 1. A signal generator for generating a plurality of types of signals of a predetermined level at a predetermined frequency, a signal measuring device for measuring the frequency and amplitude of a measurement signal, an output end of the signal generator and the signal measuring device. And a second switch means for opening and closing between a signal input terminal from the tester section and a signal output terminal to the tester section. Third switch means for opening and closing between the signal input terminal and the input terminal of the semiconductor under test, and fourth switch means for opening and closing between the signal output terminal and the output terminal of the semiconductor under test, A semiconductor test apparatus including a test head section including fifth switch means for opening and closing between an input terminal and an output terminal of the semiconductor under test, and a connection cable connecting the tester section and the test head section. .