JPH0799665A - Digital convergence correction device - Google Patents

Abstract

PURPOSE:To provide the digital convergence correction device which has a short processing time for interpolating operation and setting of correction data and is superior in workability of convergence adjustment based on interpolating operation. CONSTITUTION:Correction data required for convergence adjustment is interpolated divisionally in two stages of rough interpolation at the time or adjustment and fine interpolation at the time of the end of adjustment; and with respect to rough interpolation at the time of adjustment, the address signal to a frame memory 3 is switched by an address substituting circuit 2 so that it is outputted as an address signal AD2 where the value of lower N bits (N is an integer equal to or larger than one and is smaller than M) of the M-bit vertical address (M is an integer larger than one) of an address signal AD1 generated by an address generating circuit 1 is substituted with a fixed value. The number of correction data based on rough interpolation operation is reduced to 1/2 of that based on fine interpolating operation to set the correction data in real time, and correction data at the time of the end of adjustment are set by fine interpolating operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention sets each correction data by interpolation calculation based on a value of typical correction data corresponding to an intersection of a lattice pattern assumed on a display screen of a CRT display device. The present invention relates to a digital convergence correction device configured to flow a correction current based on correction data in a correction coil of a convergence yoke.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a general configuration of a conventional digital convergence correction device. In the figure, 1 is an address generation circuit that outputs an address signal AD1 consisting of a horizontal address and a vertical address synchronized with a raster scan, 3 is a frame memory that stores correction data, and digital correction data corresponding to the input address signal AD1 Output DX. A D / A converter 4 converts the digital correction data DX output from the frame memory 3 into an analog voltage (current) value. 5 is a low-pass filter, which is a D / A converter 4
Horizontal interpolation is performed on the output of. 6 is a current output circuit, which is driven by the output of the low-pass filter 5,
A correction current based on the correction data DX is supplied to the correction coil 10 of the convergence yoke.

The adjustment and setting of the correction data DX of the frame memory 3 are performed by controlling the CPU control circuit 8 by operating the control panel 7, and the CPU control circuit 8 is based on a command input from the control panel 7. , And control the arithmetic processing and reading / writing of the correction data DX.

When the correction data DX is read from or written to the frame memory 3, the address signal AD1 output from the address generation circuit 1 becomes invalid, and the correction signal DX is read from or written to the address signal AD3 output from the CPU control circuit 8. And the data signal DS and the control signal CS.

In the digital convergence correction device 12 configured as described above, the lattice pattern of the lattice pattern is formed on the display screen of the CRT display device on the basis of the values of typical correction data corresponding to the respective intersections of the lattice pattern assumed as the correction points. Correction data was set by interpolation calculation for all correction points to perform convergence adjustment.

[0006]

In these digital convergence correction devices, in order to set the correction data of each correction point of the lattice pattern by interpolation calculation and actually perform the convergence adjustment, the display screen of the CRT display device is displayed. It requires observation and measurement work on the screen, and
The correction data needs to be set in the frame memory in real time. However, since the processing time required for interpolation calculation and setting of correction data is proportional to the number of correction data, increasing the number of correction data increases the processing time for interpolation calculation and setting of correction data, resulting in adjustment. There is a problem that the required waiting time becomes long and the workability is significantly reduced.

An object of the present invention is to provide a digital convergence correction device which has a short processing time for interpolation calculation and setting during convergence adjustment and is excellent in workability.

[0008]

In the convergence adjustment of a CRT display device, convergence correction data DX interpolated based on representative correction data corresponding to intersections of a grid pattern assumed as correction points on a display screen. A frame memory 3 for storing the address, an address generation circuit 1 for outputting an address signal AD1 composed of a horizontal address and a vertical address for sequentially reading the correction data DX of the frame memory 3 in synchronization with a raster scan, and the address signal. AD1 and the address signal AD
Address signal AD2 obtained by replacing the value of N lower bits (N is an integer of 1 or more and smaller than M) of a vertical address of M bits (M is an integer larger than 1) of 1 with a fixed value.
And an address replacement circuit 2 for switching the output from the frame memory 3 as an address signal, a D / A converter 4 for converting the correction data DX output from the frame memory 3 into an analog amount, and a D / A converter 4 A low-pass filter 5 for performing horizontal interpolation of the analog amount output from the CPU, a CPU control circuit 8 for controlling each circuit, a control panel 7 for operating the CPU control circuit 8, and a video on a CRT display device. It is provided with a display pattern generating circuit 9 for supplying a signal and a current output circuit 6 for supplying a correction current based on the correction data DX read from the frame memory 3 to the correction coil 10 of the convergence yoke, which is necessary for convergence adjustment. Rough interpolation at the time of adjusting the interpolation of the correction data DX by interpolation calculation and at the end of the adjustment Performed in two stages of the fine interpolation, the address signal AD2 is during adjustment when the coarse interpolation frame memory 3
The address data signal is output and the correction data is set by the coarse interpolation calculation in real time, and the correction data is set by the fine interpolation calculation at the end of the adjustment.

[0009]

In the rough interpolation calculation at the time of adjustment, the values of the lower N bits of the vertical address signal of the address signal of the frame memory are replaced with fixed values, so that the correction data necessary for the interpolation calculation at the time of adjustment can be obtained. As a result, the number is reduced to 1/2 ^N as compared with the conventional dense interpolation, the processing time for interpolation calculation and setting is reduced, the waiting time at the time of convergence adjustment is shortened, and the workability is improved.

[0010]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a digital convergence correction device of the present invention, and FIG. 2 is a circuit configuration diagram showing a configuration of an address replacement circuit used in the present invention. Incidentally, components having the same function as those of the conventional digital convergence correction device are designated by the same reference numerals. Also, the number of bits of the address is made much smaller than the actual one for the sake of simplicity of explanation, but in reality, the larger the number of bits of the address, the more remarkable the effect.

The digital convergence correction device 11 of the present invention includes an address generation circuit 1 for outputting a signal composed of a horizontal address and a vertical address, and M bits (M is an integer greater than 1) of the address signal AD1 at the time of convergence adjustment. Address replacement circuit 2 that switches to output an address signal AD2 in which the values of N lower bits (N is an integer greater than or equal to 1 and smaller than M) of the vertical address are output to a fixed value, and interpolation-corrected convergence correction data DX , A D / A converter 4, a low-pass filter 5, and a current output circuit 6
A control panel 7, a CPU control circuit 8 and a display pattern generation circuit 9.

The address generating circuit 1 includes a 2-bit horizontal address (H0, H1) synchronized with the raster scan,
A signal composed of a 4-bit vertical address (V0 to V3) is output as an address signal AD1 (see FIG. 2). When the address signal AD1 and the address signal AD2 are the same, the address signal AD1 and the CRT display screen are as shown in FIG.
It corresponds as shown in FIG. In addition, the address generation circuit 1 receives the control signal CS input from the CPU control circuit 8.
When the frame memory 3 and the display pattern generation circuit 9 are controlled by the CPU control circuit 8, the address signal AD1 is controlled to be invalid.

The address replacing circuit 2 is composed of a first multiplexer MP1 and a second multiplexer MP2, as shown in FIG. The lower two bits V0 and V1 of the vertical address of the address signal AD1 output from the address generation circuit 1 are input to the A terminals of the multiplexers MP1 and MP2, respectively, and the B terminal of the first multiplexer MP1 is The low level L and the B terminal of the second multiplexer MP2 are fixed to the high level H.

The S terminal of each multiplexer has a C terminal.
The control signal S from the PU control circuit 8 is input,
Each Y terminal is connected to the frame memory 3 so as to output the lower 2 bits (A0, A1) of the address signal AD2. The remaining bits V2, V3, H0, H1 of the address signal AD1 are connected so as to be directly output to the frame memory 3 corresponding to the remaining bits A2, A3, A4, A5 of the address signal AD2. .

Therefore, the address signal AD1 is switched to the address signal AD2 via the address replacing circuit 2,
It is configured to be input to the frame memory 3. When the control signal S is at the low level L, the address signal AD2 and the CRT display screen correspond to each other as shown in FIG.
When, the lower 2 bits of the address signal AD2 are A0 = 0,
As a result of being fixed as A1 = 1, the correspondence becomes as shown in FIG.

By the way, one frame of digital correction data DX is stored in the frame memory 3, and the digital correction data DX designated by the address signal AD2 is output. Then, the digital correction data DX output from the frame memory 3 is converted into a voltage value (current value) of an analog amount by the D / A converter 4 and output, and then the low-pass filter 5 performs horizontal interpolation. The output of the low-pass filter 5 drives the current output circuit 6, and the correction current based on the correction data is supplied to the correction coil 10 of the convergence yoke.

The control panel 7 is a CPU control circuit 8
It is composed of a key switch group for operating, and outputs a command signal to the CPU control circuit 8. On the other hand, the CPU control circuit 8 receives the command signal from the control panel 7,
In addition to the interpolation calculation and setting of the correction data DX in the frame memory 3, the display pattern generating circuit 9 for generating a video signal for displaying the adjustment pattern and the cursor on the display screen of the CRT display device at the time of convergence adjustment is controlled.

In the digital convergence correction device 11 having the above-described configuration, the interpolation of the correction data by the interpolation calculation required for the convergence adjustment is performed in two steps, that is, the rough interpolation at the time of adjustment and the fine interpolation at the end of the adjustment. . Then, in the rough interpolation at the time of adjustment, the control signal S for the address replacement circuit 2 is switched to the high level H by the CPU control circuit 8, and the lower 2 bits of the address signal AD2.
The bits are fixed to A0 = 0 and A1 = 1. As a result, the address signal AD2 and the CRT display device display screen correspond to each other as shown in FIG. Further, the correction data corresponding to the display screen at this time is D02, D12, ..., D3E as shown in FIG. 6, and only 16 pieces of correction data are needed. Therefore, in the rough interpolation at the time of adjustment, only these 16 correction data are arithmetically processed in real time by the interpolation calculation and the data are set.
In the embodiment, as a result of replacing the value of the lower 2 bits of the 4-bit vertical address with a fixed value, the number of correction data required for the rough interpolation at the time of adjustment is 1/4 that of the adjustment by the fine interpolation.
It has decreased to (2 ^N = 4).

On the other hand, at the end of the adjustment, the address signal AD2 is switched to the address signal AD1 and the address signal AD2 (address signal AD2 = address signal AD).
1) and the CRT display device display screen correspond to each other as shown in FIG. Then, the correction data corresponding to the display screen at this time comes to correspond as shown in FIG. 5, and interpolation calculation is performed by dense interpolation for all 64 correction data of D00, D10, ..., D3F, The correction data is set.

As described above, the processing time required for data setting according to the present invention is 16 t rough interpolation required at the start of adjustment, where t is the time required for interpolation calculation and setting of one correction data. And repeat the required number of times,
It is the sum of 64t time required for fine interpolation at the end of adjustment,
The processing time required for the interpolation calculation and setting of the correction data is reduced as compared with the case where only the fine interpolation calculation is used.

[0021]

According to the present invention, the interpolation of the correction data by the interpolation calculation required for the convergence adjustment is performed in two steps, that is, the rough interpolation at the time of adjustment and the fine interpolation at the end of the adjustment, and the rough interpolation at the time of adjustment is performed. By reducing the number of necessary correction data, the processing time required for interpolation calculation and setting of the correction data can be greatly reduced, the waiting time during convergence adjustment can be shortened, and the time during convergence adjustment can be shortened. A digital convergence correction device with excellent workability was obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing a specific example of an address replacement circuit used in the present invention.

FIG. 3 is an explanatory diagram showing a correspondence relationship between a display screen of a CRT display device and an address signal.

FIG. 4 is an explanatory diagram showing a correspondence relationship between a display screen of a CRT display device and address signals at the time of rough interpolation.

FIG. 5 is an explanatory diagram showing a correspondence relationship between a display screen of a CRT display device and correction data.

FIG. 6 is an explanatory diagram showing a correspondence relationship between a display screen of a CRT display device and correction data during rough interpolation.

FIG. 7 is a block diagram showing a circuit configuration of a conventional example.

[Explanation of symbols]

 1 Address Generation Circuit 2 Address Replacement Circuit 3 Frame Memory 4 D / A Converter 5 Low Pass Filter 6 Current Output Circuit 7 Control Panel 8 CPU Control Circuit 9 Display Pattern Generation Circuit 10 Correction Coil 11, 12 Digital Convergence Correction Device MP1, MP2 Multiplexer

Claims (1)

[Claims] 1. A frame for storing convergence correction data DX interpolated based on typical correction data corresponding to intersections of a lattice pattern assumed as correction points on a display screen in convergence adjustment of a CRT display device. A memory 3, an address generation circuit 1 for outputting an address signal AD1 composed of a horizontal address and a vertical address for sequentially reading the correction data DX of the frame memory 3 in synchronization with a raster scan, the address signal AD1 and the address The address signal AD2 is formed by replacing the value of N lower bits (N is an integer of 1 or more and smaller than M) of the vertical address of M bits (M is an integer larger than 1) of the signal AD1 with a fixed value. An address replacement circuit 2 for outputting as an address signal of the frame memory 3; , A D / A converter 4 for converting the correction data DX output from the frame memory 3 into an analog amount, and a low-pass filter 5 for performing horizontal interpolation of the analog amount output from the D / A converter 4.
A CPU control circuit 8 for controlling each of the above circuits;
Control panel 7 for operating PU control circuit 8
And a display pattern generation circuit 9 for supplying a video signal to the CRT display device and a current output circuit 6 for supplying a correction current based on the correction data DX read from the frame memory 3 to the correction coil 10 of the convergence yoke. Then, the correction data DX is interpolated by the interpolation calculation required for the convergence adjustment in two steps of coarse interpolation at the time of adjustment and fine interpolation at the end of the adjustment. A digital convergence correction device characterized in that the correction data is set as a signal in real time and correction data is set by coarse interpolation calculation in real time, and when the adjustment is completed, the correction data is set by fine interpolation calculation.