JP3146808B2 - Television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an aspect ratio of 16: 9.
The present invention relates to a television receiver having a display screen of
When an image having an aspect ratio of 4: 3 is displayed on the display screen, the display size in the horizontal direction is enlarged as it approaches the left and right ends relative to the center in the horizontal direction of the display screen. The present invention relates to a television receiver including a non-linear processing circuit for displaying the image No. 3 on the entire display screen, and a picture-in-picture (PIP) circuit for inserting a child screen into a parent screen.

[0002]

2. Description of the Related Art Recently, an image having an aspect ratio of 16: 9, such as a high-definition broadcast, which provides a more realistic feeling than a conventional image having a 4: 3 aspect ratio has appeared. A television receiver having a display screen with a ratio of 16: 9 has been commercialized and spread. A video signal having an aspect ratio of 16: 9 can be displayed on a television receiver having a display screen having an aspect ratio of 16: 9,
Conventionally, a video signal having an aspect ratio of 4: 3 is displayed. Thus, the aspect ratio 1
With the advent of 6: 9 video, video having an aspect ratio different from the aspect ratio of the display screen of a television receiver has come to be displayed.

As a display method for displaying a video signal having an aspect ratio of 4: 3 on a television receiver having a display screen having an aspect ratio of 16: 9, the aspect ratio is 4: 3.
Mode in which the video signal of the aspect ratio is compressed on the time axis and displayed on the display screen having the aspect ratio of 16: 9, and the mode in which the aspect ratio 16: 9 of the video signal having the aspect ratio of 4: 3 in the vertical center is enlarged and displayed. And a mode in which a video signal having an aspect ratio of 4: 3 is horizontally stretched and displayed on a display screen having an aspect ratio of 16: 9. As another mode, the present applicant has previously disclosed, in Japanese Patent Application No. 4-255871, when displaying an image having an aspect ratio of 4: 3 on a display screen of a television receiver having a display screen having an aspect ratio of 16: 9. In addition, the display size in the horizontal direction is enlarged as it approaches the left and right edges relative to the center in the horizontal direction of the display screen, so that an image having an aspect ratio of 4: 3 can be displayed on the entire display screen having an aspect ratio of 16: 9. Suggested how to display.

Here, an outline of this new display method will be described. One method for realizing this display method is to use a horizontal deflection output circuit. In FIG.
Horizontal output transistor 1, damper diode 2, resonance capacitor 3, horizontal deflection coil 4, S-shaped correction capacitor 5, flyback transformer (or horizontal output transformer)
The horizontal deflection output circuit 6 is newly provided with an S-shaped correction capacitor 7 in parallel with the S-shaped correction capacitor 5 and a switch 8 for switching between conduction and non-conduction of the S-shaped correction capacitor 7. At this time, the switch 8 is turned off (disconnected), and the power supply voltage Vcc applied to the transformer 6 is appropriately selected, so that the image having the aspect ratio of 4: 3 can be converted to the aspect ratio of 1
When the image is horizontally stretched and displayed on the 6: 9 display screen, the capacitance of the S-shaped correction capacitor 5 is selected so that the display size on the display screen is constant in the horizontal direction.

[0005] Then, when displaying as described above,
The switch 8 is turned on (turned on) to increase the power supply voltage Vcc so that the horizontal display range substantially matches the display screen.
When the switch 8 is turned on, the capacitance of the S-shaped correction capacitor increases due to the combined capacitance of the S-shaped correction capacitor 5 and the S-shaped correction capacitor 7, and the horizontal deflection current flowing through the horizontal deflection coil 4 is changed to the left and right ends on the display screen. As the scanning speed of the electron beam increases, the display size in the horizontal direction increases.
As can be seen from the display example of the cross hatch signal shown in FIG. In the display method as shown in FIG. 9A, the display size in the horizontal direction is enlarged as approaching the left and right ends relative to the center in the horizontal direction of the display screen. I have.
Hereinafter, this display method is referred to as non-linear processing.

According to such nonlinear processing, FIG.
As can be seen from the display example of the monoscopic signal shown in (B), the image is distorted at the left and right ends of the display screen, but the aspect ratio of the image is maintained at about 4: 3 at the center of the display screen. Therefore, a video having an aspect ratio of 4: 3 can be displayed on the entire display screen having an aspect ratio of 16: 9 without giving a viewer a sense of incongruity without any part being lost. Display that makes full use of the wide aspect becomes possible.

On the other hand, many television receivers having a PIP circuit for inserting another screen (child screen) into one screen (parent screen) have been widely used. Where PIP
The configuration and operation of a television receiver including a circuit will be described. In FIG. 10, a composite video signal for a main screen is input to an input terminal 101, and a composite video signal for a small screen is input to an input terminal 102. The input composite video signal for the main screen is input to the video signal processing circuit 103 for the main screen and the synchronization signal processing circuit 104 for the main screen, and the composite video signal for the sub-screen is converted to the video signal processing circuit for the sub-screen. 105
The signal is input to the synchronization signal processing circuit 106 for the child screen.
The small-screen video signal output from the small-screen video signal processing circuit 105 is input to the memory 107. The respective synchronizing signals output from the main screen synchronizing signal processing circuit 104 and the sub-screen synchronizing signal processing circuit 106 are input to the memory control circuit 108.

[0008] The video signal for the child screen input to the memory 107 is compressed in the vertical and horizontal directions by low-speed writing / high-speed reading and address control by the memory control circuit 108. In this way, the video signal for the child screen becomes a video signal of the screen reduced by the memory 107 and is input to the signal switching circuit 109. The video signal for the main screen output from the video signal processing circuit 103 for the main screen is input to the signal switching circuit 109, and the signal switching circuit 109 controls the child screen in the main screen under the control of the system control circuit 112. To be output, the video signal for the main screen and the video signal for the sub-screen are switched and output. Further, the system control circuit 112 controls the deflection circuit 111 to project a video signal input to the cathode ray tube (CRT) 110 so as to be in a predetermined display state (mode).

In such a configuration, if the video signal for the main screen is a video having an aspect ratio of, for example, 16: 9 and the video signal for a child screen is, for example, a video having an aspect ratio of 4: 3, the CRT 110 includes: As shown in FIG. 11, a child screen is inserted into the parent screen and projected. The on / off control of the small-screen display and the control of the display position are performed by the system control circuit 112.

[0010]

A non-linear processing circuit for enlarging the horizontal display size as it approaches the left and right ends relative to the horizontal center of the display screen, and a child display in the parent screen In a television receiver provided with both a PIP circuit for inserting a screen, that is, for example, a television receiver in which a non-linear processing circuit as shown in FIG. 8 is provided in the deflection circuit 111 in FIG. When the processing by the circuit and the processing by the PIP circuit are performed at the same time, in the case of displaying the child screen at the lower right end of the main screen, as shown in FIG. 12, as the right end of the video of the child screen approaches the end, There is a problem that the image is expanded. The present invention has been made in view of such a problem, and a non-linear processing circuit that enlarges the horizontal display size as it approaches the left and right ends relative to the horizontal center of the display screen; In a television receiver having both a PIP circuit into which a small picture is inserted, a television capable of displaying a small picture without distortion even when the processing by the non-linear processing circuit and the processing by the PIP circuit are performed simultaneously. It is intended to provide a John receiver.

[0011]

SUMMARY OF THE INVENTION According to the present invention, a display screen having an aspect ratio of 16: 9 and an image having an aspect ratio of 4: 3 are displayed on the display screen. A non-linear processing circuit that enlarges a display size in a horizontal direction relatively to left and right ends with respect to a horizontal center portion of the display screen, thereby displaying an image having the aspect ratio of 4: 3 on the entire display screen. And a picture-in-picture circuit for inserting a smaller sub-screen into a parent screen displayed on the entire display screen, wherein the aspect ratio is 4: 3 by the non-linear processing circuit. A non-linear correction processing circuit that corrects the video of the child screen so as to cancel the distortion caused by the non-linear processing when displaying the video by performing the non-linear processing. As road, a memory for writing the input pixel data of the child screen is read from the memory
Of two adjacent pixel data at a predetermined mixture ratio
Mix and interpolate pixels in the horizontal direction.
And a mixer for outputting force pixel data .

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a television receiver according to the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of the television receiver of the present invention, FIG. 2 is a block diagram showing an example of an inverse correction circuit 113 in FIG. 1, and FIG.
FIGS. 4 and 4 are diagrams for explaining the operation of the inverse correction circuit 113, FIGS. 5 and 6 are diagrams for explaining the operation of the television receiver of the present invention, and FIG. 7 is a diagram of the television receiver of the present invention. It is a figure showing a PIP image.

In FIG. 1, an input terminal 101 receives a composite video signal for a main screen, and an input terminal 102 receives a composite video signal for a child screen. The input composite video signal for the main screen is input to the video signal processing circuit 103 for the main screen and the synchronization signal processing circuit 104 for the main screen, and the composite video signal for the sub-screen is converted to the video signal processing circuit for the sub-screen. 105 and the synchronization signal processing circuit 106 for the small screen. The small-screen video signal output from the small-screen video signal processing circuit 105 is input to the memory 107. The respective synchronizing signals output from the main screen synchronizing signal processing circuit 104 and the sub-screen synchronizing signal processing circuit 106 are input to the memory control circuit 108.

The video signal for the small screen input to the memory 107 is compressed in the vertical and horizontal directions by low-speed writing / high-speed reading and address control by the memory control circuit 108. In this way, the video signal for the child screen becomes the video signal of the screen reduced by the memory 107. The video signal for the child screen output from the memory 107 is input to the inverse correction circuit 113 newly added according to the present invention. As will be described in detail later, when an operation ON command is issued, the inverse correction circuit 113 performs an inverse correction of the input video signal and inputs the image signal to the signal switching circuit 109, and the operation ON command is not issued (operation OFF). Is issued), the input video signal is directly used as the signal switching circuit 10
Enter 9 The video signal for the main screen output from the video signal processing circuit 103 for the main screen is input to the signal switching circuit 109, and the signal switching circuit 109 controls the child screen in the main screen under the control of the system control circuit 112. To be output, the video signal for the main screen and the video signal for the sub-screen are switched and output. Further, the system control circuit 112 controls the deflection circuit 111 to project a video signal input to the cathode ray tube (CRT) 110 so as to be in a predetermined display state (mode).

Here, the configuration and operation of the inverse correction circuit 113 will be described. As described above, in the television receiver including the non-linear processing circuit provided in the deflection circuit 111 to increase the horizontal display size relatively to the horizontal center of the display screen as it approaches the left and right ends. The problem is that when the PIP circuit is operated when the image having the aspect ratio of 4: 3 is nonlinearly processed by the nonlinear processing circuit as shown in FIG. 9, the image of the child screen is distorted due to the effect of the nonlinear processing. there were. Therefore, when the non-linear processing circuit is operated, the video signal for the small screen may be corrected so as to cancel the effect of the non-linear processing. That is, when displaying the sub-screen at the lower right end of the parent screen, the reverse correction circuit 113 performs correction such that the left side of the video of the sub-screen is enlarged as compared to the right side (or the right side of the video of the sub-screen becomes Correction to reduce the size of the image).

FIG. 2 shows an example of the configuration of the inverse correction circuit 113. In FIG. 2, a digital video signal input from an input terminal 11 is written into one of two line memories 13 and 14 via a switch 12 by a write clock WCK.
Is written selectively. Line memory 13, 1
4 is a write clock WCK and a read clock RCK.
Are independently input, and a read enable signal (RE) is externally input and controlled as described later. Here, the number of pixel data in the horizontal period of the input video signal is 9
Assuming that 10, the write clock WCK of the line memories 13 and 14 is 4 fsc (= 14.3 MHz), and the read clock RCK is 8 fsc (= 28.6 M
Hz).

The switch 15 which operates in reverse to the switch 12 is switched for each horizontal line, and the line memory 1
Data written to 3, 14 is read clock RCK
Is read by The output of the switch 15 for selecting the output of the line memories 13 and 14 is input to the data buffer 21, and the output from the data buffer 21 is two adjacent ones.
Pieces of pixel data are output from the two output terminals. These pixel data are input to the mixer 22, and the mixer 22 generates pixel data obtained by mixing two pieces of pixel data at a mixing ratio according to a predetermined coefficient given from the outside, and outputs the pixel data from the output terminal 16. . The coefficients provided to the mixer 22 and the operation of the mixer 22 will be described later in detail.

On the other hand, the ROM or RAM 23 stores the position information of all the pixel data in the horizontal period in the form of an increment value. The increment value of this position information is based on the horizontal drive pulse (HD) input from the terminal 25. Are sequentially taken out as triggers and applied to one input terminal of the adder 24.
The output of the adder 24 is circulated to the other input terminal.
The adder 24 is an adder having a finite number of input / output bits. If the number of bits is 6, the most significant bit (MSB) becomes a read enable signal RE for the line memories 13 and 14, and The data buffer 21 is controlled as a control signal for the buffer 21. The remaining 5 bits excluding the MSB become interpolation coefficients and are applied to the control terminal of the mixer 22.

FIG. 3 shows the writing / reading operation of one of the two line memories 13 and 14 as time on the horizontal axis and the memory address on the vertical axis. , The latter one horizontal period indicates reading. The other line memory performs the reading operation when the one line memory is writing, and performs the operation opposite to the writing operation when reading. The input video signal is linearly divided into 910 data in one horizontal period by the write clock WCK, and is divided into line memories (13 or 1).
4). Line memory (1
3 or 14) is read by the read clock RCK having a frequency twice as high as the write clock WCK. Therefore, if the line memory (13 or 14) is always in a readable state (the read enable signal RE is always on), the read operation is performed. As shown by A in FIG. 3, the operation ends linearly in half of one horizontal period. Further, by applying the read enable signal RE at a cycle twice as long as the read clock RCK, the read is linearly performed as shown by B in FIG.
End in horizontal period. Further, the read enable signal R
By controlling E irregularly, the reading can be performed by using C in FIG.
An arbitrary non-linear shape can be obtained as in the curve shown by.

FIG. 4 is a conceptual diagram of conversion in a case where an input pixel data group of a video signal is non-linearly converted in the horizontal direction to output pixel data. In FIG. 4, input pixel data n, n + 1, n + 2... Are arranged by sampling horizontal video information at equal intervals. On the other hand, the output pixel data m, m + 1, m + 2... Which are equally spaced in time are arranged by sampling the video information in the horizontal direction in a non-linear manner. The output pixel data m is directly obtained from the input pixel data n, while the output pixel data m + 1 is obtained from the input pixel data n.
And the input pixel data n + 1 are obtained by mixing the input pixel data n + 1 with coefficients of 3/4 and 1/4, and the output pixel data m + 2 is obtained by mixing the input pixel data n + 1 with the coefficients of 3/8 and 5/8. The output pixel data m + 3 is obtained by dividing the input pixel data n + 1 and the input pixel data n + 2 by ４ ，,
It is obtained by mixing with a coefficient of 3/4. This is a state in which the change in pixel data from the output pixel data m to the output pixel data m + 1 is not large, but the change gradually increases as the output pixel data becomes m + 1, m + 2,. Using such a non-linear conversion, it is possible to create a state where the left side of the horizontal period of the video of the small screen is enlarged as compared with the right side.

These two coefficients represent the mixing ratio, and the sum is 1. As is clear from the above, the output pixel data group is obtained by interpolating the two adjacent pixel data of the input pixel data group by the mixer 22. Therefore, a control coefficient is externally given to the mixer 22 so that an arbitrary interpolation can be obtained. The number of control bits determines the precision of the coefficient. As described above, the finite number of bits of the adder 24 is 6, the MSB becomes the read enable signal RE, and the MSB becomes
Since the remaining 5 bits excluding are used as the interpolation coefficient, the precision of the interpolation coefficient is 1/32. In this embodiment, all the remaining 5 bits excluding the MSB are supplied to the mixer 22 and used as interpolation coefficients so as to obtain the maximum accuracy. However, in order to simplify the mixer 22, the 5 bits are used. For example, the upper three bits may be used.

By controlling the read enable signal RE at the outputs of the line memories 13 and 14, input pixel data groups n, n + 1, n + 2... Are sequentially obtained at the timing of the curve C in FIG. The data buffer 21 holds two adjacent input pixel data necessary for generating interpolation data. Therefore, the read enable signal RE of the line memory (13 or 14), the control signal of the data buffer 21, and the coefficient of the mixer 22 need to be linked and integrally controlled. The operation principle of the control method will be described in detail below.

In FIG. 2, the increment value output from the ROM or RAM 23 is input to one input terminal of the adder 24 as described above, and the output is fed back to the other input terminal. The increment value is given by the number of bits equivalent to the number of bits of the interpolation coefficient. In this embodiment, the minimum value is 0 and the maximum value is 31 (all five bits are 1). Here, when the output pixel data m + 1 is generated with a coefficient of 3/4, 1/4 from the input pixel data n, n + 1, the input pixel data n, n + 1 is held and output from the data buffer 21, and the adder is used. 24 in ROM or RAM2
By inputting the increment value 8 from 3, the coefficient 8 is given to the mixer 22. The coefficient 8 means that the coefficient is 8/32 = 1/4 for the input pixel data n + 1. Therefore, the mixer 22 outputs the input pixel data n, n +
1 is mixed at a mixing ratio of 3/4, 1/4 to generate output pixel data m + 1.

Next, in order to obtain output pixel data m + 2, the adder 24 stores the increment value 12 from the ROM or RAM 23.
Is input to the output, and a value 20 obtained by adding the previous increment value 8 and the increment value 12 is obtained, and given to the mixer 22 as a coefficient 20. Therefore, the mixer 22 outputs the input pixel data n,
n + 1 is mixed at a ratio of 3/8, 5/8 to generate output pixel data m + 2. Next, the output pixel data m +
In order to obtain 3, the adder 24 has a ROM or a RAM 23.
A further increment value 16 is input and a similar operation yields a value 36 at its output. At this time, since the maximum value is 31, the MSB changes from 0 to 1, and the lower 5 bits are 36 bits.
It becomes 4 from -32. When the MSB changes, the read enable terminals of the line memories 3 and 4 are controlled, and new input pixel data n + 2 is read. Then, the data buffer 21 discards the input pixel data n which is the old data, and newly holds and outputs the input pixel data n + 1 and n + 2. That is, the MSB of the data output from the adder 24 is a control signal for updating the pixel data stored in the data buffer 21. Then, since the coefficient 4 is given to the mixer 22, the input pixel data n + 1, n + 2 is calculated by 7 /
Mix at a ratio of 8, 1/8. In this way, the mixer 22 generates pixel data by mixing two pieces of pixel data, so that the left side in the horizontal direction can be enlarged to the right side as shown by the curve C in FIG. it can. Of course, at this time, an increment value is set so as to give an optimal coefficient that becomes the curve C.

The operation of the television receiver of the present invention configured as described above is summarized as follows. Assuming that the image of the sub-screen is a video having an aspect ratio of 4: 3 as shown in FIG. 5A, the image of the sub-screen is displayed by the inverse correction circuit 113 having characteristics as shown in FIG. The signal is corrected and output as shown in FIG. When the non-linear processing is performed, the edge of the display screen of the CRT 110 has characteristics as shown in FIG. 6B, and as a result, the image of the child screen has no distortion as shown in FIG. 5A. The image is displayed as an image having an aspect ratio of 4: 3. Therefore, in the television receiver of the present invention,
Even when the processing by the non-linear processing circuit and the processing by the PIP circuit are performed at the same time, when the child screen is displayed at the lower right end of the parent screen, the image of the child screen without distortion is displayed as shown in FIG. You.

Further, in the configuration shown in FIG. 1, the system control circuit 112 controls the deflection circuit 111 to operate so that the image having the aspect ratio of 4: 3 is nonlinearly processed and displayed on the CRT 110, and at the same time, the system control circuit 112 However, if the inverse correction circuit 113 is operated, only when the non-linear processing circuit is operated, the inverse correction is applied to the video signal for the sub-screen, so that the sub-screen which is always free from distortion regardless of the on / off state of the non-linear processing circuit. Can be displayed. By the way, in the present embodiment described above, the case where the child screen is displayed at the lower right end of the parent screen as shown in FIG. 7 has been described. However, when the child screen is displayed at the lower left end of the parent screen,
As shown by the curve D in FIG. 3, a correction may be made so that the right end of the picture of the small screen is enlarged as compared with the left end. Furthermore, although the non-linear processing circuit having a built-in deflection circuit 111 has been described, the present invention is not limited to this, and the inverse correction circuit 113 is not limited to the above.

According to the present invention, when displaying an image having an aspect ratio of 4: 3 on a display screen having an aspect ratio of 16: 9, the display size in the horizontal direction is adjusted to the left and right ends relative to the center in the horizontal direction of the display screen. A description has been given of a television receiver that includes a non-linear processing circuit that enlarges as it approaches a unit, and displays an image having an aspect ratio of 4: 3 on the entire display screen having an aspect ratio of 16: 9 by this non-linear processing. The above-mentioned prior application by the applicant of the present invention, Japanese Patent Application No. 4-2558571, discloses that when displaying an image having an aspect ratio of 4: 3 on a display screen having an aspect ratio of 16: 9, the display size in the vertical direction is changed to the display screen. A non-linear processing circuit for reducing the size as it approaches the upper and lower ends relative to the center in the vertical direction,
A television receiver that displays an image having an aspect ratio of 4: 3 on the entire display screen having an aspect ratio of 16: 9 by this non-linear processing has also been proposed. In such a television receiver, it can be easily inferred that the principle of the present invention should be used to correct the image of the small screen in the vertical direction.

[0028]

As described in detail above, the television receiver of the present invention has a display screen with an aspect ratio of 16: 9 and a horizontal display when displaying an image with an aspect ratio of 4: 3 on the display screen. A non-linear processing circuit for displaying an image having the aspect ratio of 4: 3 on the entire display screen by enlarging the display size in the direction relative to the left and right ends with respect to the center in the horizontal direction of the display screen; A picture-in-picture circuit for inserting a smaller sub-screen into a main screen displayed on the entire screen, wherein a non-linear processing circuit performs non-linear processing on an image having an aspect ratio of 4: 3 and displays the image. Since an inverse correction circuit is provided for correcting the image of the small screen so as to cancel the distortion caused by the nonlinear processing, the processing by the nonlinear processing circuit and the processing by the picture-in-picture circuit are performed. Even if management at the same time, it is possible to display a distortion-free child screen. Further, in the present invention,
As the inverse correction circuit, since it is configured such that the non-linear output pixel data in the horizontal direction by pixel interpolation in the horizontal direction input pixel data of the child screen, very complicated memory control as to change the sampling frequency There is no need to perform

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing an example of an inverse correction circuit 113 in FIG.

FIG. 3 is a diagram for explaining the operation of an inverse correction circuit 113;

FIG. 4 is a diagram for explaining the operation of the inverse correction circuit 113;

FIG. 5 is a diagram for explaining the operation of the present invention.

FIG. 6 is a diagram for explaining the operation of the present invention.

FIG. 7 is a diagram showing a PIP image according to the present invention.

FIG. 8 is a circuit diagram illustrating an example of a nonlinear processing circuit.

FIG. 9 is a diagram illustrating a display example by a non-linear processing circuit.

FIG. 10 is a block diagram showing a conventional example.

FIG. 11 is a diagram showing a PIP image.

FIG. 12 is a diagram showing a PIP image which is a problem of the conventional example.

[Explanation of symbols]

 101, 102 input terminal 103 video signal processing circuit for parent screen 104 synchronization signal processing circuit for parent screen 105 video signal processing circuit for child screen 106 synchronization signal processing circuit for child screen 107 memory 108 memory control circuit 109 signal switching Circuit 110 CRT 111 Deflection circuit 112 System control circuit 113 Reverse correction circuit

Claims (1)

(57) [Claims] 1. A display screen having an aspect ratio of 16: 9 and a display size in a horizontal direction when displaying an image having an aspect ratio of 4: 3 on the display screen, relative to a horizontal center portion of the display screen. A non-linear processing circuit for displaying the image having the aspect ratio of 4: 3 on the entire display screen by enlarging the image as it approaches the left and right ends, and a smaller sub-screen in the parent screen displayed on the entire display screen And a picture-in-picture circuit for inserting a picture, wherein when the picture having the aspect ratio of 4: 3 is nonlinearly processed and displayed by the nonlinear processing circuit, the picture of the child screen is displayed in the nonlinear form. A reverse correction circuit that corrects so as to cancel the distortion due to the processing, as the reverse correction circuit, the input pixel data of the child screen
Write memory and pixel data read from this memory.
Data adjacent to each other at a predetermined mixing ratio
Interpolates pixels in the horizontal direction, and outputs non-linear output pixel data in the horizontal direction.
A television receiver, comprising: a mixer that outputs data .