JPH0799451A - D/a converter - Google Patents

Abstract

PURPOSE:To provide D/A converter suitable for large scale circuit integration whose D/A converter circuit does not require high precision. CONSTITUTION:A digital filter 10 and a noise shaper 11 convert a digital input into a digital signal with a high sampling frequency and less bit number, a decoder 12 converts the digital signal into a corresponding one-bit signal strings, each string is converted into an analog signal at a 1-bit D/A converter array 13, an analog adder 14 sums the outputs of the D/A converter array 13 to obtain an analog output. An output of the decoder is an output in which 1-bit signals of the number corresponding to the output of the noise shaper are circulated and each 1-bit D/A converter having a relative error opposite to adjacent bits of the decoder output is arranged to eliminate the correlation between the specific 1-bit signal and the output of the noise shaper and noise and distortion are reduced by cancelling the relative error among the 1-bit D/A converters.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A (digital / analog) converter for converting a digital signal into an analog signal, and in particular, performs D / A conversion at a sampling frequency higher than the sampling frequency of a digital input signal. The present invention relates to an oversampling D / A converter.

[0002]

2. Description of the Related Art As one of D / A converters, a D / A converter using a noise shaper and PWM has been reported. A D / A converter of this type that has been reported in the past will be described with reference to FIG. Regarding this technology, refer to "National Technical Report (Vol. 34, No. 2,
April 1988) pp.40-45 ”.

FIG. 9 is a block diagram showing an example of a conventional D / A converter. 10 is a digital filter (DF)
That is, the sampling frequency fs of the input digital signal is multiplied by n (n ≧ 2). Where n =
64. 11 is a noise shaper (NS),
The word length of the digital signal output from F10 is limited, and the frequency characteristic of noise is changed to a predetermined characteristic. Here, a noise shaper with a third-order characteristic is used.
The output Y with respect to the input X is represented by (Equation 1).

[0004]

[Equation 1]

The output Y is assumed to have an 11 (= p) level output. 70 is a pulse width modulation circuit (PWM)
And converts it into a 1-bit pulse signal having 11 pulse widths corresponding to the digital signal output from the NS 11, and outputs it as an analog signal. D / A of FIG.
The converter sets the sampling frequency to 64 fs and 11 levels by the DF10 and NS11, and then further at least 704 times (64 x 64) by the PWM70.
This is a so-called oversampling type D / A conversion device for converting an analog signal using the clock of 11) and converting a digital signal into an analog signal at a higher sampling frequency.

FIG. 10 shows the result of computer simulation of the output signal spectrum of the D / A converter shown in FIG. For simplicity, signals of 0 to 2 fs are shown here. As described above, although only a 11-level digital signal is converted into an analog signal,
As shown in 0, the NS 11 provides a dynamic range (DR) of 120 dB or more in the signal band of 0 to fs / 2.

[0007]

However, in the configuration shown in FIG. 9, the PWM 70 requires a clock of at least 704 fs. For example, in the case of a sampling frequency fs = 48 kHz widely used in digital audio, the clock becomes an extremely high clock of 704 fs = 33.792 MHz, and there is a practical problem such as a need for countermeasures against electromagnetic interference and electromagnetic interference.

When D / A conversion is performed by a method other than PWM, it is possible to operate at a clock lower than that in PWM. For example, a D / A conversion circuit using a resistor string may be used. However, for this purpose, there is a problem that it is difficult to manufacture the D / A conversion circuit because extremely high relative accuracy is required for the resistor string.

The present invention solves the above-mentioned problems of the prior art, does not require a high clock unlike PWM, and
An object of the present invention is to provide a D / A conversion device that does not require high accuracy in the / A conversion circuit.

[0010]

To achieve this object, the present invention has the following constitution.

(1) A digital filter that multiplies the sampling frequency of an input digital signal by n times (n ≧ 2), and the output of the digital filter is input to change the word frequency and the frequency characteristic of noise to a predetermined characteristic. A noise shaper for making the input, a decoder for receiving the output of the noise shaper and converting it into a 1-bit signal string corresponding to the value of the input, and a 1-bit D / A converter string for converting the output of the decoder into an analog signal , The 1-bit D / A
An analog adder that integrates the outputs of the converter array, and outputs at least (p-1) the output of the decoder corresponding to the p-value (p is an integer) value output from the noise shaper. One 1-bit signal string is output, and the 1-bit signal string is cyclically allocated so that the allocation start position is next to the final allocation position of the 1-bit signal string one sample data before. D / A converters arranged such that adjacent 1-bit D / A converters in the 1-bit D / A converter train having opposite relative errors are assigned to adjacent bits of the decoder output.
A conversion device.

(2) Each 1-bit D / A converter in the 1-bit D / A converter array is output in the order of output levels D1, D2, D3, D.
4, ..., Dm-3, Dm-2, Dm-1, Dm, the 1-bit D for each bit of the decoder output signal sequence
/ A converter array assignment is D1, Dm-1, D3, Dm-3, ...
.., D4, Dm-2, D2, Dm are arranged in this order as a D / A converter.

(3) When the 1-bit D / A converters in the 1-bit D / A converter array are arranged in a line with exactly the same shape and arranged in an LSI to form an LSI, each of the 1-bit D / A converters , D1, D2, D3, D4, ..., Dm-3, Dm-2, D
When m-1 and Dm, the allocation of the 1-bit D / A converter train to each bit of the output signal train of the decoder is D
1, Dm-1, D3, Dm-3, ..., D4, Dm-2, D2, Dm
The D / A converters are arranged in this order.

[0014]

According to the present invention having the above-described configuration, (1) D / A conversion is performed by converting the output of the noise shaper into a 1-bit signal string by the decoder and further converting it into an analog signal by the 1-bit D / A converter string. The sampling frequency at that time may be the same as the sampling frequency of the digital output of the noise shaper, and it is possible to operate with a clock much lower than that of PWM.

(2) Correlation between the output value of the noise shaper and a specific 1-bit D / A converter by the decoder allocating the output of the noise shaper so as to circulate to the plurality of 1-bit D / A converters. Is lost.

(3) The 1-bit D / A converter array is arranged so as to reduce the effective value of noise caused by the relative error of each 1-bit D / A converter. Each one by this
Even if there are variations in the outputs between the bit D / A converters, it is possible to reduce the occurrence of distortion and noise in the signal band.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a D / A converter according to the present invention. In FIG. 1, 10 is a digital filter (DF) and 11 is a noise shaper (NS), both of which have the same configurations and functions as those shown in FIG. A decoder (DEC) 12 outputs m 1-bit signals corresponding to the digital signals output from the NS 11. Reference numeral 13 is a 1-bit D / A converter string (DAC), which is a first D / A converter (DAC-
From 1) to the m-th D / A converter (DAC-m), all are composed of m uniform 1-bit D / A converters. 1
An analog adder 4 synthesizes m analog signals output from the DAC 13 and outputs them as analog signals. Reference numeral 15 is a D / A conversion circuit, which includes a DAC 13 and an analog adder 14. The D / A converter of FIG. 1 sets the digital input signal to the sampling frequency of 64 fs and 11 (= p) level by the DF10 and NS11, and then makes m number of 1-bit signals by the DEC12, and further
The A / A conversion circuit 15 converts the analog signal into an analog signal, which is a so-called oversampling D / A conversion device that converts a digital signal into an analog signal at a higher sampling frequency.

An example of the DEC 12 of FIG. 1 is shown in FIG. In FIG. 2, reference numeral 20 denotes a pointer, which outputs the remainder of the accumulated value of the input signal. Reference numeral 21 denotes a ROM (read-only memory) which outputs m-bit data corresponding to an address whose input signal is lower and output of the pointer 20 is upper. Here, it is assumed that m = 10 (= p-1). The operation of FIG. 2 will be described.
11 level signal (0 to 1) output from NS11 of
0) is accumulated and the remainder of 10 is obtained and output. Therefore, there are 10 outputs, 0 to 9. Next, the address whose input signal is lower and the output signal of the pointer 20 is upper is R.
Input to OM21 and obtain 10-bit data. This one
The 0-bit data represents 10 1-bit signals. The relationship between the address (decimal number) and the data (binary number) at this time is shown in (Table 1).

[0020]

[Table 1]

Explaining (Table 1), 10-bit data is "1" as indicated by the lower address, that is, the numerical value of the input signal, and the sum of each bit is equal to the input signal. The lower address, that is, the pointer 20
The value of the output signal of is shifted to the left as shown, and the overflowing digits are circulated so that they appear from the right. By defining the ROM 21 as in (Table 1), data is output as in (Table 2).

[0022]

[Table 2]

As can be seen from (Table 2), "1" indicated by the numerical value of the input signal is output so as to circulate the 10-bit data.
It indicates that there is no correlation with a specific bit of the bit data. Therefore, even if there are variations in the outputs of the 1-bit D / A converter rows 13 to which the 10-bit data are respectively connected, it is possible to reduce distortion and noise in the signal band.

An example of the D / A conversion circuit 15 of FIG. 1 is shown in FIG. In FIG. 3, 13 is a 1-bit D / A converter array (DA
C) and 14 are analog adders, and 15 is a D / A conversion circuit, which correspond to FIG. Reference numeral 30 denotes a switch, which switches to be connected to Vref when the value of the digital input signals b1 to bm is "1" and to be connected to GND when the value is "0". Reference numeral 31 is a capacity. The operation of FIG. 3 will be described. According to "1" and "0" of the digital input signal, the switch is switched to Vref or GND, and each capacitor 31
The output voltage is obtained by redistributing the charges among the capacitors 31 with the electrode on one side thereof being common. That is, a charge redistribution type D / A converter is formed by an array of capacitors and switches. Now, the capacitance value of the capacitance 31 of the DAC-1 is C1, the capacitance value of the capacitance 31 of the DAC-2 is C2, ..., D
When the capacitance value of the capacitor 31 of AC-m is Cm, the analog output voltage Vo is obtained by (Equation 2).

[0025]

[Equation 2]

Since the DAC 13 has a uniform structure, the capacitance value of the capacitor 31 is also C1 = C2 = ... = Cm, and the analog output is "1" of the digital input signal.
The voltage value is output in proportion to the number of signals.

In an actual circuit, it is impossible to manufacture the capacitor 31 of the DAC 13 completely uniformly, and there is some relative error. In this case, as is clear from (Equation 2), a voltage value that depends not only on the number of signals that are "1" in the digital input signal but also on the position is output.

Here, the relationship between the analog output and the relative error between the 1-bit D / A converter array (DAC) will be described.
Now, the output of DAC-1 is D1, and the output of DAC-2 is D
2, ..., When the output of the DAC-m is Dm and the average output of each DAC is D, the relative error εi of each DAC (i = 1, 2, ...
・, M) has the relationship of (Equation 3).

[0029]

[Equation 3]

Of the outputs of the DEC 12 of FIG. 1, the probability that the number of signals that are "1" becomes 1 is P1, the probability that it is 2 is P2, ... To Pm
Then, the effective value εrms of the relative error included in the analog output is (Equation 4).

[0031]

[Equation 4]

In (Equation 4), the first term on the right side is each DAC.
The relative error between the DACs must be reduced in order to reduce this term. However, from the second term on the right side, the D that is combined when the number of DACs corresponding to the output of the DEC 12 is combined and outputted.
This term is an error caused by a relative error between ACs, and this term can be reduced by combining DACs. As is clear from (Equation 4), in order to reduce the second term on the right side and thereafter, the sum of the relative errors of the adjacent DACs may be reduced. To that end, for the adjacent bits of the output signal string of the DEC 12, With opposite relative error (negative relative error to positive relative error, or vice versa)
Should be arranged so that

In the D / A converter of FIG. 1, DF10 and NS
11, the digital input signal is sampled at a sampling frequency of 6
After setting 4 fs and 11 levels, when the DEC 12 produces 10 1-bit signals, 1-bit D / A converter array 1
FIG. 4 shows a result obtained by simulating the output signal spectrum in the case where 3 is, for example, as shown in (Table 3) and the plus and the minus alternate with a variation of ± 1.0% at maximum. For simplification, a signal of 0 to 2 fs is shown here.

[0034]

[Table 3]

As shown in FIG. 10, the output from the NS 11 can obtain a dynamic range of 120 dB or more in the signal band of 0 to fs / 2, but in FIG. 4, the dynamic range is about 102 dB. It can be seen that the performance of 16-bit precision or higher is obtained despite the variation of up to ± 1.0% in the bit D / A converter array 13. In addition, FIG. 5 shows the result of the simulation of the output signal spectrum in the case where the plus and the minus do not alternate with the variation of maximum ± 1.0% as shown in (Table 4).

[0036]

[Table 4]

In FIG. 5, the dynamic range is about 99 dB, and if the variation in the 1-bit D / A converter array 13 cannot be taken into consideration, the dynamic range is degraded by 3 dB. On the other hand, FIG. 6 shows a result obtained by simulating the output signal spectrum when the output is such that the data does not circulate, for example, when the output of the pointer 20 is fixed to 0 regardless of the input. As shown in FIG. 6, noise is increased, harmonic distortion is generated, and the dynamic range is about 7 as compared with FIGS.
It can be seen that it is greatly deteriorated to 0 dB.

Further, here, 1-bit D / which has a relative error contradictory to the adjacent bit of the output of the decoder 12
Although the A converter 13 is assigned, as another embodiment of the present invention, the 1-bit D / A converter outputs D1, D2, D3, D4, ..., Dm-3, Dm in the order of output levels. -2, D
When m-1 and Dm, the allocation of the 1-bit D / A converter train to each bit of the output signal train of the decoder 12 is D
1, Dm-1, D3, Dm-3, ..., D4, Dm-2, D2, Dm
You can arrange them in this order. For example, as a result of simulating the output signal spectrum in the case where the output of the 1-bit D / A converter array 13 varies up to ± 1.0% in the order of the output levels as shown in (Table 5). Is shown in FIG.

[0039]

[Table 5]

In FIG. 7, the dynamic range is about 106 dB, which is the highest characteristic among all combinations of arrangements. In particular, in this method, when the output level of the 1-bit D / A converter is known, it is possible to obtain the maximum dynamic range simply by using the above arrangement.

Next, still another embodiment of the present invention will be described. Generally, when a 1-bit D / A converter array having uniform characteristics is to be realized by an LSI, each 1-bit D / A converter array
By arranging the / A converters in the same shape and arranging them in a line, it is possible to reduce the deterioration of the relative error due to the error of the planar processing accuracy, and to make a highly accurate 1-bit D / A converter line. You can LSI of the D / A conversion circuit shown in FIG.
An example of the mask pattern is shown in FIG. In FIG. 8, reference numeral 30 is a switch, 31 is a capacitor having a two-layer polysilicon structure in which two layers of polysilicon are used for an upper electrode and a lower electrode, and 13 is a 1-bit D / A converter array, each 1 Bit D
The A / A converters are arranged in a line and have the same shape, and each corresponds to FIG. In this D / A conversion circuit, the relative error of the 1-bit D / A converter array is determined by the relative accuracy of the capacitance, and the capacitance value is the dielectric constant of the insulating layer between the upper electrode and the lower electrode, the thickness of the insulating layer, and the electrode. Is determined by the area of. LS
Since the dielectric constants of the insulating layers are the same in the chip of I, the factors that deteriorate the relative accuracy of the capacitance are the difference in the thickness due to the inclination of the insulating layer and the difference in the electrode area due to the error in the processing accuracy. Regarding the factor due to the error of the processing accuracy, the capacitance ratio accuracy can be improved by arranging the capacitors in the same shape in one row and further increasing the capacitance area as much as possible. Does not directly depend on the shape, arrangement, or area of the capacitance. Here, the inclination of the insulating layer will be considered separately for the following three cases.

(1) The insulating layer has capacitances C1, C2, ..., C
When sequentially inclined with respect to m, the capacitance value of each capacitance also increases or decreases in inverse proportion to the inclination.

(2) The insulating layer has capacitances C1, C2, ..., C
When sloping in a wavy shape with respect to m, the capacitance value of each capacitance is also distributed in inverse proportion to the slope.

(3) The insulating layer has capacitances C1, C2, ..., C
When tilted in a small wavy shape with respect to m, each capacity is distributed with random specific accuracy.

When the capacitance is distributed as shown in (1), the capacitance C
1, C2, C3, C4, ..., Cm-3, Cm-2, Cm-1, Cm
C for each bit of the output of the decoder with respect to the arrangement order of
1, Cm-1, C3, Cm-3, ..., C4, Cm-2, C2, Cm
The maximum dynamic range can be obtained by allocating in the order of. In addition, when the capacitances are distributed as shown in (2), the optimal placement differs depending on the distribution state in order to obtain the maximum dynamic range, and it cannot be determined as one, but the relative error between the capacitances adjacent to each other is the same. There is a high possibility of having polarity, and the second and subsequent terms on the right side of (Equation 4) do not become smaller. Therefore, when the arrangement as shown in (1) is adopted, the distribution of the ratio accuracy is apparently close to random, and there is a high possibility that the second and subsequent terms on the right-hand side of (Equation 4) are canceled out to be reduced. When the capacitances are randomly distributed as in (3), the dynamic range does not change significantly even if the arrangement order of the capacitances is changed. Therefore, in order to obtain high performance considering all cases, the capacitances C1, C2, C3, C4, ...
.., Cm-3, Cm-2, Cm-1, Cm are arranged in the order of C1, Cm-1, C3, Cm-3 ,.
.., C4, Cm-2, C2, Cm may be assigned in this order.

The D / A converter is constructed as described above. Here, the NS 11 represented by (Equation 1) is used, but it goes without saying that different orders and characteristics may be used as long as they function as a noise shaper. In addition, the configuration of the DEC 12 shown in FIG. 3 and (Table 1)
The ROM data and the like are only examples for explanation, and are not limited to these. Furthermore, the output bit number m of the DEC 12 (that is, the number m of the 1-bit D / A converters 13) for each of the p outputs of the NS 11 has been described as (p-1), but these are all minimum. In some cases, m may be more than this, depending on the circuit configuration and the like.

[0047]

As described above, in the D / A converter of the present invention, the sampling frequency at the time of D / A conversion may be the same as the sampling frequency of the digital output of the noise shaper, which is much lower than PWM. It has an excellent feature that it can operate with a clock.

Further, since the decoder allocates the output of the noise shaper so as to circulate to the plurality of 1-bit D / A converters, the correlation between the output value of the noise shaper and a specific 1-bit D / A converter. Moreover, since the 1-bit D / A converters are arranged so as to cancel the relative error, the effective value of noise caused by the relative error can be reduced,
Even if there is a variation in the output between the 1-bit D / A converters, it has an excellent feature that distortion and noise in the signal band can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a D / A conversion device according to the present invention.

FIG. 2 is a block diagram showing an example of a decoder 12 in FIG.

FIG. 3 is a circuit diagram showing an example of a D / A conversion circuit 15 of FIG.

FIG. 4 is an output signal spectrum in the D / A conversion device of FIG. 1 when the variation of the 1-bit D / A converter array alternates between plus and minus.

FIG. 5 is an output signal spectrum in the D / A conversion device of FIG. 1 when the variation of the 1-bit D / A converter array is such that plus and minus do not alternate.

6 is an output signal spectrum when the output of the pointer 20 is fixed to 0 regardless of the input in the D / A converter of FIG.

FIG. 7 is an output signal spectrum of the D / A converter of FIG. 1 when the variation of the 1-bit D / A converter array is as shown in (Table 5).

8 is a pattern diagram showing an example of an LSI mask pattern of the D / A conversion circuit of FIG.

FIG. 9 is a block diagram showing an example of a conventional D / A conversion device.

FIG. 10: Obtained by computer simulation
Output signal spectrum of D / A converter of FIG.

[Explanation of symbols]

 10 Digital Filter (DF) 11 Noise Shaper (NS) 12 Decoder (DEC) 13 1-bit D / A Converter Sequence (DAC) 14 Analog Adder 15 D / A Conversion Circuit 20 Pointer 21 ROM (Read Only Memory) 30 Switch 31 capacity 90 pulse width modulation circuit (PWM)

Claims (3)

[Claims] 1. A digital filter that multiplies a sampling frequency of an input digital signal by n times (n ≧ 2), and receives the output of the digital filter as input, and changes the frequency characteristic of noise to a predetermined characteristic with word length limitation. A noise shaper, a decoder that inputs the output of the noise shaper, and converts the output of the decoder into a 1-bit signal string, and a 1-bit D / A converter string that converts the output of the decoder into an analog signal , An analog adder that integrates the outputs of the 1-bit D / A converter array, and the output of the decoder corresponds to a signal having p (p is an integer) values output from the noise shaper. To output at least (p-1) 1-bit signal sequence, and the allocation start position of the 1-bit signal sequence is 1 sample data before 1 sample data. So that it is cyclically allocated so as to be positioned next to the final allocation position of the input signal sequence, and contradictory relative errors in the 1-bit D / A converter sequence with respect to adjacent bits of the decoder output. D / A arranged so that a 1-bit D / A converter with
A converter. 2. Each 1-bit D of a 1-bit D / A converter string
Set the / A converter in the order of output levels D1, D2, D3, D4, ...
.., Dm-3, Dm-2, Dm-1, and Dm, the allocation of the 1-bit D / A converter train to each bit of the output signal train of the decoder is D1, Dm-1, D3 ， Dm-3 ， ・ ・ ・ ，
The D according to claim 1, wherein D4, Dm-2, D2 and Dm are arranged in this order.
/ A converter. 3. A 1-bit D / A converter string for each 1-bit D
L / A converters are arranged in a line with exactly the same shape
Convert to SI and set each 1-bit D / A converter to D
1, D2, D3, D4, ..., Dm-3, Dm-2, Dm-1, Dm
, The allocation of the 1-bit D / A converter train to each bit of the decoder output signal train is D1, Dm-1,
The D / A converter according to claim 1, wherein D3, Dm-3, ..., D4, Dm-2, D2, Dm are arranged in this order.