KR100345668B1 - Digital to analog converter for minimizing error due to mismatch of capacitors - Google Patents

Abstract

The present invention is to provide a D / A conversion device that minimizes the harmonic distortion caused by mismatch between the capacitors by a random decoding method, for this purpose the present invention is provided with a plurality of capacitors inside due to mismatch between the capacitors A digital-to-analog conversion device with minimized harmonic distortion, comprising: N-bit sigma-delta conversion means for receiving a digital input signal from the outside and converting the sigma-delta into a N-bit signal (N is a natural number); Decoding means for receiving and decoding the N-bit signal output from the sigma-delta conversion means and outputting 2 ^N signals; A random generation circuit section for randomizing the 2 ^N signals output from the decoding means; And switched-capacitor filtering means for outputting a final analog output signal converted to the digital input signal after performing a low pass filtering operation by receiving the randomized signal output from the random generation circuit unit.

Description

DIGITAL TO ANALOG CONVERTER FOR MINIMIZING ERROR DUE TO MISMATCH OF CAPACITORS

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal converter, and more particularly, to a digital-to-analog converter (hereinafter referred to as a D / A converter) which minimizes performance degradation due to mismatch between capacitors inevitably occurring in a process.

As is well known, D / A converters are devices for converting digital signals into analog signals.

In a typical D / A converter, a mismatch between capacitors occurs in a semiconductor process, and this mismatch causes harmonic distortion from the D / A converter. Therefore, such a conventional D / A converter has a problem in that the signal-to-harmonic distortion ratio (Signal-to-Harmonic distortion rate) is reduced to reduce the overall performance.

On the other hand, D / A converters for high resolution speech signals, which are frequently used in speech signal processing, typically use sigma-delta modulation. The sigma-delta transformation is already well known technology, and a detailed description thereof is omitted here.

1 is a D / A converter having a 1-bit sigma-delta converter of a sigma-delta conversion method, and a 1-bit sigma-delta converter 10 for receiving a digital input signal and converting a sigma-delta, and a sigma-delta converter. And a switched-capacitor filter 12 for outputting an analog output signal after performing a low pass filtering operation on the 1-bit signal output from (10).

Specifically, the 1-bit sigma-delta converter 10 receives a digital input signal from the outside and converts the digital input signal into a 1-bit signal having a high noise level in the high frequency region as shown in FIG. 2 ((a) of FIG. 2). . Subsequently, the switched-capacitor filter 12 low pass filters the 1-bit signal from the sigma-delta converter 10 and outputs it as an analog output signal. However, even after the filtering operation through the switched-capacitor filter 12, the noise level is still high as shown in FIG.

In order to overcome this problem, it may be configured by increasing the order of the switched-capacitor filter 12, but in this case, the filtering operation of the filter itself is likely to become unstable, and the transfer function of the entire filter is changed by mismatch between capacitors. Another problem arises, such as increased degree.

Therefore, recently, a method of lowering a noise level by employing a sigma-delta converter that outputs multiple bits when configuring a D / A converter has been used.

3 is a D / A converter having a sigma-delta converter with a multi-bit output, an N-bit sigma-delta converter 20 for receiving a digital input signal and converting a sigma-delta into a multi-bit signal, and a sigma-delta converter. after performing a second low pass filtering operation for the ^N signals output from the decoder 22 and the decoder 22 for the input received decoding the N-bit signal and outputs a second ^N signals output from the converter 20 It consists of a switched-capacitor filter 24 which outputs an analog output signal.

When the number of output bits increases, as in the N-bit sigma-delta converter 20 of FIG. 3, the noise component in the high frequency region of the signal output from the sigma-delta converter 20 decreases by (6.02 × number of output bits). (C) of FIG. 4, therefore, the noise level after the filtering operation through the switched-capacitor filter 12 also slightly lowers the noise level as shown in FIG. 4 (d).

However, the D / A converter using the N-bit sigma-delta converter 20 as shown in FIG. 3 converts the digital signal into an analog signal using a plurality of capacitors as shown in FIG.

FIG. 5 is an internal circuit diagram of the switched-capacitor filter of FIG. 3 and includes a plurality of capacitors connected in parallel between an operational amplifier 30 and an inverting input terminal (−) and a reference voltage terminal Vref of the operational amplifier 30. (C1, C2, C3, ..., Cn), and a resistor (R) and a capacitor (Cf) for adjusting the output level of the analog signal of the operational amplifier 30.

In general, a high-precision capacitor such as the capacitor of FIG. 5 is formed by stacking two poly layers into a stack, and using the capacitance between the two layers. All conventional semiconductor processes are performed in terms of time and space. This will cause mismatch between the capacitors. The main cause of this mismatch is that the thickness of the oxide layer (oxide) that electrically separates the two poly layers is not constant, and as shown in FIG. 6, the thickness (X) of the oxide layer is monotonically increased in a constant direction or is thick in a specific region. This is because an error in the capacitance of a capacitor composed of two poly layers occurs due to the thickness difference of the oxide layer by having a distribution such as decreases as the distance increases from.

Meanwhile, the D / A converter having such a configuration charges the input value corresponding to the input value among the plurality of input capacitors C1, C2, C3, ..., Cn, as shown in FIG. Other capacitors Cf and switching (S1, S2, ..., Sn, Sf) are converted into an analog signal. In addition, the conventional D / A converter uses the decoder 22 to select the number of capacitors charged with the digital signal input from the N-bit sigma-delta converter 20 and charge the plurality of capacitors sequentially from the left. . As an example, a 3-bit D / A converter is shown in Table 1 below.

Digital input signal The output of the decoder Final analog output signal 000 0000000 0 001 0000001 1/8 010 0000011 2/8 011 0000111 3/8 100 0001111 4/8 101 0011111 5/8 110 0111111 6/8 111 1111111 7/8

When the digital input signal is converted into an analog output signal as shown in Table 1 using the D / A converter of FIG. 3, an error component is included in the digital input signal due to mismatch between capacitors. . That is, it is as if the digital input signal had an error corresponding to the mismatch of the capacitors. This error component causes distortion of the signal component. Analyzing the frequency component of the analog output signal output from the D / A converter with this error, harmonic components of the frequency of the digital input signal occur. That is, mismatch between capacitors will cause harmonic distortion of the entire D / A converter.

Using a typical CMOS process, the mismatch between these capacitors is about 0.1%, and the resolution of the D / A converter is about 10 bits. Therefore, implementing a D / A converter with 10-bit or higher resolution requires a separate design technique that can use a higher precision process or eliminate harmonic distortion.

An object of the present invention is to provide a D / A conversion apparatus which minimizes harmonic distortion caused by mismatch between capacitors in a random decoding scheme.

1 is a block diagram of a D / A converter with a 1-bit sigma-delta converter in a sigma-delta conversion scheme.

2 is a signal and noise characteristic diagram for a 1 bit signal from a 1 bit sigma-delta converter and a signal from a switched-capacitor filter in the D / A converter of FIG.

3 is a block diagram of a D / A converter having a sigma-delta converter with a multiple bit output.

4 is a signal and noise characteristic diagram for a signal from a multi-bit sigma-delta converter and a signal from a switched-capacitor filter in the D / A converter of FIG.

5 is an internal circuit diagram of the switched-capacitor filter of FIG.

6 is a characteristic diagram of two types causing mismatch of capacitors according to process.

7 is a block diagram of a D / A converter according to an embodiment of the present invention.

FIG. 8 is a diagram of a unit random generation circuit unit constituting the random generation circuit unit of FIG. 7 according to an embodiment of the present invention; FIG.

FIG. 9 is an internal circuit diagram of a control signal generation unit generating control signals Pass and Exchange input to the unit random generation circuit unit of FIG. 8.

Fig. 10 is a block diagram of a random generation circuit unit constructed by taking an example where an output of a sigma-delta converter is 3 bits.

* Description of the main parts of the drawing

40: N-bit sigma-delta converter

42: decoder

44: random generation circuit

46: switched capacitor filter

In order to achieve the above object, the present invention provides a digital-to-analog converter having a plurality of capacitors therein and minimizing harmonic distortion caused by mismatch between the capacitors. N-bit sigma-delta conversion means for sigma-delta conversion into a signal of which N is a natural number; Decoding means for receiving and decoding the N-bit signal output from the sigma-delta conversion means and outputting 2 ^N signals; A random generation circuit section for randomizing the 2 ^N signals output from the decoding means; And switched-capacitor filtering means for receiving a randomized signal output from the random generation circuit unit and performing a low pass filtering operation to output a final analog output signal converted to the digital input signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

The present invention converts the harmonic distortion into random noise to minimize the effects of mismatches between capacitors occurring in the process. In other words, when charging the number of capacitors corresponding to the signal output from the decoder, instead of charging the capacitors according to a certain rule, randomizing them and converting the capacitor mismatch error into a random error causes the error corresponding to the harmonic distortion to age. It is evenly distributed over the Nyquist frequency band to minimize noise. For example, consider a digital-to-analog converter with an 8-bit switched-capacitor filter. The decoder described above has 256 output signals, Each output signal is connected to 256 capacitors of the same size, and dozens of capacitors are mismatched with other capacitors due to other problems such as process and the like. To charge the capacitor when charging If the capacitor is charged according to a certain rule, the value converted to analog by the digital-to-analog converter always outputs an analog value having the error of the mismatched capacitor, and thus an error is generated from the actual data value. If the percentage occurs, it becomes difficult to implement a digital-to-analog converter using a switched-capacitor filter having a resolution of more than 10 bits, but according to the present invention, the output of the decoder is converted into random data having no regular rules and thus the capacitor Charging does not cause the capacitor to be mismatched and all capacitors are charged with the same probability at any decoding value, thereby reducing the error caused by capacitor mismatch. This results in a high resolution digital-to-analog converter with more than 16 bits. phrase It can be manifested. In other words, the present invention has an effect that a digital-to-analog converter using a switched-capacitor filter can be implemented with high resolution even with a conventional structure and process.

FIG. 7 is a block diagram of a D / A converter according to an embodiment of the present invention. An N-bit sigma-delta converter 40 and a sigma- sigma-delta converter are applied to a multi-bit signal by receiving a digital input signal. A decoder 42 for receiving and decoding an N-bit signal output from the delta converter 40 and outputting 2 ^N signals, and a random generation circuit unit for randomizing the 2 ^N signals output from the decoder 42 ( 44 and a switched-capacitor filter 46 for performing a low pass filtering operation in response to a signal output from the random generation circuit unit 44 and then outputting an analog output signal.

Referring to the drawings, an exemplary operation of the present invention will be described below.

The digital input signal input to the D / A converter of the sigma-delta conversion method of the present invention is converted into an N-bit signal in which a noise component exists in a high frequency band through the N-bit sigma-delta converter 40, and this N-bit The signal is input to the decoder 42 and decoded into 2 ^N signals. The decoded signal is input to the random generator circuit 44 to remove the regularity of the input signal and finally converted into an analog output signal by the switched-capacitor filter 46. In the case of the final analog output signal converted as described above, an error due to mismatch between a plurality of capacitors constituting the switched-capacitor filter 46 is converted into a random error so that it does not generate harmonic distortion unlike a conventional D / A converter. .

The random error is uniformly distributed in the Nyquist frequency band, and the sigma-delta D / A converter using the oversampling method has a frequency band versus a Nyquist frequency band (1/2 × sampling frequency) of the signal. This very low rise in the noise level of the random error due to capacitor mismatch in the signal band is very small, resulting in a significant performance improvement, especially when compared to the performance degradation caused by harmonic distortion, which occurs when using conventional methods.

Accordingly, in the present invention, a unit random generator as shown in FIG. 8 is provided to convert 2 ^N signals output from the decoder 42 into random signals.

8 is a unit random generation circuit unit constituting the random generation circuit unit of FIG. 7 according to an embodiment of the present invention, and has two inputs (in1 and in2) and two outputs (o1 and o2) and generates unit random. Combining the previous input to the circuit section and the current input to the current unit random generation circuit section, output the input signals in1 and in2 as it is or output the input signals in1 and in2. (o2, o1). The operation of the unit random generation circuit unit is controlled by control signals Pass and Exchange.

FIG. 9 is a control signal generator for generating control signals Pass and Exchange input to the unit random generation circuit of FIG. 8, and receives one input signal in1 and another input signal in2. An exclusive OR gate 48 for exclusive OR, a D flip-flop 50 for edge triggering the output T1 of the exclusive OR gate 48 to the output terminal Q in response to the clock signal CLK, and the exclusive OR An exclusive OR gate 52 for receiving the output signal T1 of the OR gate 48 and the signal from the output terminal Q of the D flip-flop 50 and ORing the two signals exclusively with each other to output a control signal Exchange. And an inverter 54 which inverts the output signal of the exclusive OR gate 52 and outputs another control signal Pass.

When only one of the two input signals in1 and in2 is configured to be '1', the control signal generator configured as described above outputs the output signal T1 to '1' through the exclusive OR gate 48, and the D flip-flop ( 50) and the previous output is enabled when the control signal (Exchange) is enabled through the exclusive OR gate, then another control signal (Pass) is enabled, the previous output is enabled by the control signal (Pass) After that, the regularity of the input signal is eliminated by enabling the control signal (Exchange) to be output.

FIG. 10 is a random generation circuit unit configured with an example in which an output of a sigma-delta converter is 3 bits. The unit random generation unit illustrated in FIG. 10 is the same as that of FIG. 8, and the unit random generation unit is the FFT (Fast Fourier Transform). It is composed of a three-stage array using a butterfly-type connection as in the above, through which the eight input signals (in0 to in7) output from the decoder 42 are combined with the current input and the previous input signal. By randomizing through, the regularity of the output signal of the decoder is removed, and the random signal is converted into a random signal to improve the performance of the D / A converter having an oversampling sigma-delta converter.

The technique of minimizing harmonic distortion caused by mismatch between capacitors by the random decoding scheme as described above is applicable to a conventional Nyquist D / A converter.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention as described above, by using a random decoding method to minimize the harmonic distortion caused by the mismatch between the capacitors have the effect of implementing a 16-bit or higher high-resolution D / A converter in a process having a resolution of about 10 bits have.

The technique of the present invention can be applied to all D / A converters using capacitors, and in particular, a high performance improvement effect can be obtained in an oversampling D / A converter having a very high sampling frequency.

Claims (4)

In the digital-to-analog converter having a plurality of capacitors inside to minimize the harmonic distortion caused by mismatch between the capacitors, N-bit sigma-delta conversion means for receiving a digital input signal from the outside and converting the sigma-delta into a N-bit signal (N is a natural number); Decoding means for receiving and decoding the N-bit signal output from the sigma-delta conversion means and outputting 2 ^N signals; A random generation circuit section for randomizing the 2 ^N signals output from the decoding means; And Switched-capacitor filtering means for outputting a final analog output signal converted to the digital input signal after performing a low pass filtering operation by receiving the randomized signal output from the random generation circuit unit Digital-to-analog conversion device comprising a. The method of claim 1, wherein the random generation circuit unit, It includes a plurality of unit random generation circuit, The unit random generation circuit unit, respectively The first and second control signals are combined by combining the previous first and second input signals and the current first and second input signals input to the unit random generation circuit in response to the first and second input signals. Generating control signal generation means; And In response to the first control signal output from the control signal generating means, output the first and second input signals as first and second output signals as they are, and in response to the second control signal, the first and second signals. Random signal output means for swapping two input signals and outputting the second and first output signals Digital-to-analog conversion device comprising a. The method of claim 2, wherein the control signal generating means, First exclusive OR means for receiving the first and second input signals to both input terminals and performing an exclusive OR; A D flip-flop that edge-triggers the output signal from the first exclusive OR means in response to a clock signal and sends it to an output terminal; Second exclusive OR means for receiving an output signal from the first exclusive OR means and a signal from the output terminal Q of the D flip-flop and outputting the second control signal by performing an exclusive OR on the two signals; And Inverting means for inverting the output signal of said second exclusive OR means to output said first control signal Digital-to-analog conversion device comprising a. The method of claim 1, wherein the random generation circuit unit, The plurality of unit random generation circuits arranged in multiple stages using a butterfly connection in response to the 2 ^N signals output from the decoding means. Digital-to-analog conversion device comprising a.