JP2002190738A - Digital/analog converter and analog/digital converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance conversion precision by reducing the influence of a parasitic capacity in the capacity string of a digital/analog converter. SOLUTION: Each capacity used for the converter has an upper polysilicone layer and a lower polysilicone layer. The upper polysilicone layer of a capacity Ch(h-1) to Ch1 corresponding to a high-order bit (H-DAC) is all connected to a common node on the side of the high-order bit and each lower polysilicone layer is connected to analog switches SWh(h-1) to SWh1. The upper polysilicone layer of a capacity Cl(l-1) to Cl1 corresponding to a low-order bit (L-DAC) is all connected to a common node on the side of the low-order bit and each lower polysilicone layer is connected to analog switches SWl(l-1) to SWl1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-to-analog converter comprising a capacity sequence weighted by binary values and a comparison type analog-to-digital converter provided with the digital-to-analog converter.

[0002]

2. Description of the Related Art Conventionally, an analog / digital converter has
Widely used for communication equipment and control equipment.

[0003] As a method, a comparison type analog-to-digital converter, that is, an analog-to-digital converter having a digital-to-analog conversion unit and a comparator is frequently used.

FIG. 8 is a block diagram showing an example of the configuration of a conventional analog / digital converter. The analog-to-digital converter shown in FIG. 8 is one configuration example using a comparison-type digital-to-analog converter, and is weighted by binary values (1, 2, 4,..., 2 ^(n-1) ). A digital-to-analog converter that has a column of capacitances (capacitance column) having capacitance values, and converts an input analog amount (analog voltage) into a voltage value that is inversely proportional to the weight for each digit and prepares for comparison with a reference voltage 91, a comparator 92 for sequentially comparing the voltage value generated for each digit with the reference voltage, and a voltage value for each digit sequentially while latching the comparison result of the comparator 92 sequentially. A successive approximation register 93 for sequentially sending out a switch control signal (a digital code whose final state is converted) is provided for the switches for producing the data.

Usually, the digital / analog conversion section 91
Takes a configuration in which two capacitance columns are coupled via a coupling capacitance. This is because the chip occupation area in the case of the LSI is smaller and higher resolution can be obtained as compared with the case where only one capacitor row is used.

FIG. 9 is a circuit diagram showing one configuration example of a digital-to-analog converter of a conventional analog-to-digital converter. Digital-to-analog converter unit 91 shown in FIG. 9
Are the capacitances C9 _{h (h-1)} , which constitute the capacitance sequence for the upper bits,
..., C9 and _h2, C9 _h1, capacitance forming the capacitor rows of lower bit _{C9 l (l1), ...,} C9 l2, C9 l1, and C9e, capacitance column and a lower bit for the above upper bit a coupling capacitor C9c for coupling the capacitor columns of the switch for sequentially applying a reference voltage for comparison with the analog input voltage to each of the capacitance of the capacitor rows _{SW9k, SW9 h (h-1} ), ..., SW9 h2 ,
SW9 _h1 , SW9 _{l (l-1)} ,..., SW9 _l2 , SW9 _l1 , S
W9e.

[0007] A switch SW9c shown in FIG. 9 indicates a switch on the comparator (dynamic comparator) side. In the digital / analog conversion section 91, the digital / analog conversion section forming the upper bits is indicated by a code (H-DAC), and the digital / analog conversion section forming the lower bits is indicated by a code (L-DAC). ).

[0008] A capacitor C9 constituting a capacity column for upper bits
The capacity value of _{h (h-1)} ,..., C9 _h2 , C9 _h1 is 1
c are 2 ^(h-1) c,..., 2c, 1c, respectively, and the capacitances C9 _{l (l-1)} ,
, _C9l2 , _C9l1 are 2 ^(l-1) c,..., 2c, 1c, respectively, assuming that the unit capacity is 1c.

The capacitance value of the capacitor C9e is equal to 1 of the unit capacitance.
c, and the capacitance value of the capacitor C9c is 2 ^lc / (2^l-1)
is there. Hereinafter, the digital / analog converter 9 shown in FIG.
1 is shown.

During the sampling period of the analog input voltage, all the capacitors in the capacitor row are connected to the analog input terminal (AIN), and the comparator is stopped at the intermediate potential by turning on the switch SW9c. .

When the conversion operation starts, the analog input terminal (A
IN) and SW9c are shut off, and switches SW9k, SW9
_{9 h (h1), ...,} SW9 h2, SW9 h1, SW9 l (l-1),
.., SW9 _l2 , SW9 _l1 , and SW9e are sequentially operated, so that the reference voltage (Vref) and the GND (ground) are provided in order from the upper digit to the lower digit for the capacity corresponding to each bit (digit). Repeat the operation of alternately applying the potential and
As a result, a digit in which the potential of the common node of the capacitor string becomes the intermediate potential of the comparator is sequentially searched, and the digital code output shown in FIG. 8 is obtained as a result of the search.

FIG. 10 is a circuit diagram showing one configuration example of a conventional digital-to-analog converter. The digital-to-analog converter 101 of the conventional digital-to-analog converter shown in FIG. 10 has a capacitor constituting a capacitor array for upper bits, similarly to the digital-to-analog converter 91 of the analog-to-digital converter shown in FIG. C10 _{h (h-1)} , ..., C1
_0h2 , C10 _h1 and capacitances C10 _{l (l−1)} ,..., C10 _l2 , C10 ₁₁ , C10e forming a capacitance sequence for lower bits
And a coupling capacitance C10c that couples the capacitance sequence for the upper bits and the capacitance sequence for the lower bits. The digital / analog converter 101 further includes a grounded capacitor C1.
Each volume of non-0e, analog switch SW10 to connect either the ground potential and the reference voltage by a digital code that is input _{h (h-1), ...} , SW10 h2, SW
10 _h1 , SW10 _{l (l−1)} ,..., SW10 _l2 , SW10 _l1
Is provided.

The digital-to-analog converter includes an operational amplifier for amplifying the output of the digital-to-analog converter 101 and a switch SW10G connected to a common node of the upper bits.

The capacitance value of the capacitance constituting the digital / analog converter 101 is the same as that of the digital / analog converter 91 in FIG. Hereinafter, the digital communication shown in FIG.
The operation of the analog converter 101 will be described.

First, in order to reset the capacitance, an analog switch SW10h _(h-1) connected to each capacitance is set.
.., SW10 _h2 , SW10 _h1 , SW10 _{l (l-1)} ,.
By connecting SW10 _l2 and SW10 _l1 to the ground side, and closing SW10G connected to the common node of the upper bit, all unnecessary charges charged in the capacitor are discharged.

When the digital code is input after the SW 10G is opened, one side of the capacitance where the digital code is 1 is connected to Vref, and one side of the capacitance where the digital code is 1 is still connected to the ground. The electric charge stored in the total equivalent capacitance of the capacitance connected to Vref is output from DAOUT as an analog voltage through an operational amplifier.

[0017]

In the above-mentioned conventional digital-to-analog converter and analog-to-digital converter, the value of the coupling capacitor C9c must be partially changed in order to perform a correct conversion operation. When the partial digital-to-analog converter (L-DAC) side is viewed from the converter (H-DAC) side through the coupling capacitor C9c, the capacitance value is the unit capacitance value on the (H-DAC) side. Must be set to the same value as

That is, the total capacity on the (L-DAC) side is:
When the value of the unit capacity is 1c and the number of bits is l,
Since the capacitance value is 2 ^l (the capacitance value of the capacitance SW 9 e is also assumed to be 1 c of unit capacitance), the value of the coupling capacitance C 9 c is 2 ^l c
/ (2 ^l -1).

The value of the coupling capacitance C9c is, for example, l = 4
Is 16c / 15 when l = 8, and 2 when l = 8.
56c / 255, that is, a value slightly larger than 1c.

However, when a digital-to-analog converter or an analog-to-digital converter is actually formed on a silicon wafer, the optimum value of the coupling capacitance C9c deviates from the above theoretical value because various parasitic capacitances exist. Therefore, there is a problem that high conversion accuracy cannot be obtained.

That is, the capacitance value when the (L-DAC) side is viewed from the (H-DAC) side via the coupling capacitor C9c is shifted by the influence of the parasitic capacitance. to cause.

In order to improve the above, a parallel plate capacitor made of polysilicon, whose capacitance value does not show voltage dependency and which can be formed relatively accurately, is used as each of the capacitors in the above-mentioned capacitor row. Even if the capacitance value of the coupling capacitor C9c is set to a theoretical value, a relatively large parasitic capacitance is formed between the underlying polysilicon and the substrate, which has the opposite effect and significantly reduces the conversion accuracy. There was a problem.

Further, the capacitance value of the parasitic capacitance between the lower polysilicon and the substrate changes due to a change in the oxide film thickness between the lower polysilicon and the substrate for each manufacturing process. In addition, there has been a problem that the optimum value of the coupling capacitance C9c changes, and that there is an influence of manufacturing variations.

FIG. 11 is a circuit diagram showing an example of a configuration of a capacitor string included in a digital-to-analog converter of a conventional analog-to-digital converter. The capacitances C9 _{h5 to} C9 _h1 , C9 _{l5 to} C9 _l1 , and the coupling capacitance C9c ′ included in the capacitance row shown in FIG. 11 are all formed of polysilicon.

The lower polysilicon electrodes forming the capacitors C9 _{h5 to} C9 _h1 are all connected to the common node on the upper bit side, and the lower polysilicon electrodes forming the capacitors C9 _{15 to} C9 _l1 are all connected to the lower bit side. Connected to a common node.

The symbol Cp in the figure indicates the parasitic capacitance between the lower polysilicon and the substrate in each of the capacitors included in the capacitor column. Due to the existence of the parasitic capacitance Cp, a capacitance value when the (L-DAC) side is viewed from the (H-DAC) side via the coupling capacitance C9c 'becomes larger than a theoretical design value. .

FIG. 12 is a graph showing simulation results and actual measurement results of conversion characteristics of a conventional analog-to-digital converter in which a capacitance column included in the digital-to-analog converter has a parasitic capacitance.

The measurement object of the graph shown in FIG.
This is a conventional analog / digital converter provided with a capacity column shown in FIG. FIG. 12A shows a simulation result, and FIG. 12B shows an actual measurement result.

The resolution of the analog-to-digital converter corresponding to the conversion characteristic shown in FIG. 12 is 10 bits (including 5 bits on the (H-DAC) side and 5 bits on the (L-DAC) side), The conversion range of the analog input voltage is 0 to 5 (V). Further, the coupling capacitance C9c ′
Are left as theoretical values (= 32c / 31), and optimization is not performed.

The ideal characteristic required is ± 0.5 (LS) with respect to a straight line of y = ax (a = 1023/5).
Although it is within the quantization error of B), it can be seen from the graph shown in FIG. Are not satisfying the above-mentioned error level, and are not ideal characteristics.

The present invention has been made in view of the above problems in the conventional digital-to-analog converter and analog-to-digital converter.
A digital-to-analog converter and an analog-to-digital converter capable of improving the conversion accuracy without optimizing the coupling capacitance by reducing the influence of the parasitic capacitance in the capacitance string of the analog conversion unit. With the goal.

A second object of the present invention is to reduce the influence of parasitic capacitance in a capacitance column of a digital-to-analog conversion unit, thereby improving the conversion accuracy without optimizing the coupling capacitance. -To provide an analog converter and an analog-digital converter.

[0033]

According to the present invention, in order to solve the above-mentioned problem, a capacity string composed of a capacity weighted by a binary value is replaced by a capacity string of upper bits composed of a capacity corresponding to the upper bits of a digital code. And a capacitance sequence of lower bits composed of capacitances corresponding to lower bits of the digital code, wherein the capacitance sequence of upper bits and the capacitance sequence of lower bits are connected via a coupling capacitance. As the capacitor, a capacitor in which a lower polysilicon and an upper polysilicon are formed on a substrate via an insulating film is used, and all the upper polysilicon corresponding to the upper bit is connected to a common node on the upper bit side. At the same time, each of the lower polysilicon layers corresponding to the upper bits is connected to a corresponding analog switch, and All the upper polysilicon capacity corresponding to the preparative well as connected to a common node of the lower bit side,
A digital-to-analog converter and an analog-to-digital converter are provided, wherein each of the lower polysilicon layers corresponding to the lower bits is connected to a corresponding analog switch.

Further, a capacitor array composed of capacitors weighted by binary values and a comparator are provided, and a result of alternately applying an analog input voltage to be converted and a reference voltage to each of the capacitors in a predetermined order is obtained. An analog-to-digital converter which determines an output digital code by comparing with a comparator, wherein a capacitor formed by forming upper polysilicon and lower polysilicon via an insulating film on a substrate is used as the capacitor, and A configuration in which an upper bit capacity row composed of a capacity corresponding to the upper bit of the output digital code and a lower bit capacity row made of a capacity corresponding to the lower bit of the output digital code are connected via a coupling capacitor. And connecting all the upper polysilicon layers corresponding to the upper bits to the common node on the upper bit side. Each of the lower polysilicon layers corresponding to the upper bits is connected to a corresponding analog switch, and all the upper polysilicon layers corresponding to the lower bits are connected to a common node on the lower bit side. An analog-to-digital converter is provided, wherein each of the lower polysilicon layers having different capacitances is connected to a corresponding analog switch.

That is, in the present invention, the capacitance value is weighted by the binary value, and the analog voltage and the reference voltage are sequentially applied to the lower polysilicon electrode for all the capacitances included in the capacitance column formed of polysilicon. To connect to a switch (hereinafter, collectively referred to as an “analog switch”) corresponding to each of the above-described capacitances, so that the parasitic capacitance conventionally formed between the common node and the substrate can be converted to the analog It is formed between the switch side and the substrate, thereby reducing and canceling the influence of the parasitic capacitance in the capacitance row of the digital-to-analog converter.

[0036]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a circuit diagram showing a configuration of a digital-to-analog converter of an analog-to-digital converter according to a first embodiment of the present invention.

The general configuration of the analog-to-digital converter according to the present embodiment is the same as that of the conventional analog-to-digital converter having a comparison type digital-to-analog conversion unit composed of a capacity sequence weighted by binary values as shown in FIG. Is the same as in the overall configuration.

As shown in FIG. 1, the digital-to-analog conversion section according to the present embodiment comprises capacitances _{Ch (h-1)} ,..., _Ch2 , _Ch1 constituting a capacitance sequence for upper bits. The capacitances C _{l (l−1)} ,..., C _l2 , C _l1,.
Ce, a coupling capacitance Cc for coupling the above-mentioned capacitor row for the upper bit and the capacitor row for the lower bit, and an analog input voltage and a reference voltage for comparison to be sequentially applied to each of the capacitors in the above-mentioned capacitor row. Switch (analog switch) SWk, S
_{Wh (h-1)} , ..., _SWh2 , _SWh1 , SWl _(l-1) , ..., SW
_l2 , _SWl1 , and SWe.

Here, the weighting of the capacitance values given to the respective capacitances _{Ch (h-1)} ,..., _Ch2 , _Ch1 constituting the capacitance sequence for the upper bits and the capacitance sequence for the lower bits are constituted. Capacity C
_{l (l1),} ..., implemented in C _l2, C _l1, Ce each same way a weighted capacitance values to be applied to the, and it is possible to h = l.

Digital / analog according to the present embodiment
In the conversion unit, the capacitance C for the upper bit _{h (h-1)}, ..., C_h2,
C_h1All upper polysilicon electrodes that form
The lower polysilicon layer is connected to the common node on the bit (H-DAC) side.
The electrodes of the condenser are each a switch SW_{h (h-1)}, ..., SW
_h2, SW_h1Connected to

Further, capacitors C _{l (l−1)} ,...
The upper polysilicon electrodes forming C _l2 , C _l1 , and Ce are all connected to a common node on the lower bit (L-DAC) side.
The lower polysilicon electrode is connected to the switch S
W _{h (h1),} ..., it is connected to the SW _h2, SW _h1, SWe.

In this case, the upper polysilicon electrode of the coupling capacitor Cc is connected to one end of the common node on the upper bit side.
The electrode of the lower polysilicon is connected to one end of the common node on the lower bit side, respectively, but the connection reverse to this is also possible.

Capacitance C forming a capacity column for upper bits
The capacity values of _{h (h-1)} ,..., _Ch2 , _Ch1 are set to 2 ^(h-1) c,. Capacity C _{l (l-1)} , ...,
The capacitance values of C _l2 and C _l1 can be set to 2 ^(l−1) c,.

The capacitance value of the capacitance Ce is equal to 1 of the unit capacitance.
and the capacitance value of the coupling capacitance Cc is twice the capacitance value of the capacitance corresponding to the lower-order bit, that is, 2 ^lc / (2 ^l −1).
It can be.

The operation of the digital-to-analog converter according to this embodiment will be described below. During the sampling period of the analog input voltage, all the capacitors in the capacitor row are connected to the analog input terminal (AIN), and the comparator is stopped at the intermediate potential by turning on SWc.

When the conversion operation starts, the analog input terminal (A
IN) and SWc, and switches SWk, SW
_{h (h-1)} , ..., _SWh2 , _SWh1 , SWl _(l-1) , ..., S
By sequentially operating W _l2 , SW _l1 , and SWe, the reference voltage (Vref), the GND (ground) potential, and the capacitance corresponding to each bit (digit) are determined in order from the upper digit to the lower digit. Are repeated, thereby sequentially searching for a digit in which the potential of the common node of the capacitor string becomes the intermediate potential of the comparator. As a result of the search, the digital output to be output is obtained. Get the code.

FIG. 2 is a circuit diagram showing one configuration example of a capacitor string included in the digital-to-analog converter of the analog-to-digital converter according to the present embodiment. Capacitance _{C h5 ~C h1, C l5 ~C} l1 included in capacitance column 2, and the coupling capacitance Cc 'is formed by all polysilicon.

The upper-layer polysilicon electrodes forming the upper-bit capacitors _Ch5 to _Ch1 are all higher-order bits (HDD).
On the AC) side common node, the lower polysilicon electrodes are connected to the switches SW _{h5 to} SW _h1 shown in FIG. 1, respectively.

The lower-order bit capacitors C _{l5 to} C _l1 , C
e are all connected to the common node on the lower bit (L-DAC) side, and the lower polysilicon electrodes are connected to the switches SW _{h5 to} SW _h shown in FIG.
_h1 and SWe are connected.

The wiring method of the upper polysilicon electrode and the lower polysilicon electrode of the coupling capacitance Cc 'shown in FIG. 2 is reversed from the wiring method of the coupling capacitance C9c shown in FIG.

The symbol Cp in the figure indicates the parasitic capacitance between the lower polysilicon connected to the analog switch and the substrate. The existence of these parasitic capacitances Cp is determined by the above (H-DAC)
It does not affect the theoretical design value of the capacitance value when the (L-DAC) side is viewed from the side via the coupling capacitance Cc ′.

FIG. 3 is a graph showing a simulation result and an actual measurement result of one configuration example of the analog-to-digital converter according to the embodiment of the present invention. Measured in the graph shown in FIG. 3 is an analog-digital converter according to the present embodiment including the capacitor string shown in FIG.

FIG. 3A shows a simulation result, and FIG. 3B shows an actual measurement result. The resolution of the analog / digital converter corresponding to the conversion characteristics shown in FIG.
0 bits (including the (H-DAC) side and (L
−DAC) side, the conversion range of the analog input voltage is 0 to 5 (V). Also,
The capacitance value of the coupling capacitance Cc ′ was kept at the theoretical value (= 32c / 31), and optimization was not performed.

The ideal characteristic required is ± 0.5 (LS) with respect to a straight line of y = ax (a = 1023/5).
In FIG. 3, the graph shown in FIG. 3 satisfies this error level in both the simulation result and the actual measurement result.

(Second Embodiment) FIG. 4 is a circuit diagram showing a configuration of a digital-to-analog converter of an analog-to-digital converter according to a second embodiment of the present invention.

The general configuration of the analog-to-digital converter according to the present embodiment is a conventional analog-to-digital converter having a comparison type digital-to-analog conversion unit composed of a capacity sequence weighted by binary values as shown in FIG. Is the same as in the overall configuration.

The configuration of the digital-to-analog converter according to the second embodiment of the present invention is the same as that of the second embodiment shown in FIG.
Compared with the configuration of the digital-to-analog conversion unit according to the embodiment, the configuration of the coupling capacitance is a single capacitance Cc shown in FIG.
Therefore, the only difference is that the capacitance C4c shown in FIG. 4 having half the capacitance value of the capacitance Cc is replaced by two complementary coupling capacitors connected in parallel.
The configuration is the same as that of the digital-to-analog conversion unit according to the second embodiment of the present invention shown in FIG.

In the first embodiment of the present invention shown in FIG. 1, the parasitic capacitance corresponding to the coupling capacitance Cc can be connected to either the upper bit side or the lower bit side. The effect of presence on conversion accuracy cannot be completely eliminated.

However, in the circuit configuration of the digital-to-analog converter according to the second embodiment of the present invention shown in FIG. 4, the coupling capacitance Cc is replaced with the coupling capacitance Cc shown in FIG.
Value of the capacitance value of half (= 2 ^(l-1) c / (2 ^l -1))
And two coupling capacitors C4c each having a parallel connection, and a complementary coupling capacitor formed by connecting the upper-layer silicon and lower-layer polysilicon electrodes to the other-side lower-layer polysilicon and upper-layer polysilicon electrodes, respectively. Therefore, the parasitic capacitances respectively corresponding to these two coupling capacitances C4c can be offset from each other.

FIG. 5 is a circuit diagram showing an example of the configuration of a capacitor string included in the digital-to-analog converter of the analog-to-digital converter according to the present embodiment. FIG capacity included in the capacity columns shown in _{5 C h5 ~C h1, C l5} ~C l1, and the coupling capacitance C4c 'is formed by all polysilicon.

The upper-layer polysilicon electrodes forming the upper-bit capacitors _Ch5 to _Ch1 are all higher-order bits (HDD).
On the common node on the AC) side, an electrode of lower polysilicon is
Each is connected to the switches SW _{h5 to} SW _h1 shown in FIG.

The lower-order bit capacitors C _{15 to} C ₁₁ , C ₁₁
e are all connected to the common node on the lower bit (L-DAC) side, while the lower polysilicon electrodes are connected to the switches SW _{h5 to} SW _h shown in FIG.
_h1 and SWe are connected.

The symbol Cp in the figure indicates the parasitic capacitance between the lower polysilicon connected to the analog switch and the substrate. The existence of these parasitic capacitances Cp is determined by the above (H-DAC)
It does not affect the theoretical design value of the capacitance value when the (L-DAC) side is viewed through the parallel coupling circuit composed of two coupling capacitors C4c 'from the side.

FIG. 6 is a graph showing a simulation result of one configuration example of the analog / digital converter according to the second embodiment of the present invention. The measurement target of the graph shown in FIG. 6 is the analog-to-digital converter according to the present embodiment having the capacitance row shown in FIG.

An analog signal corresponding to the conversion characteristic shown in FIG.
The resolution of the digital converter is assumed to be 10 bits (including 5 bits each on the (H-DAC) side and (L-DAC) side), and the conversion range of the analog input voltage is as follows:
0 to 5 (V). In addition, two coupling capacitors C4
The capacitance value of c ′ is kept at the theoretical value (= 16c / 31), and optimization is not performed.

The ideal characteristic required is ± 0.5 (LS) with respect to a straight line of y = ax (a = 1023/5).
Although the quantization error falls within the quantization error B), the graph shown in FIG. 6 satisfies this error level.

FIG. 7 is a plan view showing an example of the structure of a complementary coupling capacitance included in the digital-to-analog converter of the analog-to-digital converter according to the present embodiment. The coupling capacitance of the complementary type shown in FIG. 7 is the coupling capacitance C4 shown in FIG.
c (= 2 ^(l-1) c / (2 ^l -1), that is, a complementary type formed by connecting two capacitors having a capacitance half the capacitance of the coupling capacitor Cc shown in FIG. 1 in parallel. And a coupling capacitance 71 formed by disposing an upper polysilicon 711 above a lower polysilicon 712 and a coupling capacitance 72 formed by disposing an upper polysilicon 721 above a lower polysilicon 722. Is provided.

The lower bit (L) of lower polysilicon 712
-DAC) side contact 74 and upper polysilicon 7
21 is connected to the contact 74 on the lower bit (L-DAC) side via the metal wiring 73 on the (L-DAC) side, and is connected to the upper bit (H-
DAC) side contact 74 and lower polysilicon 72
The second upper bit (H-DAC) side contact 74 is connected to the (H-DAC) side metal wiring 73.

In each of the above embodiments, the analog-to-digital converter has been described. However, the analog-to-digital converter according to the present invention is a digital-to-analog converter having a ladder-type circuit as shown in FIG. -It is clear that it can be converted to an analog converter.

[0070]

As described above, in the present invention, the capacitance value is weighted by the binary value, and the lower polysilicon is connected to the analog switch for all the capacitances included in the capacitance column formed of polysilicon. As a result, the parasitic capacitance conventionally formed between the common node and the substrate is now formed between the analog switch and the substrate. The effect of the capacity can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a digital-to-analog converter of an analog-to-digital converter according to a first embodiment of the present invention.

FIG. 2 shows a first example of a capacitance column included in a digital-to-analog converter of the analog-to-digital converter according to the present embodiment.
FIG. 3 is a circuit diagram illustrating a configuration example.

FIG. 3 is a graph showing a simulation result and an actual measurement result of one configuration example of the analog-to-digital converter according to the embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a digital-to-analog converter of an analog-to-digital converter according to a second embodiment of the present invention.

FIG. 5 shows one of the capacitance strings included in the digital-to-analog converter of the analog-to-digital converter according to the present embodiment.
FIG. 3 is a circuit diagram illustrating a configuration example.

FIG. 6 is a graph showing a simulation result of one configuration example of the analog-to-digital converter according to the second embodiment of the present invention.

FIG. 7 is a plan view showing one structural example of a complementary coupling capacitance included in the digital-to-analog converter of the analog-to-digital converter according to the present embodiment.

FIG. 8 is a block diagram showing a configuration example of a conventional analog-digital converter.

FIG. 9 is a circuit diagram showing one configuration example of a digital-to-analog converter of a conventional analog-to-digital converter.

FIG. 10 is a circuit diagram showing one configuration example of a conventional digital-analog converter.

FIG. 11 is a circuit diagram showing one configuration example of a capacitor string included in a digital-to-analog converter of a conventional analog-to-digital converter.

FIG. 12 is a graph showing a simulation result and an actual measurement result of conversion characteristics of a conventional analog-to-digital converter in which a capacitance column included in the digital-to-analog converter has a parasitic capacitance.

[Explanation of symbols]

71,72, Cc, Cc 'coupling capacitor 73 metal interconnect 74 contacts AIN analog input terminal _{Ce, C h1 ~C h (h1} ), C l1 ~Cl (l1) capacitance Cp the parasitic capacitance 711 and 721 upper poly silicon 712 and 722 underlying polysilicon _{SWe, SWk, SW h1 ~SW h} (h1), SW l1 ~SW
_{l (l-1)} switch Vref Reference voltage

Continued on the front page F term (reference) 5F038 AC05 AC17 CA05 CD03 DF03 EZ14 EZ20 5J022 AA02 AB04 BA01 BA04 BA06 CE08 CF01 CF07 CG01

Claims (12)

[Claims] 1. A capacity sequence consisting of a capacity weighted by a binary value is composed of a capacity sequence of upper bits consisting of a capacity corresponding to upper bits of a digital code and a lower order bit consisting of a capacity corresponding to lower bits of a digital code. A digital-to-analog converter in which the high-order bit and the low-order bit are connected via a coupling capacitor, wherein the lower-level polysilicon and the lower-level polysilicon are interposed on the substrate via an insulating film. Using a capacitor in which an upper-layer polysilicon is formed, connecting all upper-layer polysilicon of the capacitor corresponding to the upper bit to a common node on the upper-bit side, and each of the lower-layer polysilicon of the capacitor corresponding to the upper bit Are connected to the corresponding analog switches, and all the upper-layer polysilicon corresponding to the lower bits are connected to the lower bits. A digital-to-analog converter connected to a common node on the side and each lower-layer polysilicon having a capacity corresponding to the lower bit is connected to a corresponding analog switch. 2. The method according to claim 1, wherein the weighting of the capacitance value assigned to each of the capacitors corresponding to the upper bits and the weighting of the capacitance value assigned to each of the capacitors corresponding to the lower bits are set in the same manner. 2. The digital-to-analog converter according to claim 1, wherein: 3. The digital circuit according to claim 1, wherein the sum of the capacitance values of the capacitors corresponding to the upper bits is set equal to the sum of the capacitance values of the capacitors corresponding to the lower bits. Analog converter. 4. The digital-to-analog converter according to claim 1, wherein the capacitance value of the coupling capacitance is set to twice the capacitance value of the capacitance corresponding to the most significant bit of the lower bits. . 5. The digital-to-analog converter according to claim 1, wherein the coupling capacitance is a capacitance formed by forming upper polysilicon and lower polysilicon on a substrate via an insulating film. 6. A circuit in which two capacitors each having half the capacitance value of said coupling capacitance are connected in parallel, instead of said coupling capacitance, and said circuit uses an upper polysilicon layer of one of said two capacitances. 6. A digital-to-analog converter according to claim 5, wherein said lower polysilicon is connected to the other lower polysilicon, and one lower polysilicon of said two capacitors is connected to the other upper polysilicon. 7. A capacitor array comprising a capacitor weighted by a binary value and a comparator, wherein a result of alternately applying an analog input voltage to be converted and a reference voltage to each of the capacitors in a predetermined order is obtained. An analog-to-digital converter that determines an output digital code by comparing with a comparator, wherein a capacitor formed by forming upper polysilicon and lower polysilicon via an insulating film on a substrate is used as the capacitor,
The capacitance sequence is formed by coupling a capacitance sequence of upper bits composed of capacitances corresponding to upper bits of the output digital code and a capacitance sequence of lower bits composed of capacitances corresponding to lower bits of the output digital code via a coupling capacitance. In this configuration, all upper polysilicon layers corresponding to the upper bits are connected to a common node on the upper bit side, and each lower polysilicon layer corresponding to the upper bits is connected to a corresponding analog switch. All upper polysilicon layers of the capacitance corresponding to the lower bits are connected to a common node on the lower bit side, and each lower polysilicon layer of the capacitance corresponding to the lower bits is connected to a corresponding analog switch. Analog-to-digital converter. 8. The method according to claim 1, wherein the weighting of the capacitance value assigned to each of the capacitors corresponding to the upper bits and the weighting of the capacitance value assigned to each of the capacitors corresponding to the lower bits are set in the same manner. The analog-to-digital converter according to claim 7, wherein: 9. The analog / digital converter according to claim 7, wherein the sum of the capacitance values of the capacitors corresponding to the upper bits is set to be equal to the sum of the capacitance values of the capacitors corresponding to the lower bits. Digital converter. 10. The capacitance value of the coupling capacitance is set to 2 times the capacitance value of the capacitance corresponding to the most significant bit of the lower bits.
8. The analog-to-digital converter according to claim 7, wherein the setting is doubled. 11. The analog-digital converter according to claim 7, wherein said coupling capacitance is a capacitance formed by forming upper polysilicon and lower polysilicon on a substrate via an insulating film. 12. A circuit in which two capacitors each having half the capacitance value of the coupling capacitance are connected in parallel in place of the coupling capacitance, and the circuit comprises an upper polysilicon layer of one of the two capacitances. 2. The capacitor according to claim 1, wherein said lower polysilicon is connected to the other lower polysilicon, and one lower polysilicon of said two capacitors is connected to the other upper polysilicon.
2. The analog-digital converter according to 1.