JPH079909B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JPH079909B2
JPH079909B2 JP5576687A JP5576687A JPH079909B2 JP H079909 B2 JPH079909 B2 JP H079909B2 JP 5576687 A JP5576687 A JP 5576687A JP 5576687 A JP5576687 A JP 5576687A JP H079909 B2 JPH079909 B2 JP H079909B2
Authority
JP
Japan
Prior art keywords
single crystal
polysilicon layer
crystal silicon
semiconductor device
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5576687A
Other languages
Japanese (ja)
Other versions
JPS63221633A (en
Inventor
律夫 滝沢
耕一郎 本田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5576687A priority Critical patent/JPH079909B2/en
Publication of JPS63221633A publication Critical patent/JPS63221633A/en
Publication of JPH079909B2 publication Critical patent/JPH079909B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)

Description

【発明の詳細な説明】 〔概要〕 ポリシリコンによるゲッタリング技術において、素子形
成工程中に発生する反りを減少させるために、二枚の単
結晶シリコンウエーハの間にポリシリコン層を形成し
て、二枚のウエーハを一体化し、このウエーハ上に半導
体素子を形成する半導体素子の製造方法。
DETAILED DESCRIPTION [Outline] In a gettering technique using polysilicon, a polysilicon layer is formed between two single crystal silicon wafers in order to reduce warpage that occurs during an element formation process. A method of manufacturing a semiconductor device, comprising integrating two wafers and forming a semiconductor device on the wafer.

〔産業上の利用分野〕[Industrial application field]

本発明は、半導体素子の製造工程中に発生する欠陥や混
入する重金属を除去する目的で行われるゲッタリング技
術に係り、特に単結晶シリコンウエーハの変形防止方法
に関するものである。
The present invention relates to a gettering technique carried out for the purpose of removing defects and heavy metals mixed therein during a semiconductor element manufacturing process, and more particularly to a method for preventing deformation of a single crystal silicon wafer.

近年半導体素子の高集積化、微細化は著しく、それに伴
い材料となる半導体基板は益々欠陥のない高品質のもの
が要求されている。
2. Description of the Related Art In recent years, semiconductor elements have been highly integrated and miniaturized, and accordingly, semiconductor substrates, which are used as materials, are required to have higher quality without defects.

しかしCZ法により製造されたシリコン基板等の半導体基
板にはppmレベルの酸素や炭素或いはpptレベルの重金属
である鉄(Fe)や銅(Cu)等が含まれている。
However, a semiconductor substrate such as a silicon substrate manufactured by the CZ method contains oxygen and carbon at the ppm level or iron (Fe) and copper (Cu) which are heavy metals at the ppt level.

このうちで最も濃度の高い酸素は過飽和状態で固溶して
おり、素子製造プロセスの熱処理を受けると析出し、転
位や積層欠陥等を発生させる。
Of these, oxygen, which has the highest concentration, is solid-soluted in a supersaturated state and precipitates when subjected to heat treatment in the element manufacturing process, causing dislocations, stacking faults, and the like.

又、素子製造プロセスは清浄雰囲気で行われるが、装置
やガスや水等から混入する不純物も比較的多い。そして
これらの欠陥や不純物が素子の活性領域に存在すると、
素子の電気的特性を劣化させることが実験で確かめられ
ている。
Further, although the element manufacturing process is carried out in a clean atmosphere, there are relatively many impurities mixed in from the equipment, gas, water and the like. And if these defects and impurities exist in the active region of the device,
It has been confirmed by experiments that the electrical characteristics of the device are deteriorated.

従って高品質の半導体素子を歩留まり良く製造するため
には、上記の欠陥や不純物を制御或いは除去し、素子の
活性領域を清浄化することが必要である。
Therefore, in order to manufacture a high quality semiconductor device with a high yield, it is necessary to control or remove the above defects and impurities and clean the active region of the device.

以上のような状況から実施に際して副作用のないゲッタ
リング技術の適用が可能な半導体素子の製造方法が要望
されている。
Under the circumstances as described above, there is a demand for a method of manufacturing a semiconductor device that can be applied with a gettering technique without any side effects in implementation.

〔従来の技術〕[Conventional technology]

従来のゲッタリング技術には種々のものがあるが、単結
晶シリコンウエーハにおいては簡便であり且つ効果の大
きな、ポリシリコン層の形成によるゲッタリング技術が
一般に広く用いられており、単結晶シリコンウエーハに
ポリシリコン層を形成したものも既に市販されている。
Although there are various conventional gettering techniques, the gettering technique by forming a polysilicon layer, which is simple and highly effective for a single crystal silicon wafer, is generally widely used. Those having a polysilicon layer are already on the market.

従来のゲッタリング技術におけるポリシリコン層の形成
を第2図により説明する。
The formation of the polysilicon layer in the conventional gettering technique will be described with reference to FIG.

図において、単結晶シリコンウエーハ1の裏面の全面或
いは一部にポリシリコン層3をCVDにより形成してお
り、この場合にポリシリコンのグレイン及び単結晶シリ
コンウエーハ1とポリシリコン層3の界面に形成された
歪層2が不純物を捕獲するゲッタシンクとして働くもの
と考えられている。
In the figure, a polysilicon layer 3 is formed on the whole or a part of the back surface of the single crystal silicon wafer 1 by CVD. In this case, a polysilicon grain and an interface between the single crystal silicon wafer 1 and the polysilicon layer 3 are formed. It is considered that the strained layer 2 thus formed functions as a getter sink for capturing impurities.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

以上説明の従来のゲッタリング技術で問題となるのは、
ポリシリコン層を単結晶シリコンウエーハの裏面のみ或
いは裏面と表面の一部に形成しているために、素子形成
プロセスを経ると単結晶シリコンとポリシリコンの熱膨
張率の差により単結晶シリコンウエーハが反るという問
題が生じることである。
The problem with the conventional gettering technology described above is that
Since the polysilicon layer is formed only on the back surface of the single crystal silicon wafer or on a part of the back surface and the front surface, the single crystal silicon wafer will be formed due to the difference in coefficient of thermal expansion between the single crystal silicon and the polysilicon after the element formation process. The problem of warping occurs.

この単結晶シリコンウエーハの反りは、素子の微細化及
びウエーハの大口径化に伴い、より一層の低減化が望ま
れている。
The warp of the single crystal silicon wafer is desired to be further reduced with the miniaturization of the element and the increase in the diameter of the wafer.

本発明は以上のような状況から簡単且つ容易に実施し得
る半導体素子の製造方法の提供を目的としたものであ
る。
The present invention has an object to provide a method for manufacturing a semiconductor device which can be easily and easily implemented from the above situation.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点は、二枚の単結晶シリコンウエーハの間にポ
リシリコン層を形成して、二枚のウエーハを一体化し、
この単結晶シリコンウエーハ上に半導体素子を形成する
本発明による半導体素子の製造方法によって解決され
る。
The above problem is that a polysilicon layer is formed between two single crystal silicon wafers to integrate the two wafers,
This is solved by the method for manufacturing a semiconductor device according to the present invention, in which a semiconductor device is formed on this single crystal silicon wafer.

〔作用〕[Action]

即ち本発明においては、二枚の単結晶シリコンウエーハ
の間にポリシリコン層を形成して一枚のウエーハにする
ので、ポリシリコン層がウエーハの中央部に形成されて
いるため、素子形成プロセス中に生じる応力が対称的に
働き相殺されるためウエーハの反りが減少する。
That is, in the present invention, since a polysilicon layer is formed between two single crystal silicon wafers to form a single wafer, since the polysilicon layer is formed in the central portion of the wafer, during the device formation process. The warp of the wafer is reduced because the stresses generated in the wafers work symmetrically and cancel each other out.

又、裏面に形成した場合には素子形成プロセスでポリシ
リコン層が薄くなるが、本発明によればプロセス終了時
までポリシリコン層がそのまま残存するため、ゲッタ能
力が持続する利点もある。
Further, when the polysilicon layer is formed on the back surface, the polysilicon layer is thinned in the element forming process. However, according to the present invention, the polysilicon layer remains as it is until the end of the process, so that there is an advantage that the getter ability is maintained.

〔実施例〕〔Example〕

以下本発明の一実施例を、単結晶シリコンウエーハ1の
各々にポリシリコン層3を形成して接合する場合につい
て、第1図により工程順に説明する。
An embodiment of the present invention will be described in the order of steps with reference to FIG. 1 in the case where a polysilicon layer 3 is formed on each single crystal silicon wafer 1 and bonded.

第1図(a)に示すように両面を鏡面研磨した単結晶シリ
コンウエーハ1の一面にポリシリコン層3を形成したも
のを二枚製造する。
As shown in FIG. 1 (a), two single crystal silicon wafers 1 whose both surfaces are mirror-polished with a polysilicon layer 3 formed on one surface are manufactured.

次に、この二枚の単結晶シリコンウエーハ1に形成した
ポリシリコン層3の密着性を高めるために、親水処理を
した後乾燥させて、ポリシリコン層3を互いに密着させ
て第1図(b)に示すように接合する。
Next, in order to improve the adhesiveness of the polysilicon layers 3 formed on the two single crystal silicon wafers 1, a hydrophilic treatment is performed and then drying is performed to bring the polysilicon layers 3 into close contact with each other. ) As shown in FIG.

この状態で高温処理、例えば窒素雰囲気内で、30分間、
1,000℃で熱処理すると、ポリシリコン層3の表面同志
が結合し、第1図(c)に示すように二枚の単結晶シリコ
ンウエーハ1が一体となる。
High temperature treatment in this state, for example, in a nitrogen atmosphere for 30 minutes,
When heat-treated at 1,000 ° C., the surfaces of the polysilicon layer 3 are bonded to each other, and the two single crystal silicon wafers 1 are integrated as shown in FIG. 1 (c).

このようにして一体化した単結晶シリコンウエーハ1の
上に半導体素子を形成する。
A semiconductor element is formed on the single crystal silicon wafer 1 integrated in this way.

このように、ウエーハ内部にポリシリコン層3を有する
ウエーハが形成されるので、その構造がポリシリコン層
3を中心として、対称形となるため、素子形成プロセス
中に生じる応力が対称的に働くのでウエーハの反りが減
少する。
In this way, since the wafer having the polysilicon layer 3 inside is formed, the structure becomes symmetrical with the polysilicon layer 3 as the center, so that the stress generated during the element forming process acts symmetrically. Wafer warpage is reduced.

なお、上記の実施例においては、ポリシリコン層3を双
方の単結晶シリコンウエーハ1に形成しているが、一方
の単結晶シリコンウエーハ1にのみポリシリコン層3を
形成する製造方法も可能である。又、ポリシリコン層3
は一つとは限らず二層以上でもよい。
Although the polysilicon layer 3 is formed on both of the single crystal silicon wafers 1 in the above embodiment, a manufacturing method in which the polysilicon layer 3 is formed only on one of the single crystal silicon wafers 1 is also possible. . Also, the polysilicon layer 3
The number is not limited to one and may be two or more layers.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明によれば極めて簡単な工程に
より、二枚の単結晶シリコンウエーハを対称形のウエー
ハとすることができるのでウエーハの反りが減少し、又
ポリシリコン層がウエーハの中央に位置するので、ゲッ
タ能力が低下することもない等の利点があり、著しい経
済的及び、信頼性向上の効果が期待でき工業的には極め
て有用なものである。
As described above, according to the present invention, the two single crystal silicon wafers can be formed into symmetrical wafers by an extremely simple process, so that the warp of the wafer is reduced, and the polysilicon layer is formed in the center of the wafer. Since it is located, there is an advantage that the getter ability is not deteriorated, and it can be expected to have a remarkable economic and reliability improving effect, which is extremely useful industrially.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明による一実施例を工程順に示す側断面
図、 第2図は従来のポリシリコン層の形成を示す側断面図、 である。 図において、 1は単結晶シリコンウエーハ、 2は歪層、 3はポリシリコン層、 を示す。
1 is a side sectional view showing an embodiment of the present invention in the order of steps, and FIG. 2 is a side sectional view showing the formation of a conventional polysilicon layer. In the figure, 1 is a single crystal silicon wafer, 2 is a strained layer, and 3 is a polysilicon layer.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】ポリシリコンによるゲッタリング技術にお
いて、二枚の単結晶シリコンウエーハ(1)の間にポリ
シリコン層(3)を形成して、二枚のウエーハを一体化
し、前記単結晶シリコンウエーハ(1)上に半導体素子
を形成することを特徴とする半導体素子の製造方法。
1. In a gettering technique using polysilicon, a polysilicon layer (3) is formed between two single crystal silicon wafers (1) and the two wafers are integrated to form the single crystal silicon wafer. (1) A method of manufacturing a semiconductor device, which comprises forming a semiconductor device on the semiconductor device.
JP5576687A 1987-03-10 1987-03-10 Method for manufacturing semiconductor device Expired - Lifetime JPH079909B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5576687A JPH079909B2 (en) 1987-03-10 1987-03-10 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5576687A JPH079909B2 (en) 1987-03-10 1987-03-10 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS63221633A JPS63221633A (en) 1988-09-14
JPH079909B2 true JPH079909B2 (en) 1995-02-01

Family

ID=13007982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5576687A Expired - Lifetime JPH079909B2 (en) 1987-03-10 1987-03-10 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH079909B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02260428A (en) * 1989-03-31 1990-10-23 Hitachi Ltd Semiconductor substrate and device
JPH04162630A (en) * 1990-10-25 1992-06-08 Mitsubishi Materials Shilicon Corp Semiconductor substrate

Also Published As

Publication number Publication date
JPS63221633A (en) 1988-09-14

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