JPH0798358A - Semiconductor device - Google Patents

Abstract

PURPOSE:To miniaturize a device for conducting a burn-in test and conduct the burn-in test on many semiconductor devices at once by providing a feeding circuit continuously self-feeding activation signals to circuits under test. CONSTITUTION:In scan FFs 1-4 connected in series, the data applied to the scan input SI are outputted as they are at the scan output SO and the output Q in the scan mode that the input CP is set to '1', the input A to '0', and the input B to '1'. When the input TEST is set to '0' in the scan mode, the output of the FF 4 in the final stage is reversed via a feedback loop and fed to the scan input SI of the FF 1 in the first stage, i.e., '0' and '1' are outputted in turn in the closed loop of four FFs 1-4. Values of '0' and '1' thus self- generated are fed to circuits under test (internal combinational circuits) 5-7 connected to the FFs 1-4 respectively as activation signals of a burn-in test, and the burn-in test is conducted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of efficiently performing a burn-in test.

[0002]

2. Description of the Related Art Generally, it is known that the failure rate of a semiconductor product changes according to a characteristic called a bathtub curve as shown in FIG. 7, and the failure of the semiconductor product is caused by an initial failure period, a random failure period and wear. It can be divided into three periods of failure. In the semiconductor device having such a failure characteristic, the burn-in test reduces the occurrence rate of the failure in the market by operating the semiconductor device at a high temperature and a high voltage to cause the failure in advance in the initial failure period. It is a thing.

Such a burn-in test is carried out, for example, by a burn-in device of a system as shown in FIG.

In FIG. 8, the burn-in test apparatus is
It is composed of a burn-in (DUT) board and a main body that is roughly divided into a thermostatic chamber for heating a semiconductor device and a main control unit.

In such an apparatus, a semiconductor device to be subjected to a burn-in test is placed on a burn-in (DUT) board, and the burn-in board on which the semiconductor device is placed is placed in a thermostatic chamber of the main body to bring the inside to a high temperature state. Thus, a burn-in test is performed by applying a burn-in pattern, which is input data for operating the semiconductor device, to the semiconductor device and applying a load to the semiconductor device while the semiconductor device is heated. In this way, the burn-in test of the semiconductor device is performed to remove the defective semiconductor device in the initial failure period.

[0006]

As described above,
In the conventional burn-in test apparatus, an oven apparatus for heating the semiconductor device, a thermostatic chamber, a pulse generator for controlling the semiconductor apparatus, and the like are required, which leads to an increase in size of the apparatus.

Further, the size of the burn-in test device limits the number of semiconductor devices that can be burn-in tested at one time, resulting in poor test efficiency.

Therefore, the present invention has been made in view of the above, and an object of the present invention is to reduce the size of a device for performing a burn-in test and to enable a burn-in test of many semiconductor devices at one time. To provide.

[0009]

In order to achieve the above object, the invention according to claim 1 supplies an activation signal for self-oscillating during a burn-in test and continuously supplying an activation signal to a circuit under test. Composed of circuits.

According to a third aspect of the present invention, the semiconductor chip is fixed to the bed portion, and an internal heating means made of a resistive paste material is provided which heats the semiconductor chip by supplying heat during the burn-in test to heat the semiconductor chip. .

According to a fourth aspect of the present invention, there is provided an internal heating means which is connected in series or in parallel and which is supplied with a current during the burn-in test to generate heat and heat the semiconductor chip.

According to a fifth aspect of the present invention, in the semiconductor device according to the first or second aspect, the internal heating means according to the third or fourth aspect is provided.

[0013]

In the above structure, the invention according to the first aspect is arranged such that input data at the time of burn-in test is generated inside the semiconductor device and self-supplied.

According to the third aspect of the present invention, a current is passed through the resistive paste material for fixing the semiconductor chip to the bed to heat the resistive paste material to heat the semiconductor device.

According to a fourth aspect of the present invention, the semiconductor device is heated by causing the diodes to generate heat by passing a current through the plurality of diodes formed on the semiconductor chip.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the structure of a semiconductor device according to an embodiment of the invention described in claim 1. In FIG.

In FIG. 1, the semiconductor device comprises a scan test circuit composed of four scan flip-flops (F / F) 1 to 4 and a feedback loop provided in the scan test circuit to generate test data during burn-in test. ing. The respective scan F / Fs 1 to 4 are connected in series by connecting their scan inputs (SI) and scan outputs (SO).

Scan F / Fs connected in series in this way
1 to 4, the input CP is "1", the input A is "0", the input B
In the scan mode of "1", the data given to the scan input (SI) is directly output to the scan output (SO) and the output Q. When the input TEST is set to "0" in such a scan mode state, the scan F / F of the final stage is
The scan output of No. 4 is inverted via the feedback loop and applied to the scan input of the first-stage scan F / F1. That is, when the input TEST is set to “0” in the scan mode state, “0” is set in the closed loop of the four scan F / Fs 1 to 4.
And "1" are output alternately.

The self-generated values of "0" and "1" are connected to the respective scan F / Fs 1 to 4 as activation signals for the burn-in test, and the internal combinational circuit 5 becomes a circuit to be tested. , 6, 7, and each internal combination circuit 5, 6, 7 is activated. As a result, the burn-in test can be performed by activating the device under test without supplying a clock signal from the outside, and the burn-in test device can be downsized.

Even if there are, for example, three scan chains in which the scan F / Fs 1 to 4 are connected in series and a feedback loop is provided as shown in FIG.
By setting T to "0", the values of "0" and "1" are self-generated in each scan chain and given to the circuit under test as an activation signal of the burn-in test, and the same effect as the above-mentioned embodiment is obtained. Can be obtained.

FIG. 3 is a diagram showing the structure of a semiconductor device according to an embodiment of the invention described in claim 3.

In FIG. 3, the semiconductor chip 8 is mounted and fixed on the bed portion 10 by the resistive paste material 9, and the power supply potential is printed on the semiconductor chip 8 via the terminal 12 and the terminal 1
By impressing the ground potential to the bed portion 10 via 1 and the variable resistor Rv, a current is passed through the resistive paste material 9 to generate heat, and the semiconductor chip 8 is heated to perform the burn-in test. The heat generation amount of the resistive paste material 9 is controlled by adjusting the amount of current supplied to the resistive paste material 9 by the variable resistor Rv. In the normal operation, the terminal 4 is set to the power supply potential so that the bed 1
The current is not passed to 0.

In such an embodiment, a heating device such as an oven for raising the temperature of the semiconductor chip 8 is unnecessary, and the burn-in test device can be downsized.

FIG. 4 and FIG. 5 are views showing the structure of a semiconductor device according to an embodiment of the present invention.

In FIG. 4, diodes 13 for heating the semiconductor chips are respectively formed adjacent to all the output buffers, and such diodes 13 are connected in parallel on the semiconductor chips as shown in FIG. Of the power supply potential is applied to the commonly connected anode terminal of the diode 13 via the internal terminal 14 and the variable resistor Rv, and the ground potential is applied to the commonly connected cathode terminal of the diode 13 via the internal terminal 15. A current is passed through the diode 13 to generate heat, the semiconductor chip 8 is heated, and a burn-in test is performed. The heat generation amount of the diode 13 is controlled by adjusting the amount of current supplied to the diode 13 by the variable resistor Rv. In the normal operation, the terminal 14 is imprinted with the ground potential and the terminal 15 is imprinted with the power supply potential so that no current flows through each diode 13.

Even in such an embodiment, a heating device such as an oven for raising the temperature of the semiconductor chip becomes unnecessary,
The burn-in test device can be downsized.

FIG. 6 is a diagram showing the structure of a semiconductor device according to another embodiment of the present invention.

The feature of the embodiment shown in FIG. 6 is that
The diodes 13 shown in FIG. 4 are connected in series, the ground potential is applied to the cathode terminal of the diode 13 at one end through the internal terminal 14, and the internal terminal 15 and the variable resistor Rv are connected to the anode terminal of the diode 13 at the other end. The power supply potential is applied via the above to cause each diode 13 to generate heat. Note that during normal operation, the terminal 14
The power supply potential and the ground potential are printed on the terminal 15 so that no current flows through each diode 13.

Even in such an embodiment, a heating device such as an oven for raising the temperature of the semiconductor chip becomes unnecessary,
The burn-in test device can be downsized.

The embodiment shown in FIG. 1 or 2 and FIG.
The embodiment shown in FIG. 5 or FIG. 6 may be combined, and the burn-in test apparatus can be further downsized, and more semiconductor devices can be burned-in test at a time as compared with the conventional one.

[0032]

As described above, according to the first aspect of the invention, the activation signal for the burn-in test is generated inside the semiconductor device and self-supplied. The circuit under test is activated without supplying an activation signal from the outside, so that the burn-in test apparatus can be downsized and a larger number of semiconductor devices can be burn-in tested at a time as compared with the conventional case.

According to the third aspect of the present invention, by applying a current to the resistive paste material for fixing the semiconductor chip to the bed portion, the resistive paste material is heated to heat the semiconductor device. According to the invention described above, since the diodes are heated to heat the semiconductor device by supplying a current to the plurality of diodes formed on the semiconductor chip, the heating device in the burn-in test device is not required, and the burn-in test device is not required. It becomes possible to miniaturize the device and burn-in test a larger number of semiconductor devices at a time as compared with the conventional one.

According to the invention of claim 5, the invention of claim 3 and the invention of claim 4 are combined, so that the burn-in test apparatus is further miniaturized, and the burn-in test apparatus is more compact than the conventional one. It becomes possible to perform a burn-in test on many semiconductor devices.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the invention as set forth in claim 1;

FIG. 2 is a diagram showing a configuration of a semiconductor device according to another embodiment of the invention as set forth in claim 1;

FIG. 3 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a semiconductor device according to an embodiment of the invention as set forth in claim 4;

FIG. 5 is a diagram showing a configuration of a semiconductor device according to an embodiment of the invention as set forth in claim 4;

FIG. 6 is a diagram showing a configuration of a semiconductor device according to another embodiment of the invention as set forth in claim 4;

FIG. 7 is a diagram showing a time course of a failure rate of a semiconductor device.

FIG. 8 is a diagram showing a configuration of a conventional burn-in test apparatus.

[Explanation of symbols]

 1 to 4 scan F / F 5 to 7 internal combination circuit 8 semiconductor chip 9 resistive paste material 10 bed portion 11, 12, 14, 15 terminal 13 diode

Claims (5)

[Claims] 1. A semiconductor device comprising an activation signal supply circuit that self-oscillates during a burn-in test and continuously supplies an activation signal to a circuit under test. 2. The activation signal supply circuit comprises a flip-flop circuit group for scanning and inputting test data supplied to a circuit under test during a test other than a burn-in test. Semiconductor device. 3. A semiconductor device, comprising a semiconductor chip fixed to a bed portion, and having an internal heating means made of a resistive paste material for heating the semiconductor chip by supplying heat during a burn-in test to heat the semiconductor chip. 4. A semiconductor device comprising an internal heating means which is connected in series or in parallel and which is supplied with a current during a burn-in test to generate heat and heat a semiconductor chip. 5. The semiconductor device according to claim 1, further comprising an internal heating unit according to claim 3 or 4.