JPH0795536B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a CMOS LSI.
The present invention relates to a method of manufacturing a semiconductor device in which latch-up, which is a phenomenon peculiar to the above, is prevented and the PR process in the manufacturing process is simplified.

[Conventional technology]

Conventionally, a CMOS LSI well is formed by single ion implantation and activation heat treatment, and the impurity concentration inside the well is highest near the substrate surface, as shown in the conventional well impurity distribution in FIG. Similarly, the concentration decreases as the depth from the substrate surface increases.

[Problems to be Solved by the Invention] The impurity distribution in the well formed by the conventional well formation method described above is a distribution in which the concentration monotonously decreases as the depth becomes deeper than the substrate surface. In order to make the inside of the well sufficiently low resistance, there is a drawback that raising the impurity concentration raises the threshold voltage of the transistor in the well region. Due to diffusion, a wide channel separation region is required, which is disadvantageous for high integration. For the above reasons, the well with the conventional structure cannot sufficiently reduce the resistance, and the bipolar transistor parasitic on the CMOS structure has a large current amplification factor due to the substrate resistance, and thus the thyristor composed of the parasitic bipolar transistor is used. It has the drawback of being easy to operate.

An object of the present invention is to cancel impurities near the surface of the well, keep the threshold voltage of the transistor in the well region as it is, to make the inside of the well have a low resistance due to the high impurity concentration, and Another object of the present invention is to provide a method for manufacturing a semiconductor device, which can omit the PR step required for ion implantation for preventing punch-through of the transistor arranged in the above.

[Means for solving problems]

A feature of the present invention is to implant a high-concentration impurity ion of one conductivity type into a semiconductor substrate through an impurity mask, and
To form a high concentration well of one conductivity type, a step of implanting impurity ions of opposite conductivity type near the surface of the high concentration well of one conductivity type, and a second activation heat treatment. The method for manufacturing a semiconductor device has a step of performing the above, thereby obtaining a well of one conductivity type having a low concentration of one conductivity type impurity distribution in the vicinity of the surface from the inside and forming a transistor therein.

Further, after the well is formed on the entire surface of the semiconductor substrate between the step of implanting the impurity ions of the opposite conductivity type near the surface of the high-concentration well of one conductivity type and the step of performing the second activation heat treatment, the well is arranged outside the well region By performing ion implantation for preventing punch through of the transistor to be formed, a semiconductor device manufacturing method can be obtained in which the PR step conventionally required for this implantation can be omitted.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 (a) to 1 (e) are cross-sectional views of the element shown in the order of steps for explaining one embodiment of the present invention.

First, as shown in FIG. 1A, after the pre-well formation oxidation, a pattern of the photoresist film 3 for forming the well is formed by a PR process. Then, phosphorus (P ⁺ ) ions are implanted with an energy of 150 keV and a dose amount of 5.0 × 10 ¹³ atm / cm ² .

Next, as shown in FIG. 1 (b), the injected phosphorus (P ⁺ )
To activate N and form a high concentration N well 4,
Heat treatment at ℃ for 120 minutes in nitrogen atmosphere.

Next, as shown in FIG. 1 (c), boron (B ⁺ ) is applied to the high concentration N well 4 at an energy of 100 keV and a dose amount.
Counter ion implantation is performed in the N well region at 2.2 × 10 ¹³ atm / cm ² .

Next, as shown in FIG. 1 (d), in order to prevent punch-through on the N-channel side, boron (B ⁺ ) energy of 150 keV,
Ions are implanted on the entire surface of the wafer at a dose of 4.0 × 10 ¹¹ atm / cm ² .

Next, as shown in FIG. 1 (e), a second heat treatment is performed at 1200 ° C. in a nitrogen atmosphere to activate the ion-implanted boron in FIGS. 1 (c) and 1 (d). For 30 minutes. This makes it possible to obtain an N well composed of a low concentration N well 6 near the surface and a high concentration N well 7 of low resistance (sheet resistance ρ _s 300 Ω / □), and ion implantation for punch-through prevention on the N channel side. The PR step required at the time of performing the step can be omitted. The junction depth of the N well obtained here is about 5 μm.

Although one of the embodiments has been described above, the resistance value of the N well can be controlled by ion implantation of the N well and its counter ion implantation, and the junction depth of the N well can be controlled by heat treatment. It can be controlled by temperature and time.

Note that FIG. 2 is a diagram comparing the impurity concentration distribution on the line AA ′ in FIG.

〔The invention's effect〕

As described above, according to the present invention, by performing high-concentration well ion implantation, first heat treatment, counter ion implantation, and second heat treatment, impurities near the well surface are canceled out, and a transistor in the well region is protected. The threshold voltage can be maintained as it is, and the inside of the well can have a low resistance due to the high impurity concentration. CMOS is used to reduce well resistance
Since the current amplification factor of the bipolar transistor that contributes to the structure can be reduced, it is possible to prevent the thyristor formed by the parasitic bipolar transistor from operating, and it is very effective in preventing latch-up.

In addition, the ion implantation for preventing punch-through of the transistor arranged outside the well region can be omitted by performing the ion implantation on the entire surface of the wafer between the counter ion implantation and the second heat treatment. To be

[Brief description of drawings]

1 (a) to 1 (e) are sectional views of the device shown in order of steps for explaining one embodiment of the present invention, and FIG. 2 is an impurity concentration on line AA 'in FIG. 1 (e). It is a figure which compared the distribution of with the conventional one. 1 ... P-type semiconductor substrate, 2 ... silicon oxide film, 3 ...
Photoresist film, 4 ... High concentration N well, 5 ... High concentration N well, 6 ... Low concentration well.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/092

Claims (2)

[Claims] 1. A step of implanting a high-concentration impurity ion of one conductivity type into a semiconductor substrate through an impurity mask, a step of performing a first activation heat treatment to form a high-concentration well of one conductivity type, The method has a step of implanting impurity ions of the opposite conductivity type near the surface of a high-concentration well of one conductivity type and a step of performing a second activation heat treatment. A method of manufacturing a semiconductor device, characterized in that a well of one conductivity type having a distribution of impurities and forming a transistor therein is obtained. 2. A well region formed after the well is formed over the entire surface of the semiconductor substrate between the step of implanting impurity ions of the opposite conductivity type near the surface of the high-concentration well of one conductivity type and the step of performing the second activation heat treatment. The method of manufacturing a semiconductor device according to claim (1), characterized in that ion implantation is performed to prevent punch-through of a transistor arranged outside.