JPH078773U - Speed detector - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a speed detection device capable of improving speed calculation accuracy and detecting speed and acceleration / deceleration with high accuracy. A counter circuit 2 for performing a free-run count of the number of speed pulses output from a speed generator in accordance with the rotation of wheels of a transportation device, and a reference clock generation circuit 4
A counter circuit 12 for performing a free-run count of the clock output from the counter circuit 2 and a counter circuit 2 for each sampling period.
Circuit for latching the value of the counter circuit 12 and the latch circuit 13 for latching the value of the counter circuit 12 for each cycle of the speed pulse.
A latch circuit 15 for latching the value of the counter circuit 12 at the time of outputting the first speed pulse after the start of the sampling period, and the latch circuits 3, 13, 1 for each sampling period.
RAM memory for storing the value latched in 5, and RAM
A CPU for calculating the velocity and the acceleration / deceleration during the calculation period that is an integral multiple of the sampling period is provided based on the value stored in the memory.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a speed detection device that detects, for example, the speed and acceleration / deceleration of a railway vehicle.

[0002]

[Prior art]

 In railway vehicles and the like, it is necessary to prevent scratches between wheels and rails during braking and to keep the braking distance as short as possible. In this case, in order to reduce the relative slippage that occurs between the wheel and the rail during braking, the vehicle speed and the deceleration during deceleration are detected in a short time and with high accuracy, and the braking force is controlled accordingly. You need this.

For this purpose, a speed generator that rotates a gear corresponding to rotation of a wheel of a railway vehicle or the like to generate a pulse (hereinafter, referred to as a speed pulse) has been conventionally installed, and the number of pulses thereof is set. An apparatus has been developed that detects the speed and acceleration / deceleration of a vehicle or the like by counting the number of times every predetermined sampling period. The applicant has already proposed Japanese Patent Application No. 4-20292 as an example of this type of device.

FIG. 4 is a block diagram showing a configuration of a detection circuit of the speed detection device disclosed in Japanese Patent Application No. 4-20292. In this figure, 1 is a waveform shaping circuit, which shapes the speed pulse PLS output from a speed generator (not shown) and outputs it as a speed pulse P LS1. A counter circuit 2 counts the speed pulse PLS1 output from the waveform shaping circuit 1 and outputs this count value CNT. A latch circuit 3 receives the latch signal LAT output from the reference clock generation circuit 4 and latches the count value CNT output from the counter circuit 2.

The reference clock generation circuit 4 outputs an interrupt signal INT to a CPU (central processing unit) (not shown) at regular intervals τ (hereinafter referred to as sampling period τ). Upon receiving the interrupt signal INT, the CPU outputs a read command RCV to the latch circuit 3. The latch circuit 3 outputs the latched count value CNT to the CPU as the speed pulse count value of the speed generator in response to the read command RCV. The counter circuit 2 is cleared by the clear signal CLR output from the reference clock generation circuit 4.

Reference numeral 11 is a D flip-flop. A speed pulse PLS1 output from the waveform shaping circuit 1 is input to the D flip-flop 11 as a clock CK, and a high level signal is always input as data D. The D flip-flop 11 is cleared by the clear signal CLR output from the reference clock generation circuit 4. Reference numeral 14 denotes an AND gate, which takes an AND between the output signal Q of the D flip-flop 11 and the clock signal CLK output from the reference clock generation circuit 4 and outputs the result as a clock signal CLK2.

Reference numeral 12 is a counter circuit. The counter circuit 12 counts the clock signal CLK2 output from the AND gate 14, outputs the count value CNT12, and is cleared by the clear signal CLR output from the reference clock generation circuit 4. Reference numeral 13 is a latch circuit, which latches the count value CNT12 of the counter circuit 12 according to a latch signal LAT13 output from the reference clock generation circuit 4 based on the speed pulse PLS1. Further, the latch circuit 13 outputs the latched count value CNT12 to the CPU in response to the read command RCV2 supplied from the CPU.

The counter circuit 12 outputs an overflow signal OFL to the CPU when the vehicle speed becomes equal to or lower than a predetermined speed and the count value exceeds the predetermined value. From this, the CPU identifies that the speed and acceleration / deceleration cannot be detected below the current speed.

Next, the operation of the detection circuit will be described with reference to the timing chart of each signal shown in FIG. First, when the interrupt signal INT is raised by the reference clock generation circuit 4, the CPU performs an interrupt process described later. When the interrupt signal INT is raised, the latch signal LAT having a predetermined pulse width is output from the reference clock generation circuit 4 to the latch circuit 3, and the count value CNT of the counter circuit 2 is latched by the latch circuit 3. It When the latch signal LAT is output, a clear signal CLR having a predetermined pulse width is output from the reference clock generation circuit 4, and the counter circuits 2 and 12 and the D flip-flop 11 are cleared.

After that, when the speed pulse PLS1 rises for the first time, the counter circuit 2 starts counting the speed pulse PLS1 and thereafter counts up each time the speed pulse PLS1 rises. On the other hand, the counter circuit 12 starts counting the number of clocks of the clock signal CLK from the first rising of the speed pulse PLS1. Then, each time the speed pulse PLS1 rises, a latch signal LAT13 having a predetermined pulse width is output from the reference clock generation circuit 4 to the latch circuit 13, and the count value CNT12 of the counter circuit 12 at this time is latched by the latch circuit 13. R.

When the interrupt signal INT is raised again by the reference clock generation circuit 4, the reference clock generation circuit 4 outputs the latch signal LAT, and the count value CNT of the counter circuit 2 at this time is latched by the latch circuit 3. To be done. In addition, immediately after the latch signal LAT is output, the clear signal CLR is output from the reference clock generation circuit 4, whereby the counter circuits 2 and 12 and the D flip-flop 11 are cleared. Thus, immediately after the rise of the interrupt signal INT, the value of A in the figure is latched in the latch circuit 3, and the value of B in the figure is latched in the latch circuit 13.

On the other hand, the CPU outputs a read command RC V to the latch circuit 3 in response to the rising edge of the interrupt signal INT. As a result, the count value CNT latched by the latch circuit 3 is supplied to the CPU. The CPU subtracts "1" from the count value CNT to obtain the speed pulse count value. Further, the CPU outputs a read command RCV2 to the latch circuit 13 in response to the rising edge of the interrupt signal INT. As a result, the count value CNT12 latched by the latch circuit 13, that is, the clock count value in the period corresponding to the speed pulse count value is supplied to the CPU.

Further, the CPU uses the velocity pulse count value obtained as described above and the clock count value of the period corresponding to this velocity pulse count value, based on the following mathematical formulas. Calculate deceleration during deceleration. First, as shown in FIG. 6, the sampling period rate pulses in τ count a n _t, when the clock count value of the period that corresponds to the speed pulse count n _t and N _t, the clock count value N _t The speed pulse counting period t _t converted to time (sec) is t _t = 1 / F ₀ × N _t ……………………………………………… (1) F ₀ : Reference clock generation It is given by the clock frequency (H _Z ) of the circuit 4. The speed pulse count value n _t is: n _t = (P × 10 ³ ) / (3.6 × π × D) × V × t _t (2) P: Pulse generated per revolution of the speed generator Number D: Wheel diameter (mm) π: Circularity V: Given by vehicle speed (km / h). Then, by setting (P × 10 ³ ) / (3.6 × π × D) = K and transforming the equation (2), the velocity V is V = n _t / (K × t _t ) ... ……………………………………… given by (3).

Further, as shown in FIG. 6, the velocity pulse count value is n _{t + 1} and the velocity pulse count is n _{t + 1} in the sampling period τ next to the period in which the velocity pulse count value n _t and the velocity pulse count period _tt are obtained. When the period is t _{t + 1} , the deceleration β during deceleration is β = 1 / (K × τ) × (n _t / t _t −n _{t + 1} / t _{t + 1} ) ... (4 ) Given by.

Thus, within the sampling period τ, the count value n _t of the speed pulse in which a pulse waveform for one cycle of the speed pulse output from the speed generator is output, and the output of the counted speed pulse The traveling speed and deceleration of the vehicle are calculated on the basis of the measured value N _{t of} the time required for.

[0016]

[Problems to be solved by the device]

 By the way, in the above-described conventional speed detection device, in order to improve the speed detection accuracy, a method of performing speed calculation in a cycle of an integral multiple (2 times, 3 times, etc.) of the sampling period τ can be considered. However, in the above-described conventional speed detection device, since the count values of the counter circuits 2 and 12 are cleared for each sampling period τ (see FIG. 5), the speed calculation is performed for a period in which a plurality of sampling periods τ are collected. As a result, the detection accuracy could not be improved even if the above procedure was performed.

The present invention has been made under such a background, and provides a speed detecting device capable of improving speed calculation accuracy and detecting speed and acceleration / deceleration with high accuracy. Has an aim.

[0018]

[Means for Solving the Problems]

 In order to solve the above-mentioned problems, the present invention is directed to a detection device for detecting the speed and acceleration / deceleration of a transportation device based on a speed pulse output from a speed generator according to the rotation of wheels of the transportation device. Counting means for counting the number of output pulses of the speed pulse; timing means for counting the number of clocks of a predetermined clock pulse; first holding means for holding the count value of the counting means for each predetermined sampling period; Second holding means for holding the count value of the time counting means for each cycle of the speed pulse, and the time keeping means for the time point at which the speed pulse is first output after the start of the period for each sampling period Third holding means for holding the count value, and a storage means for fetching the count value held in the first to third holding means for each sampling period and storing these And a first arithmetic unit that calculates a traveling speed of the transportation device in a predetermined arithmetic period that is an integral multiple of the sampling period, based on the count value stored in the storage unit; A second calculation means for calculating the acceleration or deceleration of the transportation device based on the calculated traveling speeds in two adjacent calculation periods.

[0019]

[Action]

 According to the present invention, the counting means counts the number of output pulses of the speed pulse, the clocking means counts the number of clocks of a predetermined clock pulse, and the first holding means counts every predetermined sampling period. The count value of the means is held, the second holding means holds the count value of the time counting means for each cycle of the speed pulse, and the third holding means holds the count value for each of the sampling periods after the start of the period. The measured value of the time measuring means at the time when the speed pulse is first output is held. Then, the storage means fetches the count values held in the first to third holding means for each sampling period and stores them. Further, the first calculation means calculates the traveling speed of the transportation device during a predetermined calculation period obtained by multiplying the sampling period by an integer based on the count value stored in the storage means, and the second calculation means causes the first calculation means to calculate the traveling speed. The acceleration or deceleration of the transportation device is calculated based on the traveling speeds in the two adjacent calculation periods calculated by the calculation device. As a result, the velocity is calculated for an integral multiple of the sampling period based on the count value that is not cleared for each sampling period, and the calculation accuracy of the velocity and acceleration / deceleration is improved.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the structure of a detection circuit of a speed detection device according to an embodiment of the present invention. In this figure, parts that are the same as the parts shown in FIG. 4 are assigned the same reference numerals and explanations thereof are omitted.

In FIG. 1, the counter circuit 2 free-run counts the speed pulse PLS 1 without being cleared by the clear signal CLR output from the reference clock generation circuit 4. The counter circuit 12, like the counter circuit 2, directly fetches the clock signal CLK output from the reference clock generation circuit 4 without being cleared by the clear signal CLR output from the reference clock generation circuit 4, Free run count this.

The latch circuit 15 latches the count value CNT12 of the counter circuit 12 according to the output Q (latch signal LAT15) of the D flip-flop 11. Further, the latch circuit 15 outputs the latched count value CNT12 to the CPU in response to the read command RCV3 supplied from the CPU.

Next, the operation of this detection circuit will be described with reference to the timing chart of each signal shown in FIG. First, when the interrupt signal INT output from the reference clock generation circuit 4 rises (time T ₀ ), the CPU performs an interrupt process described later. When the interrupt signal INT rises, the reference clock generation circuit 4 outputs the latch signal LAT to the latch circuit 3. As a result, the latch circuit 3 latches the count value CNT (n1 in the figure) of the counter circuit 2 that counts the rising of the speed pulse PLS1. Further, after the latch signal LAT is output, the clear signal CLR is output from the reference clock generation circuit 4, whereby the D flip-flop 11 is cleared.

After that, when the speed pulse PLS1 rises for the first time, the output Q of the D flip-flop 11 becomes High level, and this is supplied to the latch circuit 15 as the latch signal LAT15. As a result, the count value CNT (N1 in the figure) of the counter circuit 12 that counts the clock signal CLK is latched by the latch circuit 15.

Further, each time the speed pulse PLS 1 rises, the latch signal LAT 13 is output from the reference clock generation circuit 4 to the latch circuit 13. As a result, the count value CNT12 (N1, N2, ... In the drawing) of the counter circuit 12 is latched by the latch circuit 13.

Then, when the interrupt signal INT rises again (time T ₁ ), the reference clock generation circuit 4 outputs the latch signal LAT, and the count value CNT (n 3 shown in the figure) of the counter circuit 2 at this time is the latch circuit 3. Latched by. Immediately after the latch signal LAT is output, the D flip-flop 11 is cleared by the clear signal CLR. After that, when the speed pulse PLS1 rises for the first time, the output Q of the D flip-flop 11 becomes High again, whereby the count value CNT12 (N3 in the figure) of the counter circuit 12 is latched by the latch circuit 15. After that, the above-described operation is repeated in response to the rising edge of the interrupt signal INT and the rising edge of the speed pulse PLS1.

On the other hand, the CPU outputs read commands RCV, RCV2, RCV3 to the latch circuits 3, 13, 15 each time the interrupt signal INT rises (time T ₀ , T ₁ , T ₂ , ...), Take the value latched in each. Then, it is sequentially stored in a RAM memory (not shown) in the form of the table shown in FIG.

Then, the CPU calculates the speed and the deceleration for a period that is an integral multiple of the sampling period τ. For example, the velocity V1 in the period twice the sampling period τ (the period from time T ₀ to time T ₂ ) is

[Equation 1] (However, K = (P × 10 ³ ) / (3.6 × π × D)). At this time, if the speed in the period from time T ₁ to time T ₃ is V2, the deceleration β is

[Equation 2] Given by.

As described above, according to the present embodiment, the counter circuits 2 and 12 are free-run counters that are not cleared every sampling period τ 2, and the values of the latch circuits 3, 13 and 15 for each sampling period τ 2. Are sequentially stored in the RAM memory, the speed and deceleration (or acceleration) can be detected with higher accuracy than before by calculating the speed for an integral multiple of the sampling period τ.

According to the present embodiment, it is also possible to calculate the velocity and deceleration (or acceleration) by performing the calculation for each sampling period τ, as in the above-mentioned conventional example. In this case, for example, the velocity V1 ′ (see FIG. 2) in the sampling period τ from time T ₀ to time T ₁ is

[Equation 3] Given by. At this time, if the speed in the sampling period τ from time T ₁ to time T ₂ is V2 ′ (see FIG. 2), the deceleration β ′ is

[Equation 4] Given by.

[0031]

[Effect of device]

 As described above, according to the present invention, the velocity is calculated for an integral multiple of the sampling period based on the count value that is not cleared for each sampling period, and the calculation accuracy of the velocity and the acceleration / deceleration is calculated. As a result, the speed and acceleration / deceleration can be detected with high accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a detection circuit of a speed detection device according to an embodiment of the present invention.

FIG. 2 is a timing chart of each signal in the same circuit.

FIG. 3 is a diagram showing stored contents of a RAN memory according to the embodiment.

FIG. 4 is a block diagram showing a configuration of a detection circuit of a speed detection device according to a conventional example.

FIG. 5 is a timing chart of each signal in the same circuit.

FIG. 6 is a diagram showing velocity pulses counted in each sampling period in the same circuit.

[Explanation of symbols]

 1 waveform shaping circuit 2, 12 counter circuit 3, 13, 15 latch circuit 4 reference clock generation circuit 11 D flip-flop 14 AND gate

Claims (1)

[Scope of utility model registration request] 1. A detection device for detecting the velocity and acceleration / deceleration of the transportation device based on the velocity pulse output from a speed generator according to the rotation of wheels of the transportation device, wherein the number of output pulses of the velocity pulse is Counting means for counting the number of clocks of a predetermined clock pulse, first holding means for holding the count value of the counting means for each predetermined sampling period, and for each cycle of the speed pulse Second holding means for holding the count value of the timekeeping means, and third holding means for holding the count value of the timekeeping means at the time when the speed pulse is first output after the start of the period for each sampling period. Means, storage means for loading the count values held in the first to third holding means for each sampling period and storing the count values, and a storage means stored in the storage means. First computing means for computing a traveling speed of the transportation device in a predetermined computation period that is an integral multiple of the sampling period based on the value; and traveling in two adjacent computation periods calculated by the first computation device. And a second calculation means for calculating the acceleration or deceleration of the transportation device based on the speed.