JPH078772U - Speed detector - Google Patents

Abstract

(57) [Summary] [Purpose] A speed detection device capable of detecting speed and acceleration / deceleration even in a low speed region even if the sampling period for speed detection is shortened in order to detect speed in a short time. I will provide a. A counter circuit 2 for performing a free-run count of the number of speed pulses output from a speed generator according to the rotation of wheels of a transportation device, and a reference clock generation circuit 4
A counter circuit 12 for performing a free-run count on the number of clocks of a clock signal output from the latch circuit 3; Latch circuit 13 for latching the count value of the speed pulse count value and the latch circuit 13 obtained by the difference between the values latched by the latch circuit 3 every sampling period.
A CPU for calculating the speed and the acceleration / deceleration based on the clocked value obtained by the difference between the values latched in is provided.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a speed detection device that detects, for example, the speed and acceleration / deceleration of a railway vehicle.

[0002]

[Prior art]

 In railway vehicles and the like, it is necessary to prevent scratches between wheels and rails during braking and to keep the braking distance as short as possible. In this case, in order to reduce the relative slippage that occurs between the wheel and the rail during braking, the vehicle speed and the deceleration during deceleration are detected in a short time and with high accuracy, and the braking force is controlled accordingly. You need this.

For this purpose, a speed generator that rotates a gear corresponding to rotation of a wheel of a railway vehicle or the like to generate a pulse (hereinafter, referred to as a speed pulse) has been conventionally installed, and the number of pulses thereof is set. An apparatus has been developed that detects the speed and acceleration / deceleration of a vehicle or the like by counting the number of times every predetermined sampling period. The applicant has already proposed Japanese Patent Application No. 4-20292 as an example of this type of device.

FIG. 4 is a block diagram showing a configuration of a detection circuit of the speed detection device disclosed in Japanese Patent Application No. 4-20292. In this figure, 1 is a waveform shaping circuit, which shapes the speed pulse PLS output from a speed generator (not shown) and outputs it as a speed pulse P LS1. A counter circuit 2 counts the speed pulse PLS1 output from the waveform shaping circuit 1 and outputs this count value CNT. A latch circuit 3 receives the latch signal LAT output from the reference clock generation circuit 4 and latches the count value CNT output from the counter circuit 2.

The reference clock generation circuit 4 outputs an interrupt signal INT to a CPU (central processing unit) (not shown) at regular intervals τ (hereinafter referred to as sampling period τ). Upon receiving the interrupt signal INT, the CPU outputs a read command RCV to the latch circuit 3. The latch circuit 3 outputs the latched count value CNT to the CPU as the speed pulse count value of the speed generator in response to the read command RCV. The counter circuit 2 is cleared by the clear signal CLR output from the reference clock generation circuit 4.

Reference numeral 11 is a D flip-flop. A speed pulse PLS1 output from the waveform shaping circuit 1 is input to the D flip-flop 11 as a clock CK, and a high level signal is always input as data D. The D flip-flop 11 is cleared by the clear signal CLR output from the reference clock generation circuit 4. Reference numeral 14 denotes an AND gate, which takes an AND between the output signal Q of the D flip-flop 11 and the clock signal CLK output from the reference clock generation circuit 4 and outputs the result as a clock signal CLK2.

Reference numeral 12 is a counter circuit. The counter circuit 12 counts the clock signal CLK2 output from the AND gate 14, outputs the count value CNT12, and is cleared by the clear signal CLR output from the reference clock generation circuit 4. Reference numeral 13 is a latch circuit, which latches the count value CNT12 of the counter circuit 12 according to a latch signal LAT13 output from the reference clock generation circuit 4 based on the speed pulse PLS1. Further, the latch circuit 13 outputs the latched count value CNT12 to the CPU in response to the read command RCV2 supplied from the CPU.

The counter circuit 12 outputs an overflow signal OFL to the CPU when the vehicle speed becomes equal to or lower than a predetermined speed and the count value exceeds the predetermined value. From this, the CPU identifies that the speed and acceleration / deceleration cannot be detected below the current speed.

Next, the operation of the detection circuit will be described with reference to the timing chart of each signal shown in FIG. First, when the interrupt signal INT is raised by the reference clock generation circuit 4, the CPU performs an interrupt process described later. When the interrupt signal INT is raised, the latch signal LAT having a predetermined pulse width is output from the reference clock generation circuit 4 to the latch circuit 3, and the count value CNT of the counter circuit 2 is latched by the latch circuit 3. It When the latch signal LAT is output, the clear signal CLR having a predetermined pulse width is output from the reference clock generation circuit 4, and the counter circuits 2 and 12 and the D flip-flop 11 are cleared.

After that, when the speed pulse PLS1 rises for the first time, the counter circuit 2 starts counting the speed pulse PLS1 and thereafter counts up each time the speed pulse PLS1 rises. On the other hand, the counter circuit 12 starts counting the number of clocks of the clock signal CLK from the first rising of the speed pulse PLS1. Then, each time the speed pulse PLS1 rises, a latch signal LAT13 having a predetermined pulse width is output from the reference clock generation circuit 4 to the latch circuit 13, and the count value CNT12 of the counter circuit 12 at this time is latched by the latch circuit 13. R.

When the interrupt signal INT is raised again by the reference clock generation circuit 4, the reference clock generation circuit 4 outputs the latch signal LAT, and the count value CNT of the counter circuit 2 at this time is latched by the latch circuit 3. To be done. In addition, immediately after the latch signal LAT is output, the clear signal CLR is output from the reference clock generation circuit 4, whereby the counter circuits 2 and 12 and the D flip-flop 11 are cleared. Thus, immediately after the rise of the interrupt signal INT, the value of A in the figure is latched in the latch circuit 3, and the value of B in the figure is latched in the latch circuit 13.

On the other hand, the CPU outputs a read command RC V to the latch circuit 3 in response to the rising edge of the interrupt signal INT. As a result, the count value CNT latched by the latch circuit 3 is supplied to the CPU. The CPU subtracts "1" from the count value CNT to obtain the speed pulse count value. Further, the CPU outputs a read command RCV2 to the latch circuit 13 in response to the rising edge of the interrupt signal INT. As a result, the count value CNT12 latched by the latch circuit 13, that is, the clock count value in the period corresponding to the speed pulse count value is supplied to the CPU.

Further, the CPU uses the velocity pulse count value obtained as described above and the clock count value of the period corresponding to this velocity pulse count value, based on the following mathematical formulas. Calculate deceleration during deceleration. First, as shown in FIG. 6, the sampling period rate pulses in τ count a n _t, when the clock count value of the period that corresponds to the speed pulse count n _t and N _t, the clock count value N _t The speed pulse counting period t _t converted to time (sec) is t _t = 1 / F ₀ × N _t …………………………………………… (1) F ₀ : Reference clock generation It is given by the clock frequency (H _Z ) of the circuit 4. The speed pulse count value n _t is: n _t = (P × 10 ³ ) / (3.6 × π × D) × V × t _t (2) P: Pulse generated per revolution of the speed generator Number D: Wheel diameter (mm) π: Circularity V: Given by vehicle speed (km / h). Then, by setting (P × 10 ³ ) / (3.6 × π × D) = K and transforming the equation (2), the velocity V is V = n _t / (K × t _t ) ... ……………………………………… given by (3).

Further, as shown in FIG. 6, the velocity pulse count value is n _{t + 1} and the velocity pulse count is n _{t + 1} in the sampling period τ next to the period in which the velocity pulse count value n _t and the velocity pulse count period _tt are obtained. When the period is t _{t + 1} , the deceleration β during deceleration is β = 1 / (K × τ) × (n _t / t _t −n _{t + 1} / t _{t + 1} ) ... (4 ) Given by.

Thus, within the sampling period τ, the count value n _t of the speed pulse in which a pulse waveform for one cycle of the speed pulse output from the speed generator is output, and the output of the counted speed pulse The traveling speed and deceleration of the vehicle are calculated on the basis of the measured value N _{t of} the time required for.

[0016]

[Problems to be solved by the device]

By the way, in the above-described conventional speed detecting device, if the sampling period τ is shorter than the time interval at which the speed pulse PLS1 of 2 pulses is output, speed detection cannot be performed. That is, as shown in FIG. 7, when the rising of the speed pulse PLS1 occurs twice or more within the sampling period τ (T1 in the figure), the speed pulse count value n _t becomes n _t = 1 so that speed detection is possible. However, if the rise of the velocity pulse PLS1 appears only once within the sampling period τ (T2 in the figure), the velocity pulse count value n _t becomes n _t = 0, and velocity detection becomes impossible. Therefore, the shortest sampling period τ capable of speed detection is the time interval at which the speed pulse PLS1 of two pulses is output. At this time, the minimum speed V of the vehicle capable of speed detection is given by: V = (2 × 3.6 × π × D) / (P × 10 ³ × τ) (5) If the sampling period τ is shortened in order to detect the speed at, the minimum speed V at which the speed can be detected becomes high, and it becomes impossible to detect the low speed area.

The present invention has been made under such a background. Even if the sampling period for speed detection is shortened in order to detect speed in a short time, the speed and acceleration It is an object of the present invention to provide a speed detection device capable of detecting deceleration.

[0018]

In order to solve the above-mentioned problems, the invention according to claim 1 is based on a speed pulse output from a speed generator according to rotation of wheels of a transportation device, In a detection device for detecting the speed and acceleration / deceleration of the device, counting means for counting the output pulse number of the speed pulse, time counting means for counting the clock number of a predetermined clock pulse, and for each predetermined sampling period First holding means for holding the count value of the counting means, second holding means for holding the count value of the time counting means in each cycle of the speed pulse, and held by the first holding means First subtraction means for calculating a difference between count values at the start time and end time of the sampling period and outputting the result as a speed pulse count value during the sampling period; Second subtraction means for calculating a difference between the count values at the start time and the end time of the sampling period held by the holding means, and outputting the result as a time count value for the period corresponding to the speed pulse count value. A first calculation means for calculating a traveling speed of the transportation device based on the speed pulse count value and the time count value; and two adjacent sampling periods calculated by the first calculation device. A second calculation means for calculating the acceleration or deceleration of the transportation device based on the traveling speed.

The invention according to claim 2 is the device according to claim 1, wherein the storage means for fetching the values held in the first and second holding means for each sampling period and storing them The first and second subtraction means calculate a difference between count values for a predetermined operation period that is an integral multiple of the sampling period, and the first operation means includes the first and second subtraction means. Based on the calculation result of the subtraction unit, the traveling speed is calculated for the calculation period, and the second calculation unit is configured to calculate the traveling speed based on the traveling speeds of the two adjacent calculation periods calculated by the first calculation device. It is characterized by calculating acceleration or deceleration.

[0020]

[Action]

 According to the invention as set forth in claim 1, the counting means counts the number of output pulses of the speed pulse, the time counting means counts the number of clocks of a predetermined clock pulse, and the first holding means controls the predetermined sampling period. The count value of the counting means is held for each time, and the second holding means holds the count value of the time measuring means for each cycle of the speed pulse. Then, the first subtraction means calculates a difference between the count values at the start time and the end time of the sampling period held by the first holding means, and outputs the result as a velocity pulse count value in the sampling period. Then, the second subtraction means calculates the difference between the count values at the start time and the end time of the sampling period held by the second holding means, and the result is the period corresponding to the speed pulse count value. It is output as the measured value of. Further, the first calculating means calculates the traveling speed of the transportation device based on the speed pulse count value and the timekeeping value, and the second calculating means calculates the adjacent speed calculated by the first calculating device. The acceleration or deceleration of the transportation device is calculated based on the traveling speed during the two sampling periods. This makes it possible to detect the velocity and acceleration / deceleration even when the rise (or fall) of the velocity pulse does not appear more than once within the sampling period.

According to the second aspect of the invention, the storage means fetches the values held in the first and second holding means for each sampling period and stores them, and stores the first and second values. The second subtraction means calculates a difference in numerical value for a predetermined calculation period that is an integral multiple of the sampling period, and the first calculation means calculates the difference between the calculation periods based on the calculation results of the first and second subtraction means. The traveling speed is calculated, and the second calculating means calculates the acceleration or the deceleration based on the traveling speeds in the two adjacent calculation periods calculated by the first arithmetic device. As a result, in addition to the effect of the device according to claim 1, the velocity is calculated for an integral multiple of the sampling period based on the count value whose value is not cleared for each sampling period, and the calculation accuracy of the velocity and the acceleration / deceleration is calculated. Is improved.

[0022]

【Example】

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the structure of a detection circuit of a speed detection device according to an embodiment of the present invention. In this figure, parts that are the same as the parts shown in FIG. 4 are assigned the same reference numerals and explanations thereof are omitted. The embodiment shown in FIG. 1 is different from the conventional example shown in FIG. 4 in that the D flip-flop 11 and the AND gate 14 are omitted, and the clock signal CLK output from the reference clock generation circuit 4 is directly output. The counter circuit 2, 12 is supplied to the counter circuit 12 and is free-run-counted for each input pulse PLS1, CLK without being cleared by the clear signal CLR. In this case, the capacitance N of the counter circuit 12 is N> τ / (1 / F ₀ ) ... ………………………………………… (6) τ: Sampling period F ₀ : It is set to satisfy the clock frequency of the reference clock generation circuit 4. Further, the method of calculating the speed and the deceleration by the interrupt processing of the CPU (not shown) is also different from the above-mentioned conventional example, but the details will be described later.

Next, the operation of this detection circuit will be described with reference to the timing chart of each signal shown in FIG. First, when the interrupt signal INT output from the reference clock generation circuit 4 rises, the CPU performs the interrupt processing described later, and the latch signal LAT having a predetermined pulse width is output from the reference clock generation circuit 4 to the latch circuit 3. Be done. At this time, the count value CNT of the speed pulse PLS1 from the counter circuit 2 is latched by the latch circuit 3. After that, the above operation is repeated each time the interrupt signal INT rises.

On the other hand, when the speed pulse PLS1 rises, the counter circuit 2 counts up and the latch signal LAT13 having a predetermined pulse width is output from the reference clock generation circuit 4 to the latch circuit 13. At this time, the count value CNT12 of the clock signal CLK from the counter circuit 12 is latched by the latch circuit 13. After that, the above operation is repeated every time the speed pulse PLS1 rises.

When the interrupt signal INT rises, the CPU outputs a read command RCV to the latch circuit 3 and a read command RCV2 to the latch circuit 13. As a result, the count values CNT and CNT12 latched in the latch circuits 3 and 13 are supplied to the CPU.

Thus, for example, immediately after the rise of the interrupt signal INT corresponding to the beginning of the sampling period τk, the value of A ′ shown in the figure, which is latched in the latch circuit 3 at this time, and the value in the latch circuit 13 is latched. The value of B'shown in the figure is supplied to the CPU. Immediately after the rising edge of the interrupt signal INT corresponding to the end of the sampling period τk, the value shown in FIG. A latched in the latch circuit 3 and the value shown in B shown in the latch circuit 13 are latched. And are supplied to the CPU.

Thus, for example, as shown in FIG. 3, for each sampling period τ1, τ2, τ3, τ4, ... Velocity pulse count values (n3-n1), (n6-n3), (n8-n6) , (N11-n8), ... And the clock count values (N3-N1), (N6-N3), (N8-N6), (N11-N8) ,. Is supplied to.

Then, the CPU calculates the speed and the deceleration based on the mathematical formulas shown below. For example, the velocity V1 in the sampling period τ1 is

[Equation 1] (However, K = (P × 10 ³ ) / (3.6 × π × D)). At this time, if the speed in the sampling period τ2 is V2, the deceleration β in the sampling periods τ1 and τ2 is

[Equation 2] Given by.

As described above, according to this embodiment, the speed and the deceleration (or the acceleration) can be detected even when the rising of the speed pulse PLS1 does not appear twice or more within the sampling period τ. Therefore, even if the sampling period for speed detection is shortened in order to detect the speed in a short time, the speed and the acceleration / deceleration can be detected even in the low speed region.

Further, the values obtained for a plurality of sampling periods τ are stored by using a predetermined data storage area of the CPU, and the values are not cleared for each sampling period τ based on the count value. By calculating the velocity for a period that is an integral multiple of the sampling period τ, it is possible to improve the calculation accuracy of velocity and acceleration / deceleration.

[0031]

[Effect of device]

 As described above, according to the invention of claim 1, even when the rising (or the falling) of the speed pulse does not appear more than once within the sampling period, the speed and the acceleration / deceleration are detected. Therefore, even if the sampling period for speed detection is shortened in order to detect the speed in a short time, it is possible to detect the speed and the acceleration / deceleration even in the low speed range. .

According to the second aspect of the invention, in addition to the effect of the first aspect of the invention, based on the count value whose value is not cleared for each sampling period, the speed is increased for an integral multiple of the sampling period. Since it is calculated and the calculation accuracy of the velocity and acceleration / deceleration is improved, the effect that the velocity, acceleration / deceleration can be detected with high accuracy can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a detection circuit of a speed detection device according to an embodiment of the present invention.

FIG. 2 is a timing chart of each signal in the same circuit.

FIG. 3 is a diagram showing a velocity pulse count value sampled in the same circuit and a clock count value of a velocity pulse count period.

FIG. 4 is a block diagram showing a configuration of a detection circuit of a speed detection device according to a conventional example.

FIG. 5 is a timing chart of each signal in the same circuit.

FIG. 6 is a diagram showing velocity pulses counted in each sampling period in the same circuit.

FIG. 7 is a diagram showing velocity pulses counted when the sampling period is shortened in the same circuit.

[Explanation of symbols]

 1 waveform shaping circuit 2, 12 counter circuit 3, 13 latch circuit 4 reference clock generation circuit 11 D flip-flop 14 AND gate

Claims (2)

[Scope of utility model registration request] 1. A detection device for detecting the speed and acceleration / deceleration of the transportation device based on the speed pulse output from a velocity generator in accordance with the rotation of the wheels of the transportation device, wherein the number of output pulses of the velocity pulse is A counting means for counting the number of clocks of a predetermined clock pulse, a first holding means for holding the count value of the counting means for each predetermined sampling period, and for each cycle of the speed pulse Second holding means for holding the count value of the timekeeping means, and a difference between the count values at the start time point and the end time point of the sampling period held by the first holding means, and the result is sampled. A first subtracting means for outputting as a velocity pulse count value in the period, and a total of the start time point and the end time point of the sampling period held by the second holding means. Second subtraction means for calculating a difference between the numerical values and outputting the result as a time count value of a period corresponding to the speed pulse count value, and traveling of the transportation device based on the speed pulse count value and the time count value. First calculating means for calculating speed, and second calculating means for calculating acceleration or deceleration of the transportation device based on traveling speeds in two adjacent sampling periods calculated by the first calculating device. A speed detecting device comprising: 2. The speed detection device according to claim 1, further comprising a storage unit that takes in the values held in the first and second holding units for each sampling period and stores the values. And the second subtraction means calculates a difference between the count values for a predetermined calculation period that is an integral multiple of the sampling period, and the first calculation means calculates the difference based on the calculation results of the first and second subtraction means. Calculating a traveling speed in the calculation period, and the second calculating means calculating the acceleration or deceleration based on the traveling speed in the two adjacent calculation periods calculated by the first calculation device. A speed detection device characterized by.