JPH0787550B2 - Solid-state image sensor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a solid-state image sensor.

[Outline of Invention]

According to the present invention, in the solid-state image pickup device, the number of light-receiving elements is arranged in the number required to obtain a high-quality image pickup signal, and the supply of the clock signal to the vertical shift register is controlled, so that The image pickup signal of the high-quality system and the normal system can be obtained.

[Conventional technology]

In addition to the normal system (NTSC system, PAL system, etc.), in recent years, a high-quality system has been proposed in which the number of scanning lines is approximately twice that of the current system. The solid-state image pickup device for obtaining a high-quality image pickup signal has a different number of scanning lines, and thus is configured separately from the solid-state image pickup device for obtaining a normal-type image pickup signal.

[Problems to be solved by the invention]

However, when a high-quality system is adopted in the future, inconsistencies of combined use will occur in each system of input, transmission, and output at the time of switching from the current system.

In view of the above problems, the present invention makes it possible to obtain high-quality and normal-type image pickup signals from a single solid-state image pickup element, for example, to eliminate the need for switching the television camera at the time of the above-described switching. Is.

[Means for solving problems]

The present invention corresponds to a plurality of light receiving elements (1) arranged in a matrix and a plurality of light receiving elements (1) respectively.
A vertical shift register (2) having a number of electrodes arranged to transfer charges in a vertical direction, and a transfer gate (3) controlling transfer of charges generated by a plurality of light receiving elements (1) to the vertical shift register (2). , A horizontal shift register (4) for transferring charges in the horizontal direction. Then, for each electrode of the vertical shift register (2) (Va, Va ', Vb, v
b ′, ……) Clock signals φ _{1 to} φ whose phases are sequentially different
₄ is supplied to obtain a high-quality image pickup signal, and two electrodes (VaVa ′, VbVb ′,
VcVc ′, ...) Clock signal φ ₁ with sequentially different phases
~ Φ ₄ is supplied to obtain a normal type image pickup signal.

[Action]

When the clock signals φ _{1 to} φ ₄ whose phases are sequentially different for every two electrodes of the vertical shift register (2) are supplied, the clock signals φ ₁ to φ ₁ whose phases are sequentially different for each electrode of the vertical shift register (2) are supplied. Compared to when φ ₄ is supplied, a signal of 1/2 the scanning line is obtained. Therefore, when the number of light receiving elements is set to the number necessary to obtain a high-quality imaging signal,
By controlling the supply of the clock signals φ ₁ to φ ₄ to the vertical shift register (2) as described above, high-quality and normal-type image pickup signals can be obtained from one solid-state image pickup device.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. In this example, a high-quality image pickup signal having a horizontal frequency of 33.75 kHz and an NTSC image pickup signal having a horizontal frequency of 15.75 kHz are obtained.

In FIG. 1, (10) shows the whole CCD solid-state imaging device, and (1) is a light receiving device (photoelectric conversion device) arranged in a matrix corresponding to each pixel. Also, (2)
Is a vertical shift register arranged in rows, and two electrodes are formed for each light receiving element (1) in this vertical shift register (2) and driven by a four-phase method. For example, for the light receiving elements Sa, Sb, Sc, Sd and Se, electrodes (Va, Va '), (Vb, Vb'), (Vc, Vc '), (Vd,
Vd ') and (Ve, Ve') are formed. Further, between the light receiving element (1) and the vertical shift register (2), the charges accumulated in the light receiving element (1) are charged to the vertical shift register (2).
A transfer gate (3) for controlling transfer is arranged in the. For example, for the light receiving elements Sa, Sb, Sc, Sd and Se, the transfer gate G
a, Gb, Gc, Gd and Ge are arranged. In FIG. 1, only five light receiving elements (1) are arranged in the vertical direction for simplification of the drawing.
Individually distributed. The array in this case is, for example, Sa, Sb, Sc, Sd, S
It is arranged like e, Sb, Sc, Sd, Sa, Sb, Sc, Sd, ....

Further, (4) is a horizontal shift register, which is arranged electrically coupled to the vertical shift register (2). A charge detection unit (5) is provided at one end of the horizontal shift register (4).
Are arranged, and an image pickup signal is output from the outside.

Further, (6) is a clock signal generating circuit, from which a clock signal φ _{1 having} a phase relationship as shown in FIGS.
~ Φ ₄ is generated. The clock signal φ ₁ is supplied to the electrodes Va and Ve of the vertical shift register (2) as well as to the A side terminal of the switch circuit (21) and the B side terminal of the switch circuit (24), and the clock signal φ ₁ is supplied. The signal φ ₂ is supplied to the B-side terminals of the switch circuits (21) and (25) as well as to the A-side terminals of the switch circuits (22) and (23), and the clock signal φ ₃ is supplied to the switch circuit ( 22) and (26) are supplied to the B side terminals and are also supplied to the A side terminals of the switch circuits (24) and (25), and the clock signal φ ₄ is supplied to the electrode Vd ′ of the vertical shift register (2). It is also supplied to the B side terminal of the switch circuit (23) and the A side terminal of the switch circuit (26). The output of the switch circuit (21) is supplied to the electrodes Va ′ and Ve ′ of the vertical shift register (2), and the switch circuits (22) to (2
The output of 6) is supplied to the electrodes Vb to Vd of the vertical shift register (2), respectively.

In this case, the switch circuits (21) to (26) are connected to the B side when obtaining a high-quality system signal, and are connected to the A side when obtaining an NTSC system signal.

Further, the frequencies of the clock signals φ _{1 to} φ ₄ are set to 33.75 kHz when a high-quality system signal is obtained, and are set to 15.75 kHz when an NTSC system signal is obtained. 3A to 3D show clock signals φ _{1 to} φ ₄ . In this case, the high level gate pulse PG is superimposed on the clock signals φ ₁ and φ ₃ every 1/30 seconds.

Further, clock signals φ _1H and φ _2H are supplied from the clock signal generation circuit (6) to the horizontal shift register (4),
The horizontal shift register (4) is driven by, for example, a two-phase method.

In the above configuration, when a high quality signal is obtained, the clock signal generating circuit (6) generates the clock signals φ _{1 to} φ ₄ having a frequency of 33.75 kHz. Further, since the switch circuits (21) to (26) are connected to the B side, the clock signal φ ₁ is applied to the electrodes Va, Vc and Ve of the vertical shift register (2).
, The clock signal φ ₂ is supplied to the electrodes Va ′, Vc ′ and Ve ′ of the vertical shift register (2), the clock signal φ ₃ is supplied to the electrodes Vb and Vd of the vertical shift register (2), and The clock signal φ ₄ is supplied to the electrodes Vb ′ and Vd ′ of the vertical shift register (2). for that reason,
For example, at the beginning of an odd field in which the gate pulse PG is superimposed on the clock signal φ ₁ , the signal charges accumulated in the light receiving elements Sa, Sc and Se are transferred to the vertical shift register (2) via the transfer gates Ga, Gc and Ge. Are transferred to the portions corresponding to the electrodes Va, Vc, and Ve of. Then, after that, one vertical scanning line is transferred to the horizontal shift register (4) by one scanning line. 4A to 4F show the transfer positions of the signal charges at the time points t _{1 to} t ₆ of the clock signals φ _{1 to} φ ₄ shown in FIGS. 2A to 2D, which are also clear from this figure. In this way, the potential wells are sequentially moved and accumulated in the light receiving elements Sa, Sc and Se, and the vertical shift register (2)
The signal charges (indicated by) that have been transferred to the portions corresponding to the electrodes Va, Vc, and Ve of are transferred in the vertical direction. Further, for example, at the beginning of an even field in which the gate pulse PG is superimposed on the clock signal φ ₃ , the signal charges accumulated in the light receiving elements Sb and Sd are transferred to the electrodes of the vertical shift register (2) via the transfer gates Gb and Gd. It is transferred to the part corresponding to Vb and Vd. Then, as in the case of the odd field described above,
One scanning line is transferred to the horizontal shift register (4) by the vertical shift register (2).

Further, the signal charges transferred to the horizontal shift register (4) for each scanning line are sequentially supplied to the charge detection unit (5) within one horizontal period (1H), and the charge detection unit (5) horizontally transfers the charges to the outside. High-quality imaging signals with a frequency of 33.75 kHz are output.

Further, when obtaining a signal of the NTSC system, the clock signal generating circuit (6) than the frequency of 15.75kHz clock signal phi ₁
~ Φ ₄ is generated. In addition, switch circuits (21) to (2
6) is connected to the A side, the clock signal φ ₁ is supplied to the electrodes Va, Va ′, Ve and Ve ′ of the vertical shift register (2), and the clock signal φ ₂ is the electrode of the vertical shift register (2). The clock signal φ ₃ is supplied to Vb and Vb ′, and the clock signal φ ₃ is supplied to the electrodes Vc and Vc ′ of the vertical shift register (2), and the clock signal φ ₄ is supplied to the electrode Vd of the vertical shift register (2).
And Vd ′. Therefore, for example, the signal charges accumulated in the light receiving elements Sa and Se at the beginning of the odd field in which the gate pulse PG is superimposed on the clock signal φ ₁ are transferred via the transfer gates Ga and Ge to the electrode Va of the vertical shift register (2). And Ve are transferred to the corresponding part. Then, after that, one vertical scanning line is transferred to the horizontal shift register (4) by one scanning line. 5A to 5F show time points t _{1 to} t _{6 of the} clock signals φ _{1 to} φ ₄ shown in FIGS. 2A to 2D.
The transfer position of the signal charge in FIG. 3 is shown, and as is clear from this figure, wells of potential are sequentially moved to be accumulated in the light receiving elements Sa and Se, and the electrode Va of the vertical shift register (2) is , And signal charges transferred to the portions corresponding to Ve (indicated by) are transferred in the vertical direction. In this case, the transfer distance in one horizontal period is twice that in the case of the above-described high-quality system. Further, for example, the signal charge accumulated in the light receiving element Sc at the beginning of the even field in which the gate pulse PG is superimposed on the clock signal φ ₃ is the portion corresponding to the electrode Vc of the vertical shift register (2) via the transfer gate Gc. Transferred to. Then, as in the case of the odd-numbered field described above, the data is transferred by the vertical shift register (2) to the horizontal shift register (4) one scan line at a time.

Further, the signal charges transferred to the horizontal shift register (4) for each scanning line are sequentially supplied to the charge detection unit (5) within the horizontal period, and the horizontal frequency is 15.75 kHz from the charge detection unit (5) to the outside. The image signal of the NTSC system is output.

Thus, according to this example, one CCD solid-state image sensor (1
0) It is possible to obtain higher-quality image pickup signals and NTSC image pickup signals. Therefore, according to this example, it is possible to eliminate the need to switch the television camera when switching from the current normal system to the high-definition system, and to improve the efficiency of switching.

According to the above-mentioned embodiment, the NTSC system is shown as the normal system, but other systems can be constructed in the same manner. The horizontal frequency of the high-quality image pickup signal described above is an example, and the present invention is not limited to this.

〔The invention's effect〕

According to the present invention described above, it is possible to obtain high-definition type and normal type (NTSC type, PAL type, etc.) image pickup signals from a single CCD solid-state image pickup element, for example, switching from the normal type to the high-quality type. At times, it is not necessary to switch the TV camera, and the switching efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS.
The figure is a figure for the explanation. (1) is a light receiving element, (2) is a vertical shift register,
(3) is a transfer gate, (4) is a horizontal shift register,
(6) is a clock signal generation circuit, (10) is a CCD solid-state image pickup device, and (21) to (26) are switch circuits.

Claims (1)

[Claims] 1. A plurality of light-receiving elements arranged in a matrix, and a vertical shift register in which two electrodes are arranged corresponding to the plurality of light-receiving elements to transfer charges in a vertical direction.
A transfer gate for controlling transfer of charges generated by the plurality of light-receiving elements to the vertical shift register and a horizontal shift register for transferring charges in the horizontal direction are provided, and the phases of the electrodes of the vertical shift register are sequentially changed. To obtain a high-quality image pickup signal, and to supply a clock signal having a normal phase for every two electrodes of the vertical shift register to obtain a normal image pickup signal. Characteristic solid-state image sensor.