JPH0787149B2 - Multilayer chip impedance element - Google Patents
Multilayer chip impedance elementInfo
- Publication number
- JPH0787149B2 JPH0787149B2 JP2310066A JP31006690A JPH0787149B2 JP H0787149 B2 JPH0787149 B2 JP H0787149B2 JP 2310066 A JP2310066 A JP 2310066A JP 31006690 A JP31006690 A JP 31006690A JP H0787149 B2 JPH0787149 B2 JP H0787149B2
- Authority
- JP
- Japan
- Prior art keywords
- impedance element
- chip impedance
- component
- coil
- main component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Manufacturing Cores, Coils, And Magnets (AREA)
- Coils Or Transformers For Communication (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、ノイズ対策に用いられる積層チップインピー
ダンス素子に関する。The present invention relates to a laminated chip impedance element used for noise suppression.
［従来の技術］ 近年、電子機器から生ずるノイズを他の電子機器に伝達
しないように、又他の電子機器から発するノイズの影響
を受けないようにする為、磁性体の内部に導体を構成し
たノイズ対策電子部品を、前記電子機器の信号線に接続
してノイズ除去を行っている。このような電子部品の一
つに積層チップインピーダンス素子がある。[Prior Art] In recent years, in order to prevent noise generated from an electronic device from being transmitted to another electronic device and from being influenced by noise generated from another electronic device, a conductor is formed inside a magnetic body. Noise suppression electronic components are connected to the signal lines of the electronic device to remove noise. One of such electronic components is a multilayer chip impedance element.
積層チップインピーダンス素子の製造方法は、まずNi・
Zn系磁性フェライト原料粉末と有機バインダとを混合し
て、フェライト・スラリーを形成し、該スラリーをドク
ターブレード法やリバースコート法等の方法によって、
厚さ数百μｍ〜数十μｍの長尺なフェライトグリーンシ
ートを成形する。前記フェライトグリーンシートを、例
えば10cm角の大きさに裁断し、所定の位置に、0.2mm程
度の貫通孔を複数形成する。該グリーンシート上にAg・
Pd等の導電ペーストを用いてスクリーン印刷法により、
コイル状の導体となるパターンを形成する。コイル状の
導体となるパターンは数種類から成り、例えば0.3mm程
度の線幅を有する導体を、それぞれ異なる向きに配置し
た略コの字状をなし、それらの一部が前記貫通孔と接し
て印刷される。それらのシートを所定の順序で所定枚数
積み重ねると前記貫通孔を介して隣接するシート上の導
体が接続されてコイルが形成される。このようにしてラ
ミネートされた積層体は、個々のコイルの端末が露出す
る位置で細断しチップ片を構成する。The manufacturing method of the multilayer chip impedance element is as follows.
Zn-based magnetic ferrite raw material powder and an organic binder are mixed to form a ferrite slurry, and the slurry is prepared by a method such as a doctor blade method or a reverse coating method.
A long ferrite green sheet having a thickness of several hundred μm to several tens μm is formed. The ferrite green sheet is cut into a size of 10 cm square, for example, and a plurality of through holes of about 0.2 mm are formed at predetermined positions. Ag on the green sheet
By screen printing using conductive paste such as Pd,
A pattern serving as a coiled conductor is formed. There are several types of patterns that are coil-shaped conductors, for example, conductors having a line width of about 0.3 mm are arranged in different directions to form a substantially U shape, and some of them are printed in contact with the through holes. To be done. When a predetermined number of these sheets are stacked in a predetermined order, the conductors on the adjacent sheets are connected through the through holes to form a coil. The laminated body thus laminated is cut into small pieces at the positions where the ends of the individual coils are exposed to form chip pieces.
これを1000〜1200℃の温度で焼成した後、前記チップ片
の端面に導出したコイル端末と接続するように、チップ
片の端面にAg等の導電性ペーストを塗布し、焼き付けて
外部電極を構成する。また、特開平１−1107085に示さ
れるように、Ni系フェライトにホウケイ酸ガラスを添加
することにより低温で焼結が可能なチップインダクタも
提案されている。After baking this at a temperature of 1000 to 1200 ° C, a conductive paste such as Ag is applied to the end surface of the chip piece so as to be connected to the coil end led to the end surface of the chip piece, and baked to form an external electrode. To do. Further, as disclosed in Japanese Patent Application Laid-Open No. 1-1107805, a chip inductor has been proposed which can be sintered at low temperature by adding borosilicate glass to Ni-based ferrite.
［発明が解決しようとする課題］ 従来の積層チップインピーダンス素子は、インピーダン
ス素子に流せる許容電流値が低く、信号電流の大きい機
器には使用出来ないと言う課題があった。[Problems to be Solved by the Invention] The conventional multilayer chip impedance element has a problem in that it has a low allowable current value that can be passed through the impedance element and cannot be used in a device having a large signal current.
本発明の目的は、許容電流値の大きい積層チップインピ
ーダンス素子を提供する事にある。An object of the present invention is to provide a laminated chip impedance element having a large allowable current value.
［課題を解決するための手段］ 課題を解決するための手段の要旨は、Fe2O3、ZnO、Ni
O、CuOを主成分とする第１成分と、Bi2O3、V2O5、珪酸
鉛ガラスから選択された少なくとも一種以上を主成分と
する第２成分とから成るフェライト磁性体片に、Agを主
成分とする導電体をコイル状に埋設し、前記磁性体片端
面に形成された端子電極に、前記コイル端末を接続させ
た積層チップインピーダンス素子である。[Means for Solving Problems] The outline of means for solving problems is Fe 2 O 3 , ZnO, and Ni.
A ferrite magnetic piece consisting of a first component containing O and CuO as a main component and a second component containing at least one selected from Bi 2 O 3 , V 2 O 5 and lead silicate glass as a main component, A laminated chip impedance element in which a conductor containing Ag as a main component is embedded in a coil shape, and the coil terminal is connected to a terminal electrode formed on one end face of the magnetic body.
［作 用］ Fe2O3、ZnO、NiO、CuOを主成分とする第１成分と、Bi2O
3、V2O5、珪酸鉛ガラスから選択された少なくとも一種
を主成分とする第２成分とから成るフェライト磁性体片
に、Agを主成分とする導電体をコイル状に埋設し、前記
磁性体片端面に形成された端子電極に、前記コイル端末
を接続させたので、許容電流値を大きくする事が可能に
なった。[Working] Fe 2 O 3 , ZnO, NiO, CuO as the main component, and Bi 2 O
3 , a conductor containing Ag as a main component is embedded in a coil shape in a ferrite magnetic piece consisting of V 2 O 5 , and a second component containing at least one selected from lead silicate glass as a main component, Since the coil terminal is connected to the terminal electrode formed on the end face of one body, it is possible to increase the allowable current value.
以下、実施例により本発明を詳しく説明する。しかし本
発明の範囲は以下の実施例によって制限されるものでは
ない。Hereinafter, the present invention will be described in detail with reference to examples. However, the scope of the present invention is not limited by the following examples.
［実施例−１］ 本発明の積層チップインピーダンス素子とその製造方法
の一例を第１図ａ、ａ′、ｂ、ｃ、ｄを用いて説明す
る。[Example-1] An example of the multilayer chip impedance element of the present invention and a method for manufacturing the same will be described with reference to Figs.
Fe2O3 48mol％、ZnO 30mol％、NiO 10mol％、CuO 1
2mol％の原料粉末を秤量した第１成分と、その総量の3w
t％に相当する量のBi2O3を秤量した第２成分とを混合
し、750℃の温度で１時間仮焼する。その後、前記混合
物をボールミルによって粉砕し、平均粒径1.2μｍのフ
ェライト磁性粉を得た。Fe 2 O 3 48mol%, ZnO 30mol%, NiO 10mol%, CuO 1
The first component weighed 2 mol% of raw material powder and 3w of the total amount
A second component in which an amount of Bi 2 O 3 corresponding to t% is weighed is mixed and calcined at a temperature of 750 ° C. for 1 hour. Then, the mixture was ground by a ball mill to obtain ferrite magnetic powder having an average particle size of 1.2 μm.
該磁性粉5kgと、ポリビニールブチラールを500gを含
み、トルエン・エタノール混合溶剤からなる有機バイン
ダ4000kgとを混合してフェライト磁性体のスラリーを構
成する。5 kg of the magnetic powder and 4000 kg of an organic binder containing 500 g of polyvinyl butyral and a toluene / ethanol mixed solvent are mixed to form a slurry of a ferrite magnetic material.
該スラリーをポリエチレンテレフタレートの長尺なベー
スフィルム上に、ドクターブレード法に従って、厚さ20
0μｍの長尺なフェライト・グリーンシートを形成す
る。The slurry was applied on a long base film of polyethylene terephthalate to a thickness of 20 according to the doctor blade method.
A long ferrite green sheet of 0 μm is formed.
前記フェライト・グリーンシートをベースフィルムから
剥離して、100mm角の大きさに切断して、シートを複数
枚用意する。The ferrite green sheet is peeled from the base film and cut into 100 mm square pieces to prepare a plurality of sheets.
これらのシートの枚数の所定数を残して他のシートは、
予め定められた位置に0.3mmの貫通孔を複数策孔した。Other sheets, leaving a certain number of these sheets,
Plural 0.3 mm through holes were drilled at predetermined positions.
貫通孔が形成されたシートは等分に分け、それぞれのシ
ートに第１図右側のＩ、Ｆ、Ｅ、Ｈ、Ｇ、にパターン一
個分を示したが、これらのパターンが前記シートに複数
個、等間隔に配置されたスクリーンパターンを用いて、
Ag導電性ペーストを印刷し、貫通孔が形成されなかった
シートの枚数の所定枚数にパターンＪを印刷した。The sheet in which the through-holes are formed is divided into equal parts, and each sheet shows one pattern for I, F, E, H, and G on the right side of FIG. 1, but these patterns are plural in the sheet. , Using screen patterns that are evenly spaced,
The Ag conductive paste was printed, and the pattern J was printed on a predetermined number of sheets in which the through holes were not formed.
これらのシートを第１図ａに従って積み重ね、加圧した
後、前記コイルが磁性体に内設される状態で、前記コイ
ルの端末が両端に露出する位置で第１図ｂのように裁断
し、第１図ｃのようなチップ片を得た。これを大気中に
於いて900℃の温度で２時間焼成した。焼成されたチッ
プ片のコイル端末が導出している両端に、Ag導電ペース
トを塗布し、750℃の温度で焼き付けて、第１図ｄのよ
うな積層チップインピーダンス素子を構成した。After stacking these sheets according to FIG. 1a and applying pressure, the coil is cut inside as shown in FIG. 1b at the positions where the ends of the coil are exposed at both ends in a state where the coil is provided inside the magnetic body, A chip piece as shown in FIG. 1c was obtained. This was baked in the air at a temperature of 900 ° C. for 2 hours. Ag conductive paste was applied to both ends of the fired chip piece from which the coil ends were led out and baked at a temperature of 750 ° C. to form a laminated chip impedance element as shown in FIG. 1d.
その後、前記Ag端子電極にNiメッキ、半田メッキを施
し、端子電極の半田濡れ性を改善して半田付け性の良い
積層チップインピーダンス素子を得た。これらのチップ
インピーダンス素子を、25℃の恒温槽内に於いて、それ
ぞれ異なる定電流を流して、チップの温度上昇を観測し
た結果、電流量によって安定する温度が異なる事が知ら
れ、安定した温度が85℃となる電流量をもって、許容電
流とした。After that, the Ag terminal electrode was plated with Ni and solder to improve the solder wettability of the terminal electrode to obtain a laminated chip impedance element having good solderability. As a result of observing the temperature rise of the chips by applying different constant currents to each of these chip impedance elements in a constant temperature bath at 25 ° C, it is known that the stable temperature differs depending on the amount of current. The allowable current was defined as the amount of current that reached 85 ° C.
本実施例のチップインピーダンス素子50個の平均許容電
流値は415mAであった。The average permissible current value of the 50 chip impedance elements of this example was 415 mA.
［実施例−２］ 実施例−１の第２成分であるBi2O3に代えて、V2O5とし
た事以外は実施例−１と同様に行った結果、平均許容電
流値は401mAであった。Example -2 results in place of the Bi 2 O 3 as the second component of Example -1, except that was V 2 O 5 was conducted in the same manner as in Example 1, the average allowable current value 401mA Met.
［実施例−３］ 実施例−１の第２成分であるBi2O3に代えて、SiO2−PbO
を主成分とするガラスとした事以外は実施例−１と同様
に行った結果、平均許容電流値は394mAであった。Example -3] in place of the Bi 2 O 3 as the second component of Example -1, SiO 2 -PbO
As a result of carrying out in the same manner as in Example 1 except that the glass containing as a main component was used, the average permissible current value was 394 mA.
［比較例］ 実施例−１に於いてBi2O3等の第２成分を除去した事
と、Agに代えて、Ag・Pdペーストを用いた事と、焼成温
度を900℃に代えて、1150℃とした事以外は、実施例−
１と同様に行った結果、平均許容電流値は230mAであっ
た。Comparative Example In Example 1, the second component such as Bi 2 O 3 was removed, Ag / Pd paste was used in place of Ag, and the firing temperature was changed to 900 ° C. Example except that the temperature was set to ° C.
As a result of carrying out similarly to 1, the average permissible current value was 230 mA.
以上実施例に於いて、第２成分の添加例を示したがこれ
に限るものではない。The examples of adding the second component have been described in the above examples, but the present invention is not limited to this.
「効果」 本発明によれば、ノイズ対策部品として積層チップイン
ピーダンス素子の許容電流を大きくする事が出来、従
来、信号電流によって使用が限定されていた分野に於い
ても、積層チップインピーダンス素子の使用を可能にし
た効果は大きい。[Effect] According to the present invention, the allowable current of the laminated chip impedance element can be increased as a noise countermeasure component, and the laminated chip impedance element can be used even in the field where the use is conventionally limited by the signal current. The effect that made it possible is great.
第１図は、本発明の積層チップインピーダンス素子の製
造方法を（ａ）〜（ｄ）の段階で示した斜視図である。 （ａ）は積層チップインピーダンス素子のフェライトグ
リーンシートの積層状態の分解図である。 （ｂ）は、フェライトグリーンシートを圧着した積層体
を細分する切断線を模式的に示した図である。 （ｃ）は、フェライト積層体から細断されたチップ片を
示す図である。 （ｄ）は、焼成チップ片の両端に外部電極を形成した積
層チップインピーダンス素子を示す図である。 符号の説明 １……グリーンシート ２……スルホール ３……コイル導体 ４……積層体 ５……チップ片 ６……外部電極FIG. 1 is a perspective view showing a method of manufacturing a layered chip impedance element of the present invention in steps (a) to (d). (A) is an exploded view of a laminated state of a ferrite green sheet of a laminated chip impedance element. (B) is the figure which showed typically the cutting line which divides the laminated body which pressure bonded the ferrite green sheet. (C) is a figure which shows the chip piece chopped from the ferrite laminated body. (D) is a diagram showing a multilayer chip impedance element in which external electrodes are formed on both ends of a fired chip piece. Explanation of symbols 1 …… Green sheet 2 …… Through hole 3 …… Coil conductor 4 …… Layered body 5 …… Chip piece 6 …… External electrode
Claims (1)
成分と、Bi2O3、V2O5、珪酸鉛ガラスから選択された少
なくとも一種以上を主成分とする第２成分とから成るフ
ェライト磁性体片に、Agを主成分とする導電体をコイル
状に埋設し、前記磁性体片端面に形成された端子電極
に、前記コイル端末を接続させた積層チップインピーダ
ンス素子。1. A first composition containing Fe 2 O 3 , ZnO, NiO, CuO as a main component.
Coil with a conductor containing Ag as a main component in a ferrite magnetic piece consisting of a component and a second component containing at least one selected from Bi 2 O 3 , V 2 O 5 and lead silicate glass as a main component. A multilayer chip impedance element in which the coil terminal is connected to a terminal electrode formed in one end face of the magnetic body, which is embedded in a shape of a circle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2310066A JPH0787149B2 (en) | 1990-11-15 | 1990-11-15 | Multilayer chip impedance element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2310066A JPH0787149B2 (en) | 1990-11-15 | 1990-11-15 | Multilayer chip impedance element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04180610A JPH04180610A (en) | 1992-06-26 |
| JPH0787149B2 true JPH0787149B2 (en) | 1995-09-20 |
Family
ID=18000759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2310066A Expired - Fee Related JPH0787149B2 (en) | 1990-11-15 | 1990-11-15 | Multilayer chip impedance element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0787149B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101503104B1 (en) * | 2011-08-01 | 2015-03-16 | 삼성전기주식회사 | Ferrite powder of metal, ferrite material comprising the same, and multilayered chip materials comprising ferrite layer using the ferrite material |
| CN108706968B (en) * | 2018-06-05 | 2021-04-30 | 电子科技大学 | Low-temperature sintered direct-current bias resistant NiCuZn ferrite and preparation method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50107008A (en) * | 1974-01-30 | 1975-08-23 | ||
| JPS6022443B2 (en) * | 1982-04-02 | 1985-06-01 | ティーディーケイ株式会社 | insulation material |
| JPH0680613B2 (en) * | 1987-04-16 | 1994-10-12 | 日立フェライト株式会社 | High density magnetic material |
| JP2691715B2 (en) * | 1987-07-01 | 1997-12-17 | ティーディーケイ株式会社 | Ferrite sintered body, chip inductor and LC composite parts |
-
1990
- 1990-11-15 JP JP2310066A patent/JPH0787149B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04180610A (en) | 1992-06-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW422998B (en) | Inductor element and the manufacturing method of the same | |
| US8143988B2 (en) | Multilayer inductor | |
| KR20000052335A (en) | Ferrite tape composition, inductor coils, embedded inductor, and method for fabricating embedded inductor | |
| KR101050665B1 (en) | Manufacturing method of electrostatic measures parts | |
| JPH03173402A (en) | Chip varistor | |
| JP2020194807A (en) | Laminated coil component | |
| CN111986878B (en) | Laminated coil component | |
| JP7517509B2 (en) | Multilayer coil parts | |
| JPS59132604A (en) | Laminated inductor | |
| JPH0787149B2 (en) | Multilayer chip impedance element | |
| KR101408525B1 (en) | Multilayered coil elements | |
| JPH09260144A (en) | Coil component and its manufacture | |
| JPH0214501A (en) | Voltage nonlinear resistor | |
| JP3275466B2 (en) | Multilayer chip components | |
| JPH0757935A (en) | Multilayer chip inductor | |
| JPH05205944A (en) | Laminated inductor and laminated ceramic component | |
| CN218826459U (en) | Electronic component and coil component | |
| JP3948269B2 (en) | Coil parts manufacturing method | |
| CN113539592B (en) | Chip varistor and manufacturing method thereof | |
| US20220277890A1 (en) | Multilayer coil component | |
| JPH11260647A (en) | Composite part and manufacture thereof | |
| JPH09199331A (en) | Coil component and its manufacture | |
| JPH0963845A (en) | Layered component and production thereof | |
| JPH08148338A (en) | Multilayer chip inductor and production thereof | |
| JP2003297636A (en) | Coil component |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080920 Year of fee payment: 13 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080920 Year of fee payment: 13 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090920 Year of fee payment: 14 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100920 Year of fee payment: 15 |
|
| LAPS | Cancellation because of no payment of annual fees |