JPH0786893A - Detecting circuit for clock signal abnormality - Google Patents

Abstract

PURPOSE:To provide a detecting circuit which can instantaneously detect the abnormality (break and deterioration of frequency) of the clock signals by using a simulated clock signal that has the same frequency as that of the clock signal supplied to a device. CONSTITUTION:A simulated clock signal generating circuit 1 generates a simulated clock signal C that has the same frequency as that of a clock signal A supplied to a circuit. Meanwhile a fixed pattern signal B synchronized with the signal A is generated by a pattern signal generating circuit 2. Then a comparator 3 compares the cycle time of the signal B with the reference cycle time of the signal C to detect the break and the deterioration of frequency of the signal A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal abnormality detecting circuit, and more particularly, to a clock signal which is supplied to a transmission line device when an abnormality (disconnection / frequency deterioration) is detected and the abnormality is detected. Relates to a clock signal abnormality detection circuit which outputs an abnormality detection signal.

[0002]

2. Description of the Related Art Conventionally, in a transmission line device or the like, when a clock signal supplied to the device is disconnected or frequency deterioration occurs,
The device will not work and the data to be transmitted will not be transmitted correctly. Therefore, there is provided a clock signal abnormality detection circuit that monitors the supplied clock signal and outputs an abnormality detection signal (alarm signal) to ensure the device when an abnormality occurs in the clock signal.

FIG. 6 is a block diagram showing the configuration of a conventional clock signal abnormality detection circuit. In FIG. 6, reference numeral 61 is a timer composed of a pulse generation circuit, which periodically generates a timer signal c at predetermined intervals. 62
Is a latch circuit composed of an RS flip-flop, which latches a timer signal c which is periodically generated and resets the latched signal b by a clock signal a. Reference numeral 63 is a detection circuit composed of a D flip-flop, which detects an abnormality of the clock signal a by latching the latch signal b in synchronization with the timer signal c and outputs an alarm signal d.

7 and 8 are time charts (No. 1 and No. 2) of the conventional clock signal abnormality detection circuit.
7. FIG. 7 is a time chart (No. 1) when detecting the disconnection of the clock signal a. Further, FIG. 8 is a time chart (No. 2) when detecting the frequency deterioration of the clock signal a. Explaining the time chart (part 1) of FIG. 7, for example, the latch circuit 62 includes the timer 61.
It latches at the rising edge of the timer signal c generated from the above and outputs the latch signal b. At this time, when the clock signal a is supplied, the clock signal a rises,
Alternatively, the latch signal b is reset at the falling edge. Here, when the clock signal a is disconnected and the next timer signal c is input from the timer 61, the latch signal b is not reset and maintains the “High” state. next,
The detection circuit 63 further receives “high” with the next timer signal c.
By latching the latch signal b in the state of h ″, the disconnection of the clock signal a is detected and the alarm signal d is output.

[0005]

However, as shown in the time chart (No. 1) of FIG. 7, even if the disconnection of the clock signal a can be detected, it cannot be immediately detected by the cycle of the timer signal c. The operation in the apparatus could not be guaranteed until the alarm signal was detected after the disconnection of the signal a. Further, in the time chart (part 2) of FIG. 8, the frequency of the clock signal a is deteriorated and the cycle time of the clock signal a is extended, but since it is shorter than the cycle time of the timer signal c, the latch signal b is the clock signal a. As a result, the alarm signal d is not output from the detection circuit 63 because it is always reset and maintained at "Low". Therefore, when the clock signal a is deteriorated, there is a problem that the abnormality cannot be detected.

In other words, if the clock signal is monitored periodically, the operation between cycles cannot be guaranteed when the clock signal is interrupted during the cycle, and even if the frequency of the clock signal deteriorates during the cycle. If there is a change in the state of the clock signal (change in High / Low) during the period, the clock signal is regarded as normal, so that an abnormality in the clock signal cannot be detected and an abnormal operation occurs in the device. Therefore,
There has been a long-felt demand for a method of immediately detecting a break or deterioration of a clock signal.

The present invention has been made in consideration of the above circumstances, and provides, for example, a clock signal abnormality detection circuit capable of immediately detecting the disconnection of a clock signal and the detection of frequency deterioration with the same circuit.

[0008]

The technical means taken by the present invention to achieve the above object are as follows.
FIG. 1 is a block diagram showing the basic circuit configuration of the present invention.
In FIG. 1, the present invention generates a simulated clock signal generation circuit 1 for generating a simulated clock signal C having the same frequency as the clock signal A supplied to the circuit, and a fixed pattern signal B synchronized with the clock signal A. A pattern signal generation circuit 2 and a comparison circuit 3 for comparing the cycle time of the fixed pattern signal B with the cycle time of the simulated clock signal C as a reference are provided, and the comparison circuit 3 detects an abnormality in the cycle time of the fixed pattern signal B. It is a clock signal abnormality detection circuit characterized by detecting disconnection of the clock signal A and deterioration of frequency by comparing with the simulated clock signal C.

It is preferable that the fixed pattern generation circuit 2 is provided with a binary counter and is configured to divide the clock signal A into 1/2 and generate a fixed pattern signal B synchronized with the clock signal A.

The comparison circuit 3 is preferably configured to output an abnormality detection signal D when detecting an abnormality in the fixed pattern signal B in the cycle time.

In the present invention, as the simulated clock signal generation circuit 1, a pulse generator or a clock signal generation module having the same circuit configuration as that for generating a clock signal is used. As the pattern signal generation circuit 2, a binary counter composed of flip-flops is used. The comparison circuit 3 includes a counter, a decoder,
A circuit composed of a comparator or the like is used. Further, the simulated clock signal generation circuit 1, the pattern signal generation circuit 2, and the comparison circuit 3 are provided on one substrate by TTL or CM.
It can be implemented as an LSI as an OS gate array. Further, it may be composed of a microcomputer including a CPU, a ROM, a RAM, and an I / O port.

[0012]

According to the present invention, the simulated clock signal generating circuit 1 generates the simulated clock signal C having the same frequency as the clock signal A supplied to the circuit, and the fixed pattern signal B synchronized with the clock signal A is used as the pattern signal. The generation of the generation circuit 2 and the comparison circuit 3 comparing the cycle time of the fixed pattern signal B with the cycle time of the simulated clock signal C as a reference enables detection of the interruption of the clock signal A and the deterioration of the frequency.

Since the fixed pattern generation circuit 2 has a binary counter, it can generate a fixed pattern signal B synchronized with the clock signal A by dividing the clock signal A by 1/2.

The comparator circuit 3 can output an abnormality detection signal D when it detects an abnormality in the cycle time of the fixed pattern signal B.

[0015]

The present invention will be described in detail below based on the embodiments shown in the drawings. The present invention is not limited to this. Further, the present invention is suitable for use in, for example, a transmission line device or the like, for detecting an abnormality of a clock signal supplied to the device.

FIG. 2 is a block diagram showing an embodiment of the clock signal abnormality detection circuit of the present invention. In FIG. 2, FIG.
Components having the same configurations as are indicated by the same numbers or symbols. Referring to FIG. 2, 1 is a simulated clock signal generating circuit for generating a simulated clock signal C having the same frequency as the clock signal A for detecting disconnection / frequency deterioration, and 2 is an arbitrary fixed pattern for detecting disconnection / frequency deterioration. The pattern signal generation circuit 3 for generating the signal B by the clock signal A, the simulated clock signal C of the simulated clock signal generation circuit 1 for the fixed pattern signal B generated by the pattern signal generation circuit 2.
This is a comparison circuit for comparing with.

The simulated clock signal generation circuit 1 is a pulse generator having the same circuit configuration as that for generating the clock signal A,
The simulated clock signal C is generated asynchronously to the original clock signal A by using the clock signal generation module. The pattern signal generation circuit 2 is composed of a D flip-flop, and divides the clock signal A into halves to generate a fixed pattern signal B of 0/1 alternating (High, Low). The comparison circuit 3 is composed of a counter, a decoder, a comparator, etc., and the 0/1 alternating fixed pattern signal B is compared by the comparison circuit 3 at the rise of the simulated clock signal C having the same frequency as the clock signal A. If the disconnection / frequency deterioration of A is detected, the abnormality detection signal D (alarm signal) is output.

3 and 4 are time charts (No. 1 and No. 2) of the clock signal abnormality detection circuit of the present invention. FIG. 3 is a time chart (No. 1) when detecting the disconnection of the clock signal A. FIG. 4 is a time chart (No. 2) when detecting the frequency deterioration of the clock signal A. In the time chart (part 1) of FIG. 3, the comparison circuit 3 compares the fixed pattern signal B with the rising edge of the simulated clock signal C. For example, for (B, C) input to the comparison circuit 3, (1, 1), (0,
1), (1, 1), (0, 1) ... (1, 1), (0,
If 1), the clock signal A is normal. If the clock signal A is cut off, the 0/1 alternating data is High, L
It will be fixed to somewhere of ow. That is, (B, C) is (1,
1), (0,1), ... (0,1), (0,1), or (1,1), (0,1), ... (1,1), (1,
1), two consecutive sets of (0, 1),
By detecting (0, 1) or (1, 1), (1, 1) by the comparison circuit 3, the disconnection of the clock signal A can be immediately detected.

As shown in the time chart (part 2) of FIG. 4, even when the frequency is deteriorated, the change of the 0/1 alternating fixed pattern signal B is delayed, so that it is input to the comparison circuit 3 (B, C) is (1, 1), (0, 1), ...
(0,1), (0,1), or (1,1), (0,
1), ... (1,1), (1,1), so two consecutive sets of (0,1), (0,1), or (1,
By detecting 1) and (1, 1), the frequency deterioration of the clock signal A can be immediately detected.

FIG. 5 is a block diagram showing an embodiment in which the present invention is applied to a circuit composed of dual clock signals. In FIG. 5, when detecting disconnection / frequency deterioration of the 0-system clock signal A1 and the 1-system clock signal A2, pattern signal generation circuits 21 and 22 for generating two sets of fixed pattern signals B1 and B2, and a fixed pattern signal B1. , B2 are compared with the clock signals A1 and A2, respectively.
1 and 32 constitute a flock signal abnormality detection circuit. For example, the 0 system clock signal A1 is input to the comparison circuit 32 which compares the 1 system clock signal A2, and the 1 system clock signal A2 is compared with the 0 system clock signal A1. Input to the comparator circuit 31 to detect disconnection / frequency deterioration of the respective clock signals A1 and A2. Therefore, in the case of the dual configuration of the clock signals, if the fixed pattern signal generated by the clock signal for detecting the disconnection is compared with the clock signal of one system, it is possible to immediately detect the disconnection / frequency deterioration of each clock signal. Therefore, it is not necessary to provide a simulated clock signal generation circuit.

[0021]

According to the present invention, a fixed pattern signal is generated from a clock signal, a simulated clock signal having the same frequency as the clock signal is generated, and the fixed pattern signal is monitored by the simulated clock signal. An abnormality detection circuit for immediately detecting an abnormality (disconnection and frequency deterioration) of the supplied clock signal can be obtained. Therefore, it is possible to immediately guarantee the device by the detected abnormality detection signal, so that the reliability of the device is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic circuit configuration of the present invention.

FIG. 2 is a block diagram showing an embodiment of a clock signal abnormality detection circuit of the present invention.

FIG. 3 is a time chart (No. 1) of the clock signal abnormality detection circuit of the present invention.

FIG. 4 is a time chart (No. 2) of the clock signal abnormality detection circuit of the present invention.

FIG. 5 is a block diagram showing an embodiment in which the present invention is applied to a circuit composed of dual clock signals.

FIG. 6 is a block diagram showing a configuration of a conventional clock signal abnormality detection circuit.

FIG. 7 is a time chart (No. 1) of the conventional clock signal abnormality detection circuit.

FIG. 8 is a time chart (No. 2) of the conventional clock signal abnormality detection circuit.

[Explanation of symbols]

 1 Simulated clock signal generation circuit 2 Pattern signal generation circuit 3 Comparison circuit A Clock signal B Fixed pattern signal C Simulated clock signal D Abnormality detection signal (alarm signal)

Claims (3)

[Claims] 1. A simulated clock signal generation circuit (1) for generating a simulated clock signal (C) having the same frequency as the clock signal (A) supplied to the circuit, and a fixed pattern synchronized with the clock signal (A). A pattern signal generation circuit (2) for generating a signal (B) and a fixed pattern signal (B)
And a comparison circuit (3) for comparing the cycle time of the simulated clock signal (C) with the cycle time of the simulated clock signal (C) as a reference, and the comparison circuit (3) simulates an abnormal cycle time of the fixed pattern signal (B). A clock signal abnormality detection circuit, which detects a disconnection of a clock signal (A) and deterioration of a frequency by comparing with (C). 2. The fixed pattern generation circuit (2) includes a binary counter, divides the clock signal (A) by 1/2 and generates a fixed pattern signal (B) synchronized with the clock signal (A). The clock signal abnormality detection circuit according to claim 1, wherein 3. The clock signal abnormality according to claim 1, wherein the comparator circuit (3) outputs an abnormality detection signal (D) when detecting an abnormality in the fixed pattern signal (B) in the cycle time. Detection circuit.