JPH0786866B2 - Multiprocessor equipment - Google Patents

Description

DETAILED DESCRIPTION [Overview] Regarding a processing method for accessing a register by an incorrect address from another processor in a multiprocessor system, it is necessary to write after the address of a data register to be accessed from the main processor. For the purpose of improving the processing speed by enabling data transmission, it was identified that the accessed sub-processor has an error in the address of the register to be written, sent from the main processor. Occasionally, there is no line to write data to the data register subsequent to this address in the data register and to the main processor in response to the completion of writing.

[Industrial application] The present invention relates to a processing method for accessing a register with an incorrect address from another processor in a multiprocessor system.

[Conventional technology]

Parallel processing is performed by multiple processors in order to speed up data processing, but in such parallel processing, other processors frequently access the registers in each processor. .

In particular, as the size of each processor increases, the number of registers increases, and if there is an error in the designation of the register to be written at the time of access for writing data from another processor, the whole system malfunctions.

In order to avoid such a situation, conventionally, the main processor, which is trying to access another processor, first sends out the address of the register to be written to the sub processor, and the sub processor has no error in this register address. After confirming that, the response signal is sent back to the main processor, and the main processor receives the response signal and then sends the data to be written to the sub processor.

In this specification, a processor that attempts to access another processor as described above is referred to as a “main processor”, and a processor to be accessed is referred to as a “sub-processor”. The "sub" refers only to the relationship regarding the job, and does not refer to the configuration of the processor itself or a fixed relationship defined within the multiprocessor system.

[Problems to be solved by the invention]

In the conventional technology as described above, since the data is sent from the main processor after waiting for a response from the sub processor, the waiting time is unnecessary for the main processor, and there is a drawback that the processing as a whole becomes slow. there were.

It is an object of the present invention to improve the processing speed by allowing the main processor to send out the data to be written following the address of the data register to be accessed.

[Means for solving problems]

As shown the basic configuration in FIG. 1, the sub processor 1 ₂ which is accessible from the main processor 1 _1, that there is an error in the data register 6 ₂ address to perform writing transmitted from the main processor when identified were such that refrained row the response of write end for the write process and the main processor for the data register 6 ₂ of data sent subsequent to this address.

[Action]

To write to the main processor 1 ₁ One of the sub-processor 1 _{and second} data register group 6 _2, CPU 2 ₁ from the bidirectional line 9 through by one of the sub-processor 1 of ₂ in data register group to perform writing _Sends the address of data register _62a .

The address error check circuit 4 ₂ of the sub processor 1 ₂
Error checking is performed for example by the parity check address from the main processor 1 _1, this circuit
4 ₂ by the data gate 5 ₂ sent from the bidirectional line 9 Following this address conducts when no error is detected the register 6 _21, 6 _22, designated by the address in ...... 6 _2n Write to the registered register.

However, when an error is detected in the address by the address error check circuit 4 ₂ described above, the gate 5 ₂ is shut off by the output of the address error check circuit 4 ₂ , and the main processor 1 _{1 1} blocking as writing write data transmitted via the counter circuit 9 to the data register 6 ₂ and blocked by the gate 5 ₂ is not performed.

Then, the sub processor 1 ₂ is refrained sends a response signal indicating a write completion to the main processor 1 _1.

In the main processor 1 ₁ identifies the detected that the write is not performed that the response signal from the sub processor 1 ₂ within a predetermined time by the time measurement as shown as the timer 3 ₁ does not arrive.

Even if an address error is detected in this way, if the next error-free address arrives from one of the main processors, the data register specified by this address will be followed by this address as usual. It goes without saying that the data sent is written.

〔Example〕

FIG. 2 shows a main part of an embodiment in which the present invention is applied to a direct address system in which a data register for writing is designated by a direct address.

The register address from the main processor is supplied from the address bus 10 to the decoder 22 and the parity check circuit 23 via the receiving unit 21, and the decoder 22 decodes the received address as the data register 24 ₁ , 24 ₂ ,
... AND circuit 25 ₁ , 25 ₂ , for supplying a write clock of a specified data register in 24 _n , for example, 24 ₂ .
… And circuit corresponding to the above data register 24 ₂ in 25 _n
A "1" level signal is supplied to one input terminal of 25 ₂ .

At this time, if there is no parity error in the received address, the output of the parity check circuit 23 is “0”, and the “1” level signal is output from the inverter 26 to the AND circuit 2 described above.
Since it is supplied to one input terminal of 5 ₁ , 25 ₂ , ..., 24 _n , the write clock is sent from the AND circuit 25 ₂ designated by the output of the decoder 22 to the data register 24 ₂ , The data sent from the processor via the data bus 11 is passed through the receiving unit 27 to the data register 24 ₂
Write to.

At this time, if there is a parity error in the received address, the output of the parity check circuit 23 is "1" and the inverter 26 outputs "0" to one input terminal of the AND circuits 25 ₁ , 25 ₂ , ... 25 _n. Since the level signal is supplied, all the AND circuits 25 are cut off, so that the data registers 24 ₁ , 24 ₂ , ..., 24 _n are not written.

In this embodiment, there is provided an OR circuit 28 which takes the logical sum of the outputs of all the output terminals of the decoder 22, and the "1" output of the parity check circuit 23 which occurs when the received address has a parity error. The "1" level signal from the AND circuit 29 which takes the logical product of the above is sent from the transmitting unit 30 to the main processor as an error response signal indicating an error.

In the main processor, a timer similar to that indicated by reference numeral 31 in this figure is started at the time of sending an address,
The "1" level signal output after the timer 31 times out is supplied to one input terminal, and the error response signal from the sub-processor is supplied from the receiving section 32 to the other input terminal from the AND circuit 33. The output of "1" notifies the CPU (not shown) that the address has an error.

The AND circuits 34 ₁ , 34 ₂ , ... 34 _n provided on the output side of the data registers 24 ₁ , 24 ₂ , ... 24 _n transmit the data stored in the data register 24 to the main processor. The read address from the main processor is read by the decoder 22 as in the case of writing described above.
Decoded by the specified data register eg
The data read from the AND circuit 34 ₁ provided corresponding to 24 ₁ is sent from the OR circuit 35 through the transmission unit 36 to the main processor from the data bus 11.

Even in the case of this reading, if there is a parity error in the address from the main processor, the clock is not supplied to the data register 24, and therefore reading from these data registers is not performed.

Further, the transmitting unit 37 for transmitting to the address bus 10 is provided for transmitting the address of the register for writing or reading to the sub processor when the processor 20 operates as the main processor.

FIG. 3 shows a main part of an embodiment in which the present invention is applied to an indirect address system in which a data register to be written is designated by an indirect address.

Indirect address data from the main processor is received by the receiving unit 41
Is stored in the indirect address register 42 via the, and this indirect address is sent to the decoder 43 and the parity check circuit 44.

In this decoder 43, the decoder in the embodiment of FIG.
Similarly to 22, the data register 45 ₁ , 45 ₂ , ... 45 _m to be accessed is selected by decoding, but the decoder 22 shown in FIG. 2 has its input data as a direct address.
It will be apparent that the decoding method is different because the input of the decoder 43 in this embodiment is an indirect address.

The indirect address stored in the indirect address register 42 is checked for an address error by the parity check circuit 44. If there is an error, the error flag 46 is set to "1", and the inverter 47 outputs a "0" level signal. Is output to shut off all AND circuits 48 ₁ , 48 ₂ , ... 48 _m provided on the input side of the data registers 45 ₁ , 45 ₂ , ... 45 _m , respectively.

As a result, the data to be written, which is sent following the indirect address data from the main processor, is blocked by this AND circuit before being supplied to the data register 45 from the receiving section 41, and any data register 45 is blocked. Should not be written.

If the address error is not detected by the parity check circuit 44, the output of the inverter 47 is "1".
Since the write clock is supplied to this data register via the AND circuit 48 ₂ corresponding to the data register selected by the decoder 43, for example, 45 ₂ , it is received by the receiving unit 41 following this indirect address. The data is written to register 45 ₂ above.

The address decoder 49 sends out the address of this data register in order to notify the main processor etc. of the address of the data register in which the data has been written as described above. If the flag 46 is set, the AND circuit 50 is cut off by the "0" output of the inverter 47, so that the address from the address recorder 49 is not supplied to the transmission unit 51. Therefore, the response signal to the main processor is the response signal. Not sent out on line 16.

In the main processor, a timer similar to that indicated by the reference numeral 53 in this figure is activated at the time of sending the address,
The "1" level signal output after the timer 53 has timed out is supplied to one input terminal, and the error response signal from the sub-processor is supplied from the receiving section 52 to the other input terminal from the AND circuit 54. The "1" output of (1) informs the CPU (not shown) that the address has an error.

The AND circuits 55 ₁ , 55 ₂ , ... 55 _m provided on the output side of the data levels 45 ₁ , 45 ₂ , ... 45 _m send the data stored in these data registers 45 to the main processor. In the same manner as in the case of writing described above, a data register to be read is designated by a read address from the main processor, and the AND circuit provided corresponding to the designated data register, for example, 45 _1. 55 The data read from _{1 is} sent from the OR circuit 56 to the transmitter 57
Via the bus 15 to the main processor.

Even in the case of this read, if there is a parity error in the address from the main processor, the AND circuit 48 is in the cutoff state, so the clock is not supplied to the data register 45. Obviously, no data is sent to the main processor.

〔The invention's effect〕

According to the present invention, when the main processor accesses the data register of the sub processor, the address of the data register can be sent and then the data can be sent immediately. It is possible to achieve a remarkable effect that the effective processing efficiency can be remarkably improved as compared with the case where the response is stored and the data is transmitted.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention, and FIGS. 2 and 3 are diagrams showing an embodiment of the present invention.

Front page continued (72) Inventor Kenichi Abo 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Yasutoshi Sakurai 1015 Kamedotachu, Nakahara-ku, Kawasaki, Kanagawa (72) Invented Yushi Murata 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Masayoshi Takei, 1015, Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) Reference JP 61-18056 ( JP, A)

Claims (1)

[Claims] 1. A multiprocessor device comprising a plurality of processors having a register accessed from another processor, wherein each processor detects an error in an address of a register to be written sent from another processor. A detection unit, a write data blocking unit that blocks writing of data to be written, which is sent following the address, to the register by an error detection signal from the error detection unit, and an error from the error detection unit. A multiprocessor device, comprising: an end signal blocking means for blocking the transmission of the write end signal to the processor that has transmitted the address and the data by the detection signal.