JPH0786321A - Method for assembling semiconductor device - Google Patents
Method for assembling semiconductor deviceInfo
- Publication number
- JPH0786321A JPH0786321A JP5226255A JP22625593A JPH0786321A JP H0786321 A JPH0786321 A JP H0786321A JP 5226255 A JP5226255 A JP 5226255A JP 22625593 A JP22625593 A JP 22625593A JP H0786321 A JPH0786321 A JP H0786321A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- inner lead
- insulating tape
- conductor
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の組立方法
に関する。近年、超ＬＳＩ等の半導体デバイスの高集積
化、高速化に伴い、品質向上の要求が高まってきてお
り、いかに効率良く、高品質の製品を製造することが出
来るかが大きな課題となっている。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of assembling a semiconductor device. In recent years, as semiconductor devices such as VLSIs have become highly integrated and speeded up, demands for quality improvement have been increasing, and how to efficiently manufacture high-quality products has become a major issue. .
【０００２】[0002]
【従来の技術】図５は従来例の説明図である。図におい
て、１は半導体チップ、２はインナーリード、３は絶縁
テープ、４はパッド、５は導電体、６はモールド樹脂、
７はワイヤ、８は開口部、９は両面絶縁テープ、10はウ
エハ、11はダイステージ、12はAgペーストである。2. Description of the Related Art FIG. 5 is an explanatory view of a conventional example. In the figure, 1 is a semiconductor chip, 2 is an inner lead, 3 is an insulating tape, 4 is a pad, 5 is a conductor, 6 is a molding resin,
7 is a wire, 8 is an opening, 9 is a double-sided insulating tape, 10 is a wafer, 11 is a die stage, and 12 is Ag paste.
【０００３】従来の半導体装置の組立工程においては、
図５に示すような工程が一般に行われている。即ち、図
５（ａ）に示すように、スクライブ工程において、ウエ
ハ10からスクライブにより切り出された半導体チップ１
を、図５（ｂ）に示すように、ダイス付け工程におい
て、リードフレームのダイステージ11上に塗布された銀
ペースト12等の蝋材の上にのせ、半導体チップ１をスク
ラブ（摺動）しながら、ダイステージ11上に固定する。
その後、銀ペーストを長時間キュアして半導体チップを
しっかりダイステージ11に固着する。In the conventional semiconductor device assembly process,
The process as shown in FIG. 5 is generally performed. That is, as shown in FIG. 5A, the semiconductor chip 1 cut out from the wafer 10 by scribing in the scribing step.
As shown in FIG. 5 (b), in a dicing step, the semiconductor chip 1 is scrubbed (slipped) on a wax material such as the silver paste 12 applied on the die stage 11 of the lead frame. While fixing it on the die stage 11.
Then, the silver paste is cured for a long time to firmly fix the semiconductor chip to the die stage 11.
【０００４】次に、図５（ｃ) に示すように、ワイヤ付
け工程において、半導体チップ１上に形成されたAl等の
パッド４とリードフレーム２を30μｍ径程度の極細い金
線で接続する。Next, as shown in FIG. 5 (c), in a wire attaching step, the pad 4 made of Al or the like formed on the semiconductor chip 1 and the lead frame 2 are connected with an extremely thin gold wire having a diameter of about 30 μm. .
【０００５】続いて、図５（ｄ）に示すように、ダイス
テージ11上の半導体チップ１並びにインナーリード２の
部分を封止め工程において、モールド樹脂６により封止
成形する。Subsequently, as shown in FIG. 5D, the semiconductor chip 1 and the inner leads 2 on the die stage 11 are sealed and molded with a molding resin 6 in a sealing step.
【０００６】このように、ダイス付け工程では、ウエハ
10からスクライブした半導体チップ１をリードフレーム
のダイステージ11上に、ダイステージ11に塗布した銀ペ
ースト12を用い、その上で半導体チップ１をスクラブし
て接着していた。As described above, in the dicing process, the wafer is
The semiconductor chip 1 scribed from 10 was mounted on the die stage 11 of the lead frame using the silver paste 12 applied to the die stage 11, and the semiconductor chip 1 was scrubbed and bonded onto the die paste 11.
【０００７】[0007]
【発明が解決しようとする課題】この場合、銀ペースト
の量が一定せず、スクラブの仕方により、半導体チップ
の側面から銀ペーストが這い上がることが懸念され、ま
た、半導体チップを銀ベースによりダイステージに接着
した後、長時間、温度を上げて硬化させる必要があっ
た。In this case, the amount of silver paste is not constant, and it is feared that the silver paste may creep up from the side surface of the semiconductor chip due to the scrubbing method. After adhering to the stage, it was necessary to raise the temperature and cure for a long time.
【０００８】また、半導体チップとリードフレームのイ
ンナーリードを結ぶワイヤは微細なために強度的に弱
く、モールド樹脂封止工程で、樹脂の封入時の流れに押
されるためのワイヤフローが起こって、ワイヤの断線や
短絡がしばしば発生していた。Further, the wire connecting the semiconductor chip and the inner lead of the lead frame is minute and therefore weak in strength, and in the molding resin encapsulation process, a wire flow occurs due to being pushed by the flow during resin encapsulation. Wire breaks and shorts often occurred.
【０００９】従って、ダイス付けに長時間の処理を要
し、ダイス側面の銀ペーストの這い上がりを防止し、モ
ールド封止工程におけるワイヤフローを防止することが
必要であった。Therefore, it is necessary to process the die for a long time, prevent the silver paste from creeping up on the side surface of the die, and prevent the wire flow in the mold sealing step.
【００１０】本発明は、以上の点を鑑み、ダイス付け時
の時間短縮やペースト汚染をなくし、モールド封止工程
におけるワイヤフローをなくし、高品質の半導体製品を
得ることを目的として提供されるものである。In view of the above points, the present invention is provided for the purpose of obtaining a high quality semiconductor product by shortening the time for die attachment, eliminating paste contamination, eliminating wire flow in the mold sealing step. Is.
【００１１】[0011]
【課題を解決するための手段】図１は本発明の原理説明
図、図２〜図４は本発明の実施例の説明図である。図に
おいて、１は半導体チップ、２はインナーリード、３は
絶縁テープ、４はパッド、５は導電体、６はモールド樹
脂、７はワイヤ、８は開口部、９は両面絶縁テープであ
る。FIG. 1 is an explanatory view of the principle of the present invention, and FIGS. 2 to 4 are explanatory views of an embodiment of the present invention. In the figure, 1 is a semiconductor chip, 2 is an inner lead, 3 is an insulating tape, 4 is a pad, 5 is a conductor, 6 is a molding resin, 7 is a wire, 8 is an opening, and 9 is a double-sided insulating tape.
【００１２】上記問題点は、ダイス付け工程で銀ペース
ト等の蝋材を必要とするダイステージを使わず、絶縁テ
ープを用いて半導体チップをモールド樹脂封止工程まで
固定する手段を取り、併せてワイヤ付け工程も細いワイ
ヤを用いないで、シルクスクリーン等の導電材印刷に換
えて、大部分を絶縁テープで固定することにより、モー
ルド樹脂封止工程におけるワイヤフローをなくすことに
よって解決される。The above-mentioned problems are solved by not using a die stage which requires a wax material such as silver paste in the die attaching step but using a means for fixing the semiconductor chip to the mold resin sealing step using an insulating tape. The wire attaching step is also solved by eliminating the wire flow in the mold resin sealing step by fixing a large part with an insulating tape instead of printing a conductive material such as a silk screen without using a thin wire.
【００１３】即ち、本発明の目的は、モールド樹脂封止
型半導体装置の組立方法であって、図１に示すように、
半導体チップ１、とダイステージのないリードフレーム
のインナーリード２をともに絶縁テープ３に位置決めし
て接着し、次に、該半導体チップ１上のパッド４と該イ
ンナーリード２を導電体５で結線することにより、図２
に示すように、前記半導体チップ１の裏面、並びに前記
リードフレームのインナーリード２裏面を高分子樹脂か
らなる前記絶縁テープ３に位置決めして接着し、続いて
該半導体チップ１上のパッド４と該インナーリード２を
ワイヤ７で結線することにより、図３に示すように、前
記半導体チップ１の表面、並びに前記リードフレームの
インナーリード２表面を高分子樹脂からなる前記絶縁テ
ープ３に位置決めして接着し、続いて、該絶縁テープ３
に設けた開口部８を埋め、且つ、該半導体チップ１上の
前記パッド４と該インナーリード２の導電体結線部を繋
いで導電体５を印刷して、該半導体チップ１上の該パッ
ド４と該インナーリード２を結線することにより、図４
に示すように、前記半導体チップ１の表面、並びに前記
リードフレームのインナーリード２裏面をそれぞれ高分
子樹脂からなる両面絶縁テープ９の両面に対向して、該
両面絶縁テープ９及び該インナーリード２のそれぞれに
設けた開口部８を該半導体チップ１上のパッド４に位置
決めして接着し、続いて、該両面絶縁テープ９の開口部
８及び該インナーリード２の開口部８を導電体５で埋め
て、該半導体チップ１上の該パッド４と該インナーリー
ド２を結線することにより達成される。That is, an object of the present invention is a method of assembling a mold resin-sealed semiconductor device, as shown in FIG.
The semiconductor chip 1 and the inner lead 2 of the lead frame without a die stage are both positioned and adhered to the insulating tape 3, and then the pad 4 on the semiconductor chip 1 and the inner lead 2 are connected by a conductor 5. By doing so,
As shown in FIG. 3, the back surface of the semiconductor chip 1 and the back surface of the inner lead 2 of the lead frame are positioned and adhered to the insulating tape 3 made of polymer resin, and then the pad 4 on the semiconductor chip 1 and the pad 4 are attached. By connecting the inner lead 2 with the wire 7, as shown in FIG. 3, the surface of the semiconductor chip 1 and the surface of the inner lead 2 of the lead frame are positioned and adhered to the insulating tape 3 made of polymer resin. Then, the insulating tape 3
To fill the opening 8 provided in the semiconductor chip 1 and to connect the pad 4 on the semiconductor chip 1 to the conductor connecting portion of the inner lead 2 to print a conductor 5, and to print the conductor 4 on the semiconductor chip 1. By connecting the inner lead 2 and
As shown in FIG. 2, the front surface of the semiconductor chip 1 and the back surface of the inner lead 2 of the lead frame are opposed to both surfaces of a double-sided insulating tape 9 made of a polymer resin, respectively. The openings 8 provided in each are positioned and bonded to the pads 4 on the semiconductor chip 1, and subsequently, the openings 8 of the double-sided insulating tape 9 and the openings 8 of the inner leads 2 are filled with a conductor 5. And the inner lead 2 is connected to the pad 4 on the semiconductor chip 1.
【００１４】[0014]
【作用】本発明の方式では、ダイステージを用いず、半
導体チップを直接絶縁テーブで接着固定するため、銀ペ
ーストのような接着固定用の蝋材の塗布や蝋材の硬化の
ための加熱処理が不要となり、工程が大幅に簡易化さ
れ、ダイステージの変形も起こらない。In the method of the present invention, the semiconductor chip is directly adhered and fixed by the insulating tape without using the die stage. Therefore, a soldering material such as a silver paste for applying and fixing a wax material or a heat treatment for hardening the wax material is performed. Is unnecessary, the process is greatly simplified, and the die stage is not deformed.
【００１５】また、更に、絶縁テープによる導電体の固
定により、従来の金線が不要となるため、ワイヤフロー
によるワイヤの断線，短絡等の問題も消滅する。Furthermore, since the conventional gold wire is not required because the conductor is fixed by the insulating tape, the problems such as wire breakage and short circuit due to wire flow are eliminated.
【００１６】[0016]
【実施例】図２〜図４は本発明の実施例の説明図であ
る。図において、１は半導体チップ、２はインナーリー
ド、３は絶縁テープ、４はパッド、５は導電体、６はモ
ールド樹脂、７はワイヤ、８は開口部、９は両面絶縁テ
ープである。2 to 4 are explanatory views of an embodiment of the present invention. In the figure, 1 is a semiconductor chip, 2 is an inner lead, 3 is an insulating tape, 4 is a pad, 5 is a conductor, 6 is a molding resin, 7 is a wire, 8 is an opening, and 9 is a double-sided insulating tape.
【００１７】図２に本発明の第１の実施例を示す。本発
明の実施例においては、全て、４８０ピンのＱＦＰモー
ルドパッケージを用いたが、図面は簡略化して３６ピン
で表示した。FIG. 2 shows a first embodiment of the present invention. In all of the embodiments of the present invention, a 480-pin QFP mold package is used, but the drawing is simplified and shown with 36 pins.
【００１８】図２（ａ）に断面図、図２（ｂ）に平面図
で示すように、半導体チップ１及びダイステージのない
リードフレームのインナーリード２をツールを用いて位
置決め固定した後、半導体チップ１とインナーリード２
裏面を絶縁テープ３の接着剤のある面に接着固定する。As shown in the sectional view of FIG. 2A and the plan view of FIG. 2B, the semiconductor chip 1 and the inner lead 2 of the lead frame without the die stage are positioned and fixed using a tool, and then the semiconductor Chip 1 and inner lead 2
The back surface is adhered and fixed to the surface of the insulating tape 3 having the adhesive.
【００１９】そして、通常のワイヤボンディングにより
30μｍ径の金線をワイヤ付けする。この後、モールド樹
脂を用い、通常のモールドプレス装置を用いて、モール
ド樹脂封止型半導体デバイスに、図１（ｃ）に示したよ
うに、成形する。Then, by ordinary wire bonding
Wire a 30 μm diameter gold wire. After that, a mold resin is used to mold into a mold resin-sealed semiconductor device as shown in FIG. 1C, using a normal mold press machine.
【００２０】図３に本発明の第２の実施例を示す。図３
（ａ）に断面図で示すように、半導体チップ１及びダイ
ステージのないリードフレームのインナーリード２をツ
ールを用いて位置決め固定した後、半導体チップ１表面
とインナーリード２表面を絶縁テープ３の接着剤のある
面に接着固定する。FIG. 3 shows a second embodiment of the present invention. Figure 3
As shown in the sectional view in (a), after the semiconductor chip 1 and the inner lead 2 of the lead frame having no die stage are positioned and fixed using a tool, the surface of the semiconductor chip 1 and the surface of the inner lead 2 are bonded with an insulating tape 3. Adhesively fix to the surface with the agent.
【００２１】絶縁テープ３には予め、半導体チップ１の
パッド部分とインナーリード２の導電体５接合面に、図
３（ａ）の断面図に点線で示すように、開口部８を設け
てある。The insulating tape 3 is provided with an opening 8 in advance on the bonding surface of the pad portion of the semiconductor chip 1 and the conductor 5 of the inner lead 2, as shown by the dotted line in the sectional view of FIG. .
【００２２】銀ペーストのような導電体５をシルクスク
リーン印刷により、位置決めして、絶縁テープ３の上か
ら、図３（ｂ）の断面図、図３（ｃ）の平面図に黒い太
線で示すように導電体５の部分のみを印刷する。A conductor 5 such as a silver paste is positioned by silk screen printing, and is shown by a thick black line in the sectional view of FIG. 3B and the plan view of FIG. 3C from above the insulating tape 3. Thus, only the portion of the conductor 5 is printed.
【００２３】この後、モールド樹脂を用い、通常のモー
ルドプレス装置を用いて、モールド樹脂封止型半導体デ
バイスに図１（ｃ）に示すような第１の実施例と同様に
成形する。After that, a molding resin is used to mold a molding resin-sealed semiconductor device in the same manner as in the first embodiment as shown in FIG.
【００２４】図４に本発明の第３の実施例を示す。図４
（ａ）に断面図で示すように、半導体チップ１をツール
を用いて位置決め固定した後、半導体チップ１表面を両
面絶縁テープ９に接着固定する。FIG. 4 shows a third embodiment of the present invention. Figure 4
As shown in the cross-sectional view in (a), the semiconductor chip 1 is positioned and fixed using a tool, and then the surface of the semiconductor chip 1 is adhesively fixed to the double-sided insulating tape 9.
【００２５】次に、両面絶縁テープ９を表面に接着した
半導体チップ１をツールを用いて位置決め固定した後、
インナーリード２の裏面に位置決めして、接着固定す
る。絶縁テープ３には予め、半導体チップ１のパッド部
分とインナーリード２の導電体５接合面に、図４（ａ）
の断面図に点線で示すように、開口部８を設けてある。Next, after the semiconductor chip 1 having the double-sided insulating tape 9 adhered on its surface is positioned and fixed using a tool,
The inner lead 2 is positioned on the back surface and fixed by adhesion. In the insulating tape 3, the pad portion of the semiconductor chip 1 and the conductor 5 joining surface of the inner lead 2 are previously attached to the insulating tape 3 as shown in FIG.
As shown by the dotted line in the sectional view of FIG.
【００２６】銀ペーストのような導電体５をシルクスク
リーン印刷により、位置決めして、インナーリード２、
及び両面絶縁テープ９の開口部８を通して、図４（ｂ）
の断面図に黒丸棒、図４（ｃ）の平面図に黒丸で示すよ
うに、スクリーン印刷により埋め込み印刷を行う。The conductor 5 such as a silver paste is positioned by silk screen printing, and the inner lead 2,
4B through the opening 8 of the double-sided insulating tape 9.
As shown by a black circle in the cross-sectional view and a black circle in the plan view of FIG. 4C, embedded printing is performed by screen printing.
【００２７】この後、モールド樹脂６を用い、通常のモ
ールドプレス装置を用いて、モールド樹脂封止型半導体
デバイスに、図１（ｃ）に示すような第１の実施例と同
様に成形する。Thereafter, the mold resin 6 is molded into a mold resin-sealed semiconductor device by using a normal mold press machine in the same manner as in the first embodiment as shown in FIG. 1C.
【００２８】[0028]
【発明の効果】以上説明したように、本発明によれば、
ダイステージのないリードフレームを用い、絶縁テープ
で半導体チップとリードフレームのインナーリードを位
置決めして固定出来るため、ダイステージに半導体チッ
プを固定するための蝋材等の摺動、及び加熱作業を要す
る工程が不要となり、工程が大幅に簡略化され、ダイス
テージの変形といった問題も消滅する。As described above, according to the present invention,
Since a lead frame without a die stage can be used to position and fix the semiconductor chip and the inner lead of the lead frame with an insulating tape, it is necessary to slide the wax material and the like to fix the semiconductor chip to the die stage, and to perform heating work. The process becomes unnecessary, the process is greatly simplified, and the problem of deformation of the die stage disappears.
【００２９】更に、絶縁テープによって、ワイヤに換え
て、導電体を印刷等で絶縁テープ上及びスルーホール内
に直接配線出来るため、ワイヤフローによるワイヤの断
線，短絡等の問題も消滅する。Furthermore, since the conductor can be directly printed on the insulating tape and in the through hole by printing or the like in place of the wire by the insulating tape, problems such as wire breakage and short circuit due to wire flow disappear.
【００３０】従って、ダイス付け工程やワイヤ付け工程
の時間短縮が可能となり、半導体デバイスの品質向上、
高信頼性の確保に寄与するところが大きい。Therefore, it is possible to shorten the time of the die attaching process and the wire attaching process, and improve the quality of the semiconductor device.
It greatly contributes to ensuring high reliability.
【図面の簡単な説明】[Brief description of drawings]
【図１】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図２】 本発明の第一の実施例の説明図FIG. 2 is an explanatory diagram of the first embodiment of the present invention.
【図３】 本発明の第二の実施例の説明図FIG. 3 is an explanatory diagram of a second embodiment of the present invention.
【図４】 本発明の第三の実施例の説明図FIG. 4 is an explanatory diagram of a third embodiment of the present invention.
【図５】 従来例の説明図FIG. 5 is an explanatory diagram of a conventional example.
１ 半導体チップ ２ インナーリード ３ 絶縁テープ ４ パッド ５ 導電体 ６ モールド樹脂 ７ ワイヤ ８ 開口部 ９ 両面絶縁テープ 1 Semiconductor Chip 2 Inner Lead 3 Insulation Tape 4 Pad 5 Conductor 6 Mold Resin 7 Wire 8 Opening 9 Double-sided Insulation Tape
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小林 賢司 宮城県柴田郡村田町大字村田字西ケ丘１番 地の１ 株式会社富士通宮城エレクトロニ クス内 (72)発明者 小林 均 宮城県柴田郡村田町大字村田字西ケ丘１番 地の１ 株式会社富士通宮城エレクトロニ クス内 (72)発明者 伊藤 則夫 宮城県柴田郡村田町大字村田字西ケ丘１番 地の１ 株式会社富士通宮城エレクトロニ クス内 (72)発明者 佐々木 健一 宮城県柴田郡村田町大字村田字西ケ丘１番 地の１ 株式会社富士通宮城エレクトロニ クス内 (72)発明者 伊藤 保 宮城県柴田郡村田町大字村田字西ケ丘１番 地の１ 株式会社富士通宮城エレクトロニ クス内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenji Kobayashi Kenji Kobayashi No.1 Nishigaoka, Murata, Murata-cho, Shibata-gun, Miyagi Prefecture 1st in Fujitsu Miyagi Electronics Co., Ltd. (72) Inventor Hitoshi Kobayashi Shibata-gun, Miyagi Prefecture 1st in Nishigaoka, Murata-Chi, Murata-cho In Fujitsu Miyagi Electronics Co., Ltd. (72) Inventor Norio Ito 1 in Nishigaoka, Murata-Cho, Murata-cho, Miyagi Prefecture 1st in Fuji Miyagi Electro Co., Ltd. In Nix (72) Inventor Kenichi Sasaki 1st in Nishigaoka, Murata, Murata-cho, Shibata-gun, Miyagi Prefecture 1 In Fujitsu Miyagi Electronic Co., Ltd. (72) Inventor, Ito Murata, Murata-cho, Shibata-gun, Miyagi 1 in Nishigaoka, Fuji Miyagi Electronics Co., Ltd.
Claims (4)
法であって、 半導体チップ(1) 、とダイステージのないリードフレー
ムのインナーリード(2)をともに絶縁テープ(3) に位置
決めして接着し、次に、該半導体チップ(1) 上のパッド
(4) と該インナーリード(2) を導電体(5) で結線し、該
半導体チップ(1)、並びに該インナーリード(2) をモー
ルド樹脂(6) で封止することを特徴とする半導体装置の
組立方法。1. A method for assembling a mold resin-sealed semiconductor device, comprising positioning a semiconductor chip (1) and an inner lead (2) of a lead frame without a die stage together on an insulating tape (3) and adhering them. And then the pads on the semiconductor chip (1)
A semiconductor characterized in that (4) and the inner lead (2) are connected by a conductor (5), and the semiconductor chip (1) and the inner lead (2) are sealed with a mold resin (6). How to assemble the device.
記リードフレームのインナーリード(2) 裏面を高分子樹
脂からなる前記絶縁テープ(3) に位置決めして接着し、
続いて該半導体チップ(1) 上のパッド(4) と該インナー
リード(2) をワイヤ(7) で結線することを特徴とする請
求項１記載の半導体装置の組立方法。2. The back surface of the semiconductor chip (1) and the back surface of the inner lead (2) of the lead frame are positioned and adhered to the insulating tape (3) made of a polymer resin,
2. The method of assembling a semiconductor device according to claim 1, wherein the pad (4) on the semiconductor chip (1) and the inner lead (2) are subsequently connected by a wire (7).
記リードフレームのインナーリード(2) 表面を高分子樹
脂からなる前記絶縁テープ(3) に位置決めして接着し、
続いて、該絶縁テープ(3) に設けた開口部(8) を埋め、
且つ、該半導体チップ(1) 上の前記パッド(4) と該イン
ナーリード(2) の導電体結線部を繋いで導電体(5) を印
刷して、該半導体チップ(1) 上の該パッド(4) と該イン
ナーリード(2) を結線することを特徴とする請求項１記
載の半導体装置の組立方法。3. The surface of the semiconductor chip (1) and the surface of the inner lead (2) of the lead frame are positioned and adhered to the insulating tape (3) made of polymer resin,
Then, fill the opening (8) provided in the insulating tape (3),
Moreover, the conductor (5) is printed by connecting the pad (4) on the semiconductor chip (1) and the conductor connecting portion of the inner lead (2), and the pad on the semiconductor chip (1) is printed. The method for assembling a semiconductor device according to claim 1, wherein the inner lead (2) and the inner lead (2) are connected.
記リードフレームのインナーリード(2) 裏面をそれぞれ
高分子樹脂からなる両面絶縁テープ(9) の両面に対向し
て、該両面絶縁テープ(9) 及び該インナーリード(2) の
それぞれに設けた開口部(8) を該半導体チップ(1) 上の
パッド(4) に位置決めして接着し、続いて、該両面絶縁
テープ(9) の開口部(8) 及び該インナーリード(2) の開
口部(8) を導電体(5) で埋めて、該半導体チップ(1) 上
の該パッド(4) と該インナーリード(2) を結線すること
を特徴とする請求項１記載の半導体装置の組立方法。4. The double-sided insulating tape (9) is formed by facing the front surface of the semiconductor chip (1) and the back surface of the inner lead (2) of the lead frame to both sides of a double-sided insulating tape (9) made of polymer resin. 9) and the openings (8) provided in the inner leads (2) are positioned and bonded to the pads (4) on the semiconductor chip (1), and then the double-sided insulating tape (9) is attached. The opening (8) and the opening (8) of the inner lead (2) are filled with a conductor (5), and the pad (4) on the semiconductor chip (1) and the inner lead (2) are connected. The method for assembling a semiconductor device according to claim 1, wherein
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5226255A JPH0786321A (en) | 1993-09-13 | 1993-09-13 | Method for assembling semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5226255A JPH0786321A (en) | 1993-09-13 | 1993-09-13 | Method for assembling semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0786321A true JPH0786321A (en) | 1995-03-31 |
Family
ID=16842334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5226255A Pending JPH0786321A (en) | 1993-09-13 | 1993-09-13 | Method for assembling semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0786321A (en) |
-
1993
- 1993-09-13 JP JP5226255A patent/JPH0786321A/en active Pending
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