JPH0786159A - Growing method of compound semiconductor - Google Patents

Growing method of compound semiconductor

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Publication number
JPH0786159A
JPH0786159A JP25255093A JP25255093A JPH0786159A JP H0786159 A JPH0786159 A JP H0786159A JP 25255093 A JP25255093 A JP 25255093A JP 25255093 A JP25255093 A JP 25255093A JP H0786159 A JPH0786159 A JP H0786159A
Authority
JP
Japan
Prior art keywords
compound semiconductor
substrate
temperature
growing
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25255093A
Other languages
Japanese (ja)
Inventor
Masakiyo Ikeda
正清 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP25255093A priority Critical patent/JPH0786159A/en
Publication of JPH0786159A publication Critical patent/JPH0786159A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent substances adhering to the inside of furnace from falling by growing a single crystal Si layer on an Si substrate at a specified temperature or below, further growing a GaAs buffer layer by a specified thickness or less at a specified temperature or below, conducting the annealing at a temperature within a specified range, and then epitaxially growing a III-V compound semiconductor thereon. CONSTITUTION:The substrate temperature is set at 800 deg.C or below and hydrogen gas is fed into a reaction furnace together with disilane thus forming a single crystal Si layer on an Si substrate. The substrate temperature is then set at 450 deg.C and trimethyl gallium is fed into the reaction furnace together with arsine thus growing a GaAs butter layer by 50nm thick or less. Annealing is then conducted with the substrate temperature being set in the range of 700-800 deg.C. Subsequently, trimethyl gallium and arsine are fed to epitaxially grow a III-V compound semiconductor, i.e., a GaAs single crystal. This method eliminates troubles, e.g. falling of substances adhering to the inside of furnace and mechanical malfunction of the system, and produces a high quality compound semiconductor stably.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はSi基板上にGaAs等
の III−V族化合物半導体をエピタキシャル成長させる
成長方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a growth method for epitaxially growing a III-V group compound semiconductor such as GaAs on a Si substrate.

【0002】[0002]

【従来の技術】GaAs等の III−V族化合物半導体は
Siに比較して電子移動度が大きいため高速電子デバイ
スの材料として優れている。しかしデバイス作成に用い
る基板としてはSiの方がGaAsに比較して大口径の
ものが安価に入手可能である。そこでこのような両者の
利点を生かしたものとしてSi基板上にGaAs等のII
I−V族化合物半導体をエピタキシャル成長させてデバ
イスを作成する方法が研究開発されている。
2. Description of the Related Art III-V group compound semiconductors such as GaAs are excellent as materials for high-speed electronic devices because they have a higher electron mobility than Si. However, as a substrate used for device fabrication, Si having a larger diameter than that of GaAs is available at a low cost. Therefore, it is necessary to use the advantages of both of these to make II of GaAs etc. on the Si substrate.
Research and development has been conducted on a method of epitaxially growing a group IV compound semiconductor to form a device.

【0003】この場合の基本的な成長技術としては2段
階成長法(特公平2-36059 号公報、特公平2-36060 号公
報、M.Akiyama et al., J.Crystal Growth vol.77 (19
86)p.490)がよく知られている。この2段階成長法は I
II−V族化合物半導体の成長法である有機金属気相成長
法(MOVPE法)、分子線エピタキシー法(MBE
法)、ケミカルビームエピタキシー法(CBE法)等い
ずれの方法にも適用可能であるが、ここではMOVPE
法で2段階成長法を実施する場合について説明する。
As a basic growth technique in this case, a two-stage growth method (Japanese Patent Publication No. 2-36059, Japanese Patent Publication No. 2-36060, M. Akiyama et al., J. Crystal Growth vol.77 (19
86) p.490) is well known. This two-step growth method is
Metal-organic vapor phase epitaxy (MOVPE), which is a method for growing II-V group compound semiconductors, molecular beam epitaxy (MBE)
Method), chemical beam epitaxy method (CBE method), etc., but here, MOVPE
A case where the two-step growth method is carried out will be described.

【0004】図1に2段階成長法の温度シーケンスの一
例を示し、これに沿って説明する。先ずSi基板をHF
で処理して表面酸化膜を除去し、これを水洗乾燥した後
反応炉内に設置する。反応炉内にはキャリアガスとして
2 ガスが流される。
FIG. 1 shows an example of a temperature sequence of the two-step growth method, which will be described. First, the Si substrate is HF
To remove the surface oxide film, wash with water and dry it, and then install in a reaction furnace. H 2 gas is flowed as a carrier gas in the reaction furnace.

【0005】そして2段階成長法の第1の工程として
は、Si基板を 950℃に加熱して10分間の熱処理を行う
(図1の)。この工程の目的は、上記前処理でSi基
板は表面酸化膜を除去されるが、これを反応炉内に設置
するまでに再度酸化膜が形成されるのでこの酸化膜を除
去するためである。
In the first step of the two-step growth method, the Si substrate is heated to 950 ° C. and heat-treated for 10 minutes (see FIG. 1). The purpose of this step is to remove the surface oxide film of the Si substrate by the above-mentioned pretreatment, but the oxide film is formed again by the time it is installed in the reaction furnace, so that this oxide film is removed.

【0006】第2の工程としては基板の温度を 450℃に
下げ(図1の)、温度が安定した後反応炉内にトリメ
チルガリウム(TMGa)、アルシン(AsH3 )を導
入して基板上にGaAsバッファ層を20nmの厚さに成長
させる。なおAsH3 はこの工程以降全工程が終了する
まで反応炉内に導入し続ける。
In the second step, the temperature of the substrate is lowered to 450 ° C. (shown in FIG. 1), and after the temperature is stabilized, trimethylgallium (TMGa) and arsine (AsH 3 ) are introduced into the reaction chamber and the substrate is placed on the substrate. A GaAs buffer layer is grown to a thickness of 20 nm. AsH 3 is continuously introduced into the reaction furnace after this step until all steps are completed.

【0007】第3の工程としては基板温度を 750℃まで
上げて5分間アニールする(図1の)。
In the third step, the substrate temperature is raised to 750 ° C. and annealed for 5 minutes (FIG. 1).

【0008】第4の工程としては基板温度を 650℃とし
て(図1の)、温度安定後TMGaを再度導入して所
望のGaAsを成長させる。その後はTMGaの導入を
停止して温度を下げる。
In the fourth step, the substrate temperature is set to 650 ° C. (FIG. 1), TMGa is introduced again after temperature stabilization, and desired GaAs is grown. After that, the introduction of TMGa is stopped and the temperature is lowered.

【0009】[0009]

【発明が解決しようとする課題】上記の2段階成長法に
おいて、その第1の工程で酸化膜を除去するために基板
温度を 900℃以上の高温にするのは、第4の工程で成長
させるGaAsの特性の再現性が乏しくなるという問題
を解消するためであるが、他方 900℃以上に設定すると
反応炉内の付着物が剥離して落下しやすくなり、これが
落下して基板に付着したときには表面欠陥の一因となる
という問題があった。
In the above two-step growth method, the substrate temperature is set to 900 ° C. or higher in order to remove the oxide film in the first step, and the fourth step is to grow. This is to solve the problem of poor reproducibility of GaAs characteristics. On the other hand, if the temperature is set to 900 ° C or higher, the deposits inside the reaction furnace will peel off and fall off easily. There is a problem that it contributes to surface defects.

【0010】また反応装置として近年発達してきた自公
転型反応炉(複数の基板を円周上に配置したサセプタが
回転すると同時に、各基板自身も単独で回転する構成の
装置)では、基板自身の自転のために歯車等の機械的な
回転部品を用いているので高温に加熱されるとこれらが
熱膨張を起こして自転が停止したりする不具合が発生す
る。さらに場合によっては回転軸に無理な負荷がかかる
ために部品が破壊したりする問題があった。
Further, in a revolving-type reactor (a device in which each substrate itself rotates at the same time as a susceptor having a plurality of substrates arranged on the circumference rotates) which has recently been developed as a reactor, Since mechanical rotating parts such as gears are used for rotation, when they are heated to a high temperature, thermal expansion of these causes a problem that rotation stops. Further, in some cases, there is a problem that parts are destroyed due to an excessive load applied to the rotating shaft.

【0011】[0011]

【課題を解決するための手段】本発明はこれらの問題に
鑑みて種々検討の結果、GaAs半導体特性の再現性に
優れ、かつ基板の表面欠陥をなくした化合物半導体の成
長法を開発したものである
As a result of various studies in view of these problems, the present invention has developed a method for growing a compound semiconductor which has excellent reproducibility of GaAs semiconductor characteristics and eliminates surface defects of the substrate. is there

【0012】即ち本発明は、非酸化性雰囲気の反応炉内
でSi基板上に化合物半導体をエピタキシャル成長させ
る化合物半導体の成長方法において、該Si基板上に 8
00℃以下の温度で単結晶Si層を成長させる第1工程
と、形成した該単結晶Si層上に450 ℃以下の温度でG
aAsバッファ層を50nm以下の厚さに成長させる第2工
程と、該GaAsバッファ層を 700〜800 ℃の温度でア
ニールする第3工程と、該GaAsバッファ層上に III
−V族化合物半導体をエピタキシャル成長させる第4工
程とを有することを特徴とするものである。また、前記
III−V族化合物半導体としては、GaAs、AlGa
As及びInGaAsの群から選ばれるいずれか1種ま
たは2種以上の積層構造があげられる。
That is, the present invention provides a method for growing a compound semiconductor in which a compound semiconductor is epitaxially grown on a Si substrate in a reaction furnace in a non-oxidizing atmosphere.
The first step of growing a single crystal Si layer at a temperature of 00 ° C or lower, and G at a temperature of 450 ° C or lower on the formed single crystal Si layer.
A second step of growing the aAs buffer layer to a thickness of 50 nm or less, a third step of annealing the GaAs buffer layer at a temperature of 700 to 800 ° C., and a third step on the GaAs buffer layer.
And a fourth step of epitaxially growing a group-V compound semiconductor. Also, the above
III-V group compound semiconductors include GaAs and AlGa
There may be mentioned any one kind or two or more kinds of laminated structures selected from the group of As and InGaAs.

【0013】[0013]

【作用】このように本発明では第1工程においてSi基
板を 800℃以下の温度に加熱するものである。従って従
来の 900℃以上の加熱によって生ずる炉内付着物の剥離
や回転系の故障といった不具合は発生しなくなる。一方
上記の通り 800℃以下の基板温度ではSi基板上の表面
酸化膜は十分に除去できなくなる。しかし本発明では反
応炉内でこのSi基板上に単結晶Si層を新たに形成す
るので、引き続き行う第2工程で形成するGaAsバッ
ファ層は表面酸化膜のないSi層上に形成されることに
なり、実質的に従来の第1の工程を行ったのと同一の効
果を生ずるものである。
As described above, in the present invention, the Si substrate is heated to a temperature of 800 ° C. or lower in the first step. Therefore, problems such as separation of deposits in the furnace and failure of the rotating system caused by conventional heating above 900 ° C will not occur. On the other hand, as described above, the surface oxide film on the Si substrate cannot be sufficiently removed at the substrate temperature of 800 ° C. or lower. However, in the present invention, since the single crystal Si layer is newly formed on the Si substrate in the reaction furnace, the GaAs buffer layer formed in the subsequent second step is formed on the Si layer having no surface oxide film. Thus, substantially the same effect as that obtained by performing the conventional first step is produced.

【0014】[0014]

【実施例】以下に本発明を実施例に基いてさらに説明す
る。
EXAMPLES The present invention will be further described below based on examples.

【0015】(実施例)次の→→→の工程で反
応炉内に設置したSi基板上にGaAs化合物半導体を
エピタキシャル成長させ、半導体サンプルAを得た。
(Example) A semiconductor sample A was obtained by epitaxially growing a GaAs compound semiconductor on a Si substrate placed in a reaction furnace in the next step of →→→.

【0016】:基板温度を 750℃とし、反応炉内にキ
ャリアガスとしとH2 ガスと共にジシラン(Si
2 6 )を2cc/minの流量で10分間流して単結晶Si層
を形成した。 :基板温度を 450℃として反応炉内にTMGaを16cc
/min、AsH3 を 480cc/min流し、GaAsバッファ層
を20nmの厚さに成長させた。 :基板温度を 750℃として反応炉内にAsH3 を 100
cc/min流しながら10分間アニールした。 :基板温度を 650℃としてTMGaを 160cc/min、A
sH3 を 480cc/min流しGaAs単結晶を3μmの厚さ
にエピタキシャル成長させた。
[0016]: a substrate temperature of 750 ° C., and the carrier gas into the reactor and H 2 gas with disilane (Si
2 H 6 ) was flowed at a flow rate of 2 cc / min for 10 minutes to form a single crystal Si layer. : TMGa 16cc in reaction furnace with substrate temperature 450 ℃
/ min, AsH 3 was flown at 480 cc / min to grow a GaAs buffer layer to a thickness of 20 nm. : Set substrate temperature to 750 ° C and add 100 AsH 3 to the reactor.
Annealing was performed for 10 minutes while flowing cc / min. : TMGa 160cc / min, A with substrate temperature 650 ℃
A GaAs single crystal was epitaxially grown to a thickness of 3 μm by flowing sH 3 at 480 cc / min.

【0017】(従来例)従来例として上記の条件を下
記′の条件に変更した従来の2段階成長法によりGa
As化合物半導体サンプルBを得た。 ′:基板温度を 950℃としてキャリアガス(H2 )中
で10分間加熱した。
(Conventional Example) As a conventional example, the above-mentioned conditions are changed to the following conditions' by the conventional two-step growth method to obtain Ga.
As compound semiconductor sample B was obtained. ′: The substrate temperature was set to 950 ° C. and the substrate was heated in a carrier gas (H 2 ) for 10 minutes.

【0018】(比較例)上記2段階成長法における′
の条件を下記″に変更してGaAs化合物半導体サン
プルCを得た。 ″:基板温度を 750℃としてキャリアガス(H2 )中
で10分間加熱した。
(Comparative Example) In the above two-step growth method
Was changed to the following "" to obtain a GaAs compound semiconductor sample C. ": The substrate temperature was 750 ° C. and heating was performed in a carrier gas (H 2 ) for 10 minutes.

【0019】以上の各GaAs化合物半導体サンプルA
〜Cについて先ず表面状態を比較したところ実施例およ
び従来例のサンプルA、Bはいずれも鏡面であったが、
Si基板上の表面酸化膜が十分除去されていない比較例
サンプルCの表面は白濁しており不良品であった。
Each of the above GaAs compound semiconductor sample A
First, the surface conditions of the samples A to B were compared, and the samples A and B of the examples and the conventional examples were both mirror-finished.
The surface of the comparative sample C in which the surface oxide film on the Si substrate was not sufficiently removed was cloudy and was a defective product.

【0020】次にサンプルA、BについてHall測定を行
った結果を表1に示す。
Next, Table 1 shows the results of Hall measurement performed on Samples A and B.

【0021】[0021]

【表1】 [Table 1]

【0022】このように本発明法で得られた化合物半導
体と従来の2段階成長法で得られたものとはほぼ同等の
特性を有することがわかる。これは本発明例のの工程
でSi2 6 を反応炉内に導入することによりSi基板
上に表面酸化膜のない単結晶Si層が形成されているた
め、上記の工程を開始するに際してSi基板上には酸
化膜のないSi層が露出していることになり、従来の2
段階成長法で第1の工程を実施した場合と同じ効果が発
揮されることによるものである。
As described above, it can be seen that the compound semiconductor obtained by the method of the present invention and the one obtained by the conventional two-step growth method have almost the same characteristics. This is because a single crystal Si layer without a surface oxide film was formed on the Si substrate by introducing Si 2 H 6 into the reaction furnace in the step of the present invention, and therefore Si was not used when starting the above step. It means that the Si layer without oxide film is exposed on the substrate.
This is because the same effect as when the first step is performed by the step growth method is exhibited.

【0023】[0023]

【発明の効果】このように本発明によれば従来と同等の
半導体特性を有するにもかかわらず反応炉内付着物の落
下や装置自体の機械的な故障等の問題がなくなり、品質
の優れた化合物半導体が安定して得られる等の効果を有
する。
As described above, according to the present invention, although the semiconductor characteristics are the same as those of the conventional one, the problems such as the fall of the deposits in the reaction furnace and the mechanical failure of the apparatus itself are eliminated, and the quality is excellent. It has effects such as stable production of compound semiconductors.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来の2段階成長法の温度シーケンスの例を示
す線図である。
FIG. 1 is a diagram showing an example of a temperature sequence of a conventional two-step growth method.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 非酸化性雰囲気の反応炉内でSi基板上
に化合物半導体をエピタキシャル成長させる化合物半導
体の成長方法において、該Si基板上に 800℃以下の温
度で単結晶Si層を成長させる第1工程と、形成した該
単結晶Si層上に 450℃以下の温度でGaAsバッファ
層を50nm以下の厚さに成長させる第2工程と、該GaA
sバッファ層を 700〜800 ℃の温度でアニールする第3
工程と、該GaAsバッファ層上に III−V族化合物半
導体をエピタキシャル成長させる第4工程とを有するこ
とを特徴とする化合物半導体の成長方法。
1. A method of growing a compound semiconductor in which a compound semiconductor is epitaxially grown on a Si substrate in a reaction furnace in a non-oxidizing atmosphere, wherein a single crystal Si layer is grown on the Si substrate at a temperature of 800 ° C. or lower. A step of growing a GaAs buffer layer on the formed single crystal Si layer at a temperature of 450 ° C. or less to a thickness of 50 nm or less, and the GaA
s The buffer layer is annealed at a temperature of 700-800 ℃
A method of growing a compound semiconductor, comprising: a step; and a fourth step of epitaxially growing a III-V group compound semiconductor on the GaAs buffer layer.
【請求項2】 前記 III−V族化合物半導体がGaA
s、AlGaAs及びInGaAsの群から選ばれるい
ずれか1種または2種以上の積層構造である請求項1記
載の化合物半導体の成長方法。
2. The III-V group compound semiconductor is GaA.
The method for growing a compound semiconductor according to claim 1, wherein the compound semiconductor has a laminated structure of one or more selected from the group consisting of s, AlGaAs and InGaAs.
JP25255093A 1993-09-14 1993-09-14 Growing method of compound semiconductor Pending JPH0786159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25255093A JPH0786159A (en) 1993-09-14 1993-09-14 Growing method of compound semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25255093A JPH0786159A (en) 1993-09-14 1993-09-14 Growing method of compound semiconductor

Publications (1)

Publication Number Publication Date
JPH0786159A true JPH0786159A (en) 1995-03-31

Family

ID=17238936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25255093A Pending JPH0786159A (en) 1993-09-14 1993-09-14 Growing method of compound semiconductor

Country Status (1)

Country Link
JP (1) JPH0786159A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127326A (en) * 1999-08-13 2001-05-11 Oki Electric Ind Co Ltd Semiconductor substrate, method of manufacturing the same, solar cell using the same and manufacturing method thereof
WO2010099544A3 (en) * 2009-02-27 2011-01-13 Alta Devices, Inc. Tiled substrates for deposition and epitaxial lift off processes

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001127326A (en) * 1999-08-13 2001-05-11 Oki Electric Ind Co Ltd Semiconductor substrate, method of manufacturing the same, solar cell using the same and manufacturing method thereof
WO2010099544A3 (en) * 2009-02-27 2011-01-13 Alta Devices, Inc. Tiled substrates for deposition and epitaxial lift off processes

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