JPH0785577B2 - Video recording / playback device - Google Patents

Description

The present invention relates to recording and reproducing television video signals.

[Conventional technology]

Conventionally, there is a VTR as a means for recording and reproducing video signals. The VTR is an excellent device as a means of simply recording video signals for a long time. However, there is a drawback in that it takes time to rewind the recorded data without fail to rewind the tape. There is also a drawback that it cannot be reproduced while recording.

[Problems to be solved by the invention]

Such a defect is particularly apparent on the surface when the VTR is used as a slow motion device for sports or the like. That is, when a certain scene is to be played back in slow motion, the rewinding is first performed to find the required position, and then the playback is performed, but this takes a considerable amount of time. Also, when you find the place you need, you may have to record it for the next scene. In such a case, you substantially lose the chance of slow playback.

An object of the present invention is to provide a video recording / reproducing apparatus that does not require rewinding time.

The present invention also aims to provide a video recording / reproducing apparatus capable of reproducing while recording and changing the reproduction speed.

It is another object of the present invention to provide a video recording / reproducing apparatus capable of receiving a plurality of inputs and simultaneously recording and reproducing them.

[Means for solving problems]

A video recording / reproducing apparatus according to the present invention, a plurality of sets of A / D converters for converting a television video signal into a digital signal, and a plurality of sets of A / D converters corresponding to the digital signals of a corresponding set. A plurality of sets of write registers, each of which has a plurality of write registers for loading, and a plurality of memories corresponding to the plurality of write registers. A memory unit capable of sequentially storing at least 30 frames of signals from a group, and a plurality of read registers corresponding to the plurality of sets of write register groups and corresponding to the plurality of write registers as one group , A second group, and a plurality of sets of read registers for loading the signals read from the memory unit, and read registers of each set. A plurality of sets of D / A converters for converting signals from the group into analog signals, and a control means for controlling write and read addresses and timings thereof, the plurality of sets of write register groups, and the plurality of sets. Of the read resist groups share the memory unit and perform writing and reading for each group in order. Writing and reading of each group is performed by loading the digital signal with the write register group of the first group and the second group. The write register groups of the groups are alternately performed, and while the load register groups of one group are being loaded, the data loaded in the write register groups of the other group are written to the memory unit and then written to the memory unit. The read data of the first group and the read register group of the second group are alternately loaded. The data loaded in the read register group of the other group is output to the D / A converter while being loaded in the read register group of the other group.

〔Example〕

Next, the present invention will be described with reference to the drawings. In FIG. 1, a video input signal is converted into a digital signal by an A / D converter 101. The converted signal is transferred to the write register R01 to R08 and the write register R11.
~ R18 applied to the register group. In this figure, each register group consists of 8 registers, but memory M1
~ It can be changed depending on the access speed of M8. These registers are configured so that data can be loaded individually, and their outputs are tri-stated. The signal is first loaded into the write register R01 by the write register controller 102. It is loaded into the write register R02 at the next clock, and is sequentially loaded up to the write register R08.

Next, the write register controller 102 sets the write register R
The data stored in the write registers R01 to R08 is written to the large-capacity memories M1 to M8 using this time.

Dynamic memory (DRAM) is used for the memory. Although the time required for writing and reading to and from the DRAM by the memory controller 103 is generally longer than the clock cycle, a time margin can be obtained by performing serial / parallel conversion of signals as described above, and writing can be performed without error. . In addition,
The clock used here is the clock used for A / D conversion, and in general, a frequency four times as high as the color subcarrier of the input video signal, that is, about 14.3 MHz or 13.5 MHz is often used. Therefore, the clock cycle is about 70 nsec, and 70 × 8 = 560 nsec can be used for writing to the DRAM, which is sufficient in terms of time.

The data held in the registers R01 to R08 while loading the input signals to the write registers R11 to R18 is stored in the memory M1.
Up to M8 has been described, but data is again loaded into the write registers R01 to R08 during the next 8 clock periods. During this period, the data held in the write registers R11 to R18 is written in the memories M1 to M8. Hereinafter, this operation is repeated. A common address is given to the memories M1 to M8,
1 each time data of each register group is written to memory
Increase by one. In this way the memory controller 10
By 3, the video input signal is recorded in the memories M1 to M8 by DRAM.

The total memory capacity must be at least 30 frames of the television signal. The capacity of 30 frames corresponds to 1 second.
The recording time of 1 second is the minimum required capacity for recording one shot in sports. Writing to memory,
The read address is composed of a portion required to record one field and a portion designating the field. Every time one field is written, the field portion of the address increases by one.

The written data is read from the memories M1 to M8 once every eight clocks and loaded into the register group of the read registers RR01 to RR08 or the read registers RR11 to RR18. The read registers RR01 to RR08 and RR11 to RR18 have the opposite effect of the register group on the write side, and convert parallel data to serial data. That is, the read register controller 10
4 is read registers RR11 to RR18 when data is being loaded from memories M1 to M8 into read registers RR01 to RR08.
Data is read sequentially from the
Read registers RR01 to RR when loading to RR11 to RR18
Read every clock from 08. The read data is applied to the D / A converter 105 to obtain an analog output. The write register controller 102, the memory controller 103, and the read register controller 104 are all controlled by a CPU (not shown).

Here, if the field designation part of the address on the read side is increased by 1 for every two fields, the read speed becomes 1/2 compared to the write side, so the output video becomes 1/2 slow motion image. . Also, if the field designating section address is left at a certain value, the same video is always output, and a still image can be obtained. Furthermore,
By decrementing by 1 for each field, it is possible to obtain an image that goes backwards in time. Various operations can be performed by operating the address field section in this manner.

In the above example, there is one video input and one output.
As shown in FIG. 2, the number of registers on the write side and the number of register groups on the read side can be increased to accommodate a plurality of inputs and a plurality of outputs.

The register group 1 in FIG. 2 is the write registers R01 to R01 in FIG.
08 and write registers R11 to R18, read register group 1 is read register RR01 to RR08 and read register
Corresponds to RR11 to RR18. That is, there are two register groups on the write side and the read side. In addition, in FIG.
The write register controller, memory controller, and read register controller controlled by the CPU are not shown. The register groups 1 and 2 on the write side receive signals obtained by A / D converting the inputs 1 and 2 by the A / D converters 201 and 202, respectively, and operate in parallel. Looking at one set of registers, the contents are divided into two sets, the same as the operation of the registers in Fig. 1, one set loads the data from the A / D converter, and the other stores the held data in the memory. It is used to write to. However, in the case of FIG. 2, since the data held by the register groups 1 and 2 are written in the memories M1 to M16, the time required for writing is twice as long as that in the case of FIG.
For this reason, the number of registers for serial-parallel conversion is doubled and 16 registers are used on each side. That is, both the input 1 and the input 2 are stored in the memories M1 to M16 during the 16 clock period.
I am writing to. When writing the input 1 and the input 2 in the memory, the write address is of course switched corresponding to each input, and the memory controller supplies the necessary address.

There are also two sets of read register groups on the memory read side, and each works in the same way as the read register group of FIG. From the memory, the read register group and the read register group are read within 16 clocks respectively, but since the read addresses can be specified independently, completely independent outputs can be obtained.
Since the register groups 1 and 2 on the write side and the read register groups 1 and 2 are completely independent, and the write and read addresses are also independent, the input 1 can be written to the output 2 and the input 2 can be output. It is also possible to output what is written in the output 1. Also, the output 1 can be output at the normal speed, and the same image can be output to the output 2 as a slow motion image.

In this example, the example of 2 inputs and 2 outputs is given, but it goes without saying that the number of inputs and outputs can be changed by increasing the number of registers.

〔The invention's effect〕

As described above, according to the present invention, the A / D converter, the write register group, the memory, the read register group, and the D / A converter are provided. It can output rich images. Moreover, unlike VTRs, there is no need to rewind data, and since there are no moving parts, there is no inertia in reading and completely random reading is possible. Furthermore, it has characteristics that conventional recording devices do not have, such as multiple input / output capabilities, and is a powerful weapon for producing TV programs.

[Brief description of drawings]

FIG. 1 shows a first embodiment of the present invention, and FIG. 2 shows a second embodiment of the present invention, which is a configuration diagram in the case of expanding to a plurality of inputs and a plurality of outputs. In the figure, R01 to R08 and R11 to R18 are write registers, M1 to M8 are memories, and RR01 to RR08 and RR11 to RR18 are read registers.

Claims (3)

[Claims] 1. A plurality of sets of A / D converters for converting a television video signal into a digital signal, and a plurality of sets of A / D converters for loading the corresponding set of the digital signals. A first group of a plurality of write registers,
A plurality of sets of write registers including a second group,
Comprising a plurality of memories corresponding to the plurality of write registers, a memory unit capable of sequentially storing at least 30 frames of signals from each set of write register groups, corresponding to the plurality of sets of write register groups, And a first and a second group in which a plurality of read registers corresponding to the plurality of write registers are one group,
A plurality of sets of read register groups for loading the signals read from the memory unit, a plurality of sets of D / A converters for converting signals from the read register groups of the respective sets into analog signals, and writing of these, A plurality of sets of write register groups and a plurality of sets of read register groups respectively share the memory unit, and perform writing and reading in sequence for each group. In writing and reading a set, the loading of the digital signal is alternately performed on the write register group of the first group and the write register group of the second group, and the write register group of one group is loaded. While being written, the data loaded in the write register group of the other group is written to the memory section, and the data written in the memory section is written. Note: The read register group of the first group and the read register group of the second group are alternately loaded, and while the read register group of one group is being loaded, the read register group of the other group is loaded. A video recording / reproducing apparatus, wherein the recorded data is output to a D / A converter. 2. A video recording / reproducing apparatus according to claim 1, wherein the order of writing or reading the digital signals is controlled according to a pre-programmed sequence. 3. A video recording / reproducing apparatus according to claim 1, wherein writing of an input signal and reading of an output signal are apparently performed simultaneously.