JPH0784813A - Cpu malfunction preventing circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction in a period from a CPU runaway to the detection of the runaway by a watchdog timer. CONSTITUTION:A memory 5 (FIFO) is provided between an OUT port 3 and a CPU circuit 1 and data and address information are temporarily stored in the memory 5; after normal CPU operation is confirmed by resetting the watchdog timer, the data and address information are read out of the memory by H/W and the data are outputted to a desired port. Even in case of the CPU runaway, only normal data are always outputted and a system with high reliability is constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a malfunction prevention circuit for a control circuit using a CPU.

[0002]

[Prior art]

Conventional example 1. As shown in FIG. 4, the conventional erroneous control prevention circuit includes a CPU circuit 1; a watchdog timer 2;
It consists of a UT port and 4 chip select circuits.

Next, the operation will be described. When the program of the CPU runs out of control, it is detected by the runaway detection circuit 2 such as a watchdog timer, the output of the OUT port 3 is inhibited, and the OUT port 3 after the runaway is detected.
Data output to

Conventional example 2. FIG. 5 is a schematic view of JP-A-2-41539.
FIG. 11 is a block diagram showing a configuration of a conventional erroneous control prevention circuit disclosed in Japanese Patent No. “CPU erroneous control prevention circuit”. In the figure, 10 is a CPU, 11 is a non-volatile storage unit that stores programs, 12 is a semiconductor memory unit that holds various data, 13 is an external signal control unit that controls power supply of a terminal, and 14 is a runaway monitoring timer unit. , 15 are write inhibit control circuits. When the CPU program runs out of control, the write prohibition control circuit 15 detects the bus information before the runaway monitoring timer unit 14 detects the runaway, and when the CPU does not write according to a predetermined procedure, or a predetermined When an address other than the address is accessed, the semiconductor memory unit 12 and the signal control unit 1 for the outside
Write-inhibit control to 3 is performed.

[0005]

Since the CPU erroneous control prevention circuit of Conventional Example 1 is constructed as described above, the CPU
If erroneous data is output to the OUT port between the time the runaway occurs and the runaway is detected by the watchdog timer, the system may be erroneously controlled.
Further, in the CPU erroneous control prevention circuit of Conventional Example 2, whether or not writing is being performed by the write prohibition control circuit according to a prescribed procedure is monitored, and S / W programming needs to be designed in consideration of the control. In addition, the write inhibit control circuit has a problem that it requires a complicated configuration. The present invention has been made to solve the above problems, and prevents malfunction of the time until detection by data during CPU runaway, and
The programming of W aims at obtaining a circuit which can be designed without considering the control of the CPU malfunction prevention circuit.

[0006]

A malfunction prevention circuit according to the present invention temporarily stores, for example, data output to an OUT port in a memory, confirms that a CPU is not running out, and then outputs the data. Yes, and has the following elements. (A) A memory for storing information output from the CPU,
(B) CPU runaway detection circuit that detects CPU runaway at predetermined time intervals and monitors the normal operation of the CPU, (c) C above
A memory control circuit that outputs the information stored in the memory as information from the CPU each time the PU runaway detection circuit confirms normal operation of the CPU.

[0007]

The CPU malfunction prevention circuit according to the present invention is C
The information output from the PU is stored in the memory, and the stored information is output every time the watchdog timer is reset, that is, the CPU runaway detection circuit confirms normal operation, so that normal data is always output. It Furthermore, a simple circuit can be configured by using, for example, a FIFO for the memory.

[0008]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, 1 is a CPU circuit, 2 is a watchdog timer, 3 is an OUT port, 4 is a chip select circuit, 5 is a memory (FIFO), and 6 is a memory control circuit.

Next, the operation will be described. CPU circuit 1
The data information and the address information output from the are stored in the memory (FIFO) 5. At the same time CPU circuit 1
From, a reset signal is output to the watchdog timer 2. Since the timing from one reset signal to the next reset signal is constant, the watchdog timer 2 recognizes that the CPU circuit 1 is operating properly. Correct operation of the CPU circuit 1 is synonymous with no runaway. Meanwhile, the memory (FIFO) 5 continues to accumulate data information and address information. Watchdog timer 2 is CPU
When the reset signal is received from the circuit 1 at a constant timing, the write reset signal is output to the memory (FIFO) 5 and the memory control circuit 6. This reset signal resets the writing of the memory (FIFO) 5, and simultaneously outputs the accumulated information. The output data is input to the OUT port 3 and the address is input to the chip select circuit 4, and the data is output to the desired port.

Further, when the watchdog timer 2 does not receive the reset signal from the CPU circuit 1 at a constant timing, it outputs an inhibit signal so that the data information and the address information are not inputted to the OUT port 3 and the chip select circuit 4. By setting, the output of abnormal data during runaway is prevented. As described above, since the data is always output after the normal operation is confirmed by the reset of the watchdog timer 2, all outputs from the runaway are inhibited, and erroneous control can be prevented. In addition, since the FIFO is read immediately after the watchdog timer 2 is reset, there is no conflict between writing and reading, and the H / W
It is possible to program S / W without any control. As described above, in the first embodiment, in the system controlled by the CPU, the memory (FIFO) for storing the data information and the address information issued from the CPU,
A memory control circuit for controlling the memory, an OUT port,
Chip select circuit that selects that port and CP
A CPU malfunction prevention circuit that is composed of a U runaway detection circuit (watchdog timer) and a CPU circuit that prevents malfunctions due to CPU runaway by H / W, and does not require any control in programming due to S / W explained.

Embodiment 2. Further, in the first embodiment, the output to the OUT port is controlled, but the OUT port may be a memory as shown in FIG. 2, and normal data is always written. Has a great effect.

Embodiment 3. FIG. 3 is a block diagram showing the configuration of the third embodiment, in which the output to the OUT port is such that the OUT port and the memory are mixed. Information output from the CPU is written as in the first and second embodiments.

Embodiment 4. In the first embodiment, the memory has a FIF.
Although the method using O is illustrated, the data and address may be output in order of higher priority, not limited to the FIFO. Even in that case, every time normal operation is confirmed,
If you output information from memory, after a runaway is detected,
It is possible to prevent malfunction due to data during runaway.

[0014]

As described above, according to the present invention, there is no need to design a S / W program in consideration of control or a write-inhibit control circuit having a complicated structure, and from the CPU runaway to its detection. In addition, it is possible to prevent erroneous data from being output after CPU runaway, and to achieve a malfunction prevention function of always outputting only correct data, thereby improving system reliability.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a CPU malfunction prevention circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a CPU malfunction prevention circuit according to a second embodiment.

FIG. 3 is a block diagram showing a configuration of a CPU malfunction prevention circuit according to a third embodiment.

FIG. 4 is a block diagram showing a configuration of a CPU erroneous control prevention circuit of Conventional Example 1.

FIG. 5 is a block diagram showing a configuration of a CPU erroneous control prevention circuit of Conventional Example 2.

[Explanation of symbols]

 1 CPU circuit 2 Watchdog timer 3 OUT port 4 Chip select circuit 5 Memory (FIFO) 6 Memory control circuit

Claims (1)

[Claims] 1. A CPU malfunction prevention circuit having: (a) a memory for storing information output from the CPU;
(B) CPU runaway detection circuit that detects CPU runaway at predetermined time intervals and monitors the normal operation of the CPU, (c) C above
A memory control circuit that outputs the information stored in the memory as information from the CPU each time the PU runaway detection circuit confirms normal operation of the CPU.