JPH0783360B2 - Synchronization method - Google Patents

Description

The present invention relates to a synchronization method for synchronizing clocks between network nodes in order to realize circuit switching in a local area network (LAN) or the like.

[Conventional technology]

In order to realize circuit switching on a LAN, etc., it is necessary to synchronize the communication speeds of at least the terminals connected to the transmitting side and receiving side nodes, which is conventionally time division multiplexing (TD).
It was realized by the M) method. That is, in addition to the node to which the terminal is connected, a control device for managing synchronization of the entire network is placed on the network, and a specific time slot of a fixed-length frame having a plurality of time slots is controlled by the control device. By allocating to the corresponding transmitting / receiving node, circuit switching is realized at the communication speed according to the number of allocated time slots such that the transmitting / receiving node always occupies a specific time slot.

Further, no circuit switching has been realized in a packet multiplexing network such as a token ring or a token bus.
According to the "Data transfer control method" filed on March 14, it has been proposed that circuit switching can be realized by controlling the transfer delay of the transmission / reception buffer, assuming that synchronization is established over the entire network. .

[Problems to be solved by the invention]

However, in traditional circuit-switched networks, the networks are synchronized throughout,
Further, the speed of the circuit switching service depends on the communication speed in the network. Conversely, the communication speed of the network is determined from the common multiple of various line speeds, and the communication speed establishes synchronization between network nodes.

Therefore, according to the conventional method, it is necessary to provide a control device on the network to establish synchronization over the entire network, and the speed of the circuit switching service must be dependent on the communication speed in the network. There was a problem such as.

The present invention has been made to solve the above problems and enables circuit switching in a packet multiplex network such as a token ring or a token bus without depending on the communication speed in the network. The purpose is to obtain a synchronization method that can establish synchronization between specific nodes in a network.

[Means for solving problems]

According to the synchronization method of the present invention, in a packet multiplexing network, a node that functions as a synchronization master when establishing clock synchronization between nodes supplies a basic clock to a terminal connected to the node and A basic clock generating means 6 for generating phase information as digital information of a predetermined bit is provided, and the digital phase information is sent out as a packet on the network,
The node functioning as a synchronization slave is provided with a basic clock reproducing means 7 for reproducing a clock synchronized with the basic clock, and establishes synchronization between the nodes.

[Action]

In the present invention, when establishing clock synchronization between nodes of a packet multiplex network such as a token ring or a token bus, a node that functions as a master of synchronization is supplied to the terminal with digital phase information of a basic clock (master clock). Is generated by the basic clock generating means 6, and the packet is sent to the network as a packet addressed to the partner node. On the other hand, the node functioning as a synchronization slave receives the digital phase information, reproduces the slave clock synchronized with the master clock by the basic clock reproduction means 7, and supplies this to the terminal. This establishes synchronization between specific nodes.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. First
The figure is a diagram showing a configuration of a main part which becomes a node. In the figure, reference numeral 1 denotes a node, which is connected by a transceiver 2 to a transmission line 11 forming a network as described above. A transmission / reception control circuit 3 has a medium access control according to the network system and a transmission / reception control function of data including basic clock phase information described later. Four
Is a transmission data buffer, which temporarily stores transmission data from the terminal 13 connected through the terminal interface line 12. The data stored in the transmission data buffer 4 is received by the node 1 when a token arrives. When the transmission right is acquired by, it is sent out in a burst to the transmission line 11. 5
Is a reception data buffer that receives data addressed to the terminal 13 from the transmission line 11, accumulates the data, and continuously sends the data to the terminal 13. Here, the communication speed on the transmission line 11 is sufficiently higher than the communication speed of the terminal 13, and the continuous data stream on the terminal interface line 12 is in a time-compressed form on the transmission line 11. It corresponds to a data stream that flows in bursts (intermittently). In order to realize circuit switching by the packet multiplexing network, it is important to prevent underflow and overflow of the reception data buffer 5 and guarantee a continuous data stream. This is possible by controlling the transmission / reception buffer as described in "Data transfer control method". On the other hand, 6 is a basic clock generating circuit, and 7 is a basic clock reproducing circuit, which is a characteristic circuit serving as means for realizing the synchronization system of the present invention. In this embodiment, the function of the basic clock generation circuit 6 is used when the node 1 is the clock master, and the function of the basic clock regeneration circuit 7 is used when the node is the clock slave. Reference numeral 8 is a selector circuit, and whether to supply the master clock 14 of the basic clock generation circuit 6 or the slave clock 15 of the basic clock reproduction circuit 7 to the terminal 13 is switched by a selector control signal 9 set by an operator or the like. be able to. It is also possible to supply both the master clock 14 and the slave clock 15 to the terminal 13 so that the transmission function of the terminal 13 is operated by the master clock 14 and the reception function is operated by the slave clock 15. The issue of selection of is not the object of the present invention. Reference numeral 10 denotes a terminal interface circuit for interfacing the transmission / reception data buffers 4, 5 and the selector circuit 8 with the terminal 13. As the terminal interface line 12, a standard interface such as RS232C is used.
To provide.

FIG. 2 shows the basic clock generation circuit 6 in this embodiment.
It is a figure which shows the structural example. In the figure, 61 is an oscillation circuit,
Reference numeral 62 is a frequency divider circuit that can obtain an intermediate output. In this example, 8
As a frequency divider circuit, the final output becomes the master clock 14 supplied to the terminal 13 and each frequency division stage π / 8, π / 4, π /
The 4-bit digital value of 2, π is the above master clock 14
Is output to the transmission / reception control circuit 3 as phase information. That is, the frequency dividing circuit 62 realizes the function of generating the master clock 14 and the function of generating the digital phase information thereof by one circuit.

FIG. 3 shows a time chart of the input, the intermediate output and the final output of the frequency dividing circuit 62, that is, the master clock 14, in which the phase of one cycle (2π) of the master clock is π / 8 steps, that is, It shows that it is digitized with 4 bits. When the master node transmits the phase information of the master clock 14, the latest data of this digital phase, that is, the digital phase information (master phase information) at the time of transmission is transmitted.

FIG. 4 shows the basic clock recovery circuit 7 in this embodiment.
It is a figure which shows the structural example. In the figure, 71 is a 4-bit master phase register that holds the digital phase information transmitted from the master node and input through the transmission / reception control circuit 3, and 72 is a slave phase register that holds the digital phase information of the slave clock 15. Therefore, the contents held in the registers 71 and 72 are updated by the phase information reception pulse 31 output from the transmission / reception control circuit 3 every time the master phase information is received. 73 is a subtracter, and each of the above registers 71 and 72
The D / A converter 74 converts the phase difference into an analog voltage and supplies it to the voltage controlled oscillator (VCO) 75 to control the oscillation frequency. Voltage controlled oscillator 75
2 is input to a frequency divider circuit 76 similar to that shown in FIG. 2, and this frequency divider circuit 76 generates a slave clock 15 to be supplied to the terminal 13 and at the same time generates digital phase information of the slave clock 15 and outputs it. Supply to the slam phase register 72. That is, the basic clock recovery circuit 7 is the same as the conventional PLL except that the phase information is sampled and compared.
There is no fundamental difference, and if the fluctuation of the phase difference is sufficiently small compared to the sampling period, the slave phase can be locked to the master phase by the sampling theorem.

FIG. 5 is a diagram showing the configuration of the second embodiment of the basic clock recovery circuit. In the figure, 76A is a variable frequency dividing circuit for dividing the reproduction clock by a predetermined ratio and outputting the slave clock 15 and simultaneously outputting the slave phase information.
A is a difference between the master phase information and the slave phase information obtained by subtracting the master phase information and the slave phase information transmitted from the master node and input through the transmission / reception control circuit 3, and all the error information Alternatively, it is a subtractor as an arithmetic circuit, a part of which is used as phase control information to the frequency dividing circuit 76A.

In such a configuration, the phase information reception pulse 31 is generated each time the master phase information is received, and is given to the variable frequency dividing circuit 76A to hold the value of the phase control information 71A at that moment. The variable frequency dividing circuit 76A adjusts the slave phase according to the held value and operates so as to keep the error with the master phase constant. That is, if the stave phase is delayed with respect to the master phase, the phase control information 71A shows a positive value, and at this time, the variable frequency dividing circuit 76A corrects the frequency division ratio to advance the slave phase. Conversely, if the slave phase leads the master phase, the phase control information 71A shows a negative value, and at this time, the variable frequency dividing circuit 76A corrects the slave phase by increasing the frequency division ratio. FIG. 6 is a list of error information, which shows 4-bit phase information in hexadecimal. From FIG. 6, when the error information is 0 to 7 (positive value), the slave phase is equal to or behind the master phase, and when the error information is 8 to F (negative value), it is compared to the master phase. Then, it is understood that the slave phase is advanced. Therefore, the variable frequency divider circuit is used by using only the positive and negative sign bits (π phase information) of the error information.
76A can be controlled. In FIG. 5, the π phase of the error information is used as the phase control information 71A.

FIG. 7 is a detailed diagram of a configuration example of the variable frequency dividing circuit 76A, which is a very well known circuit.

In FIG. 7, if the output of the AND gate G2 is always "H", the JK flip-flop FF3 simply divides the reproduction clock 63 into two, and the synchronous 4-bit counter C1 and
Together with C2, it constitutes a 512 divider circuit.

FIG. 8 is a time chart showing the operation of the variable frequency dividing circuit 76A when correcting the delay of the slave phase.

The operation of the variable frequency dividing circuit shown in FIG. 7 will be described with reference to FIG.

When the slave phase lags behind the master phase, the phase control information 71A is "L", and FF1a is set at the trailing edge (rising edge) of the phase information reception pulse 31. If the Q output of FF1a becomes "H" and the Q output of FF3 is "L", the AND condition is satisfied and the output of G1a becomes "H". When the reproduced clock 63 is generated in this state, the Q output of FF3 is converted to "H" at the trailing edge (falling edge), and the Q output of FF2a also becomes "H" and at the same time FF1a.
Is reset. Now, if FF2a is set, AN
Since the output of the D gate G2 becomes "L", the state of FF3 remains unchanged with the generation of the next reproduction clock, and Q = "H".
Hold. Therefore, the synchronous 4-bit counter C1 in the next stage
On the other hand, the carry input (CI) is continuously applied for two clocks, so that advance control equivalent to π / 512 is performed. In FIG. 8, the dotted line shows the case where variable frequency division control is not performed.
The operation of FF3 and C1 (π / 128 phase output) is shown.

FIG. 9 is a time chart showing the operation of the variable frequency dividing circuit when the slave phase leads the master phase, and a description thereof will be omitted.

By the variable frequency division control as described above, the slave phase can be made to follow the master phase transmitted through the packet multiplexing network.

The number of frequency division stages of the variable frequency dividing circuit 76A and the bit width of the master and slave phase information may be appropriately determined from the transmission / reception clock deviation, the transmission interval of the master phase, and the allowable error of the master and slave phases.

Next, the operation will be described with reference to FIGS. 10 to 13 which are conceptual diagrams and frame configuration diagrams of the synchronization system of the present application.

As shown in FIG. 10, the synchronization method of the present application transmits the current time t _n measured by the transmission side clock (master clock) to the reception side as phase information, so that the reception side clock (slave clock) t ′ _n The delay advance ± Δn of is corrected and synchronized with the master clock. At this time, the transmission delay τ must be constant, but the transmission interval
t _{n + 1} −t _n does not have to be a constant cycle, and the maximum value of the transmission interval is defined by the degree of error in the transmission / reception clock. The propagation delay τ is the time during which a packet flows on a predetermined transmission line and is always constant. In a packet multiplex network such as a token ring or a token bus, the upper limit of the transmission waiting time of each node is guaranteed by the circulation of tokens and the like, and the constituent elements of the basic clock generation circuit 6 and the basic clock regeneration circuit 7 are Even when the transmission waiting time is maximized, the above condition is satisfied by making the accuracy high enough to allow the error of the transmission / reception clock. Therefore,
On the receiving side, the current time on the transmitting side is received, and t _{n + 1} −t _n = t ′
It is possible to synchronize with the master clock by correcting the slave clock so that _{n + 1−} t ′ _m , that is, the error Δn becomes constant.

Next, a specific description will be given with reference to FIG. On the transmission side, the oscillation frequency of the oscillator circuit 61 is divided by the divider circuit 62,
The master clock of frequency foHz and the phase information θo quantized in 1 / 8π steps are generated, and the phase information θo (ti) at the transmission time ti is sampled and transmitted on the network in the frame structure shown in FIG. It This phase information θo (ti) arrives at the reception side with a network transmission delay τ and is serial-parallel converted by the reception register 3a in the transmission / reception control circuit 3. At this time, the transmission / reception control circuit 3 issues the phase information reception pulse 31 based on the frame type FC of the reception frame, and at this timing, the phase information θo (ti) is held in the master phase register 71 and the frequency fcHz.
Phase information θc (ti +
τ) is sampled and held in the slave phase register 72. Phase information θ held in each of the above registers 71, 72
o (ti) and θc (ti + τ) are complement circuit 73a and adder circuit 73b.
It is input to the subtractor 73 composed of and and the phase difference is obtained. Then, the phase difference output as a digital value is converted to an analog value by the D / A converter 74, and the phase difference θo (ti) −θc (ti +
It is applied as a control voltage proportional to τ). In the voltage controlled oscillator 75, the oscillation frequency is controlled by the control voltage so that the phase difference becomes constant, and its output is input to the frequency dividing circuit 76. The frequency divider circuit 76 divides the oscillation frequency to generate a slave clock in synchronization with the master clock, and also generates phase information θc for preparing for the reception timing of the next phase information reception pulse 31.

Here, the conditions for synchronization will be described with reference to the figure. The network transmission delay τ is constant and the transmission interval t
Minimum value of sampling frequency regulated by _{n + 1} −t _n 1 /
According to the sampling theorem, (1t _{n + 1} −t _n ) max is more than twice the maximum deviation between the frequencies fo and fc of the master clock and the slave clock. As mentioned above, the transmission delay τ is constant, and if the fluctuation of the phase difference is made sufficiently small compared to the sampling period by making each clock highly accurate, the slave phase can be locked to the master phase, and Synchronization can be established by transmitting the master phase information through the network between specific nodes that are installed apart from each other.

Further, when the circuit shown in FIG. 5 is used as the basic clock reproducing means, as shown in FIG. 13, the phase information θo at the transmission time ti transmitted in the frame structure on the network is received with the network transmission delay τ. It reaches the side and is serial-parallel converted by the reception register 3a in the transmission / reception control circuit 3. At this time, the frame type FC of the reception frame from the transmission / reception control circuit 3
Phase information reception pulse 31 based on
The phase control information 71A obtained by the above is given to the variable frequency dividing circuit 76A at this timing and the variable frequency dividing control is performed, and the slave phase can be synchronized with the master phase.

As long as clock synchronization is established between nodes, circuit switching can be realized in a packet multiplexing network.

Further, according to the synchronization system of the present application, the following three types of synchronization systems are possible with the destination address DA having the frame structure shown in FIG.

Case 1; When DA is a broadcast address, the whole system synchronizes with one master.

Case 2: When the DA is a multicast address, it has a master for each group and synchronizes for each group.

Case 3: When DA is an individual address, synchronization can be established between opposite nodes.

That is, it is possible to form a network in which a circuit switching function at an arbitrary communication speed is added to the conventional network without having a special control device for controlling the entire network (Case 1), and it has been considered impossible in the past. It was possible to form a network in which different synchronous systems coexisted (case 2,
3) In this case, circuit switching can be realized at any communication speed between the corresponding nodes without depending on the synchronization and communication speed of the entire network.

In the above description, the oscillation circuit 61 is included in the basic clock generation circuit 6, but the clock supplied from outside the node is treated in the same manner as the output of the oscillation circuit 61, and the synchronization between the nodes is synchronized by the external clock. Of course, it is also possible to establish.

Also, an example of the individuality of the node 1 having both the basic clock generating circuit 6 and the basic clock reproducing circuit 7 is shown, but only one of the above may be provided depending on the node.

〔The invention's effect〕

As described above, according to the present invention, it is possible to establish synchronization between the nodes connected via the packet multiplexing network,
Moreover, the clock of the slave node can be synchronized with the basic clock of the master node regardless of the communication speed in the network. Furthermore, by installing multiple master nodes in the network and sending the master phase information transmitted from each master node as a multicast frame designating different destination node groups or by designating individual addresses, it becomes impossible at all. A plurality of synchronous systems can simultaneously exist in the existing network, and circuit switching can be realized without depending on the synchronization of the entire network or the communication speed.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a node according to an embodiment of the present invention, FIG. 2 is a block configuration diagram showing an example of a basic clock generation circuit, and FIG. 3 is a frequency divider circuit in a basic clock generation and basic clock regeneration circuit. FIG. 4 is a configuration diagram showing an example of the basic clock regeneration circuit, FIG. 5 is a configuration diagram showing another example of the basic clock regeneration circuit, and FIG. 5 is a diagram showing a list of error information output from the subtractor in FIG. 5, FIG. 7 is a configuration diagram showing a detailed configuration of the variable frequency dividing circuit in FIG. 5, and FIG. 8 is a slave phase delay in FIG. FIG. 9 is a time chart showing the operation of the variable frequency divider circuit in the case where is corrected, FIG. 9 is a time chart showing the operation of the variable frequency divider circuit when the slave phase leads the master phase, and FIG. From this 11 is a conceptual diagram for explaining the conditions of the synchronization system, FIG. 11 is a frame configuration diagram in the embodiment, and FIG. 12 is a diagram for explaining the operation of the synchronization system when the basic clock reproducing means shown in FIG. 4 is used. FIG. 13 is a schematic diagram for explaining the operation of the synchronization system when the basic clock reproducing means shown in FIG. 5 is used. 1 ... Node, 2 ... Transceiver, 3 ... Transmission / reception control circuit, 4 ... Transmission data buffer, 5 ... Reception data buffer, 6 ... Basic clock generation circuit (basic clock generation means), 7 ... Basic clock Regeneration circuit (basic clock regeneration means), 8 ... Selector circuit, 9 ... Selector control signal, 10 ... Terminal interface circuit, 11 ... Transmission line,
12 …… Terminal interface line, 13 …… Terminal, 14 …… Master clock (basic clock), 15 …… Slave clock, 31 …… Phase information reception pulse, 61 …… Oscillation circuit, 62…
… Dividing circuit, 63 …… Reproduction clock, 71 …… Master phase register, 72 …… Slave phase register, 73,73A …… Subtractor, 74 …… D / A converter, 75 …… Voltage controlled oscillator, 7
6 …… Dividing circuit, 76A …… Variable dividing circuit. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (7)

[Claims] 1. In a packet multiplex network, a node that functions as a master of synchronization when establishing clock synchronization between nodes includes basic clock generation means for generating phase information of a basic clock as digital information of predetermined bits, The node that sends the digital phase information as a packet on the network and functions as a synchronization slave is provided with a basic clock recovery means that receives the digital phase information via the network and recovers a clock synchronized with the basic clock. , A synchronization method characterized by establishing synchronization between nodes. 2. The synchronization system according to claim 1, wherein the node comprises both basic clock generating means and basic clock reproducing means. 3. The synchronization system according to claim 1, wherein the node comprises one of a basic clock generating means and a basic clock reproducing means. 4. The basic clock generating means comprises an oscillation circuit and a frequency dividing circuit for dividing the output frequency of the oscillation circuit and outputting the digital value of each frequency division stage to generate the phase information of the basic clock. Claim 1 characterized in that
The synchronization method described in the section. 5. The basic clock generating means comprises a frequency dividing circuit for dividing the frequency of a clock input from the outside and outputting a digital value of each dividing stage to generate phase information of the basic clock. The synchronization method according to claim 1, wherein 6. The basic clock reproducing means includes a master phase register for holding digital phase information received via a network, a voltage controlled oscillator whose oscillation frequency can be controlled by a control voltage, and an output frequency of the oscillator. A frequency divider circuit that divides and outputs the digital value of each frequency division stage to generate phase information of the clock, a slave phase register that holds the digital phase information output from the frequency divider circuit, and the master register. And a subtractor that subtracts the output of the slave phase register to output their phase difference, and a D / A converter that converts the digital output of the subtractor to an analog voltage and supplies it as the control voltage of the voltage controlled oscillator. The synchronization method according to claim 1, wherein 7. The basic clock reproducing means comprises a variable frequency dividing circuit capable of varying a clock frequency dividing ratio, a master phase received via a network, and a slave phase generated by the variable frequency dividing circuit at a receiving node. 3. The synchronization system according to claim 1, further comprising: an arithmetic circuit that controls the frequency division ratio of the variable frequency dividing circuit by comparing the slave frequency and the master phase. .