JPH0783355B2 - Synchronous word multiplexer - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync word multiplexer for use in a frame format data transmission system and for multiplexing sync word data with communication data.

[0002]

2. Description of the Related Art In a frame format data transmission system, frame data such as a unique word (UW) is required at the beginning of a frame, and a synchronization word forming this UW must have a predetermined specific pattern. Therefore, the UW data includes scramble, error correction coding,
Since data processing such as the punctured coding method cannot be performed, the timing control circuit prohibits it. FIG. 4 is a block diagram showing an example of a conventional synchronization word multiplexer. In the figure, 21 is a communication data storage unit that stores communication data, 22 is a first punctured encoding circuit that convolutionally encodes the read communication data 201, and 25 is a bit for this encoded communication data 203. A second punctured encoding circuit for stealing, and 26 is a data rate conversion circuit for converting the data rate of the bit stealed communication data 205. Reference numeral 23 is a sync word storage unit that stores a sync word pattern 202 that forms the UW. Further, 24 is a multiplexing circuit for multiplexing the communication data 206 from the data rate conversion circuit 26 and the synchronization word 202 from the synchronization word storage unit 23 to obtain output data 207.
Reference numeral 27 denotes the storage units 21 and 2 based on the frame signal FS.
3 and signals 208, 209 and 211, 212, 21 for timing control of the respective circuits 25, 26, 24.
The timing control circuit outputs 0.

The operation of the synchronous word multiplexer of this configuration will be described with reference to the waveform diagram of FIG. The communication data 201 is read from the communication data storage unit 21 by the communication data read signal 208 from the timing control circuit 27, and the communication data 201 is converted into convolutional coded data 202 by the first punctured coding circuit 22 and further the second punctured data. The data 205 is bit stealed by the bit steal signal 211 in the Chad encoding circuit 25, and the data rate conversion circuit 26 performs data rate conversion by the data rate conversion clock 212 to obtain data 206. On the other hand, the sync word pattern 202 is read from the sync word storage unit 23 by the sync word read signal 209. And this synchronization word pattern 2
02 and the speed-converted communication data 206 are multiplexed in the multiplexing circuit 24 by the multiplexed signal 210 to obtain output data 207. Here, when bit stealing and rate conversion are performed on the wireless data, the punctured coded signal is generated so as to prohibit these operations at the insertion portion of the synchronization word pattern 202 multiplexed in the multiplexing circuit 24. The sync word insertion portion of at least one of 211 and the data rate conversion clock 212 must be masked. In the example of FIG. 5, the portions corresponding to both signals 211 and 212 are masked. When masking, the multiplexed signal 21
0 is used.

[0004]

In such a conventional sync word multiplexing system, in order to prohibit punctured coding to the sync word insertion portion, the timing control circuit 27 causes the punctured coded signal 211 and data to be transmitted. Speed conversion clock 2
It is required to have circuitry to partially mask at least one of the twelve. In the above example, the multiplexed signal 2
Since 10 is used for masking, a gate circuit for controlling the punctured coded signal 211 and the data rate conversion clock 212 in accordance with the multiplexed signal 210 is required. Therefore, there is a problem that the circuit of the timing control circuit 27 becomes complicated and the circuit scale becomes large. An object of the present invention is to provide a synchronization word multiplexing device which can realize simplification and downsizing of the entire device by simplifying a timing control circuit.

[0005]

According to the present invention, communication data storage means for storing communication data, specific pattern storage means for storing a specific pattern in which dummy data is inserted in synchronization word data, and read from each storage means. A multiplexing unit that multiplexes the communication data and the specific pattern to output the multiplexed data, and a unit that performs bit stealing on the multiplexed data and steals at least the dummy data of the specific pattern. For example, communication data storage means for storing communication data, specific pattern storage means for storing a specific pattern that becomes a sync word pattern when bit stealing is performed, communication data read from each storage means and a specific pattern are multiplexed. Multiplexing means for converting the multiplexed data to output multiplexed data, punctured coding means for bit stealing the multiplexed data, data rate converting means for converting the data rate, and reading of communication data and a specific pattern And a timing control means for outputting a timing signal for multiplexing in the multiplexing means, a timing signal for bit stealing in the punctured encoding means, and a timing signal for conversion in the data rate converting means. Here, the timing control means is configured to continuously output the timing signal supplied to the punctured coding means and the timing signal supplied to the data rate conversion means.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a synchronization word multiplexer of the present invention. In the figure, 11 is a communication data storage unit that stores communication data, and 12 is a first convolutional code of the communication data 101 read from the communication data storage unit 11.
It is a punctured encoding circuit. Reference numeral 13 is a specific pattern storage unit that stores a specific pattern that becomes a required synchronization word pattern when bit stealing is performed in the second punctured coding circuit provided in the subsequent stage. A multiplexing circuit 14 multiplexes the specific pattern 102 read from the specific pattern storage unit 13 and the communication data 103 from the first punctured coding circuit 12 in this order. Reference numeral 15 is a second punctured coding circuit for performing bit stealing on the multiplexed data 104,
Reference numeral 16 is a data rate conversion circuit for converting the data rate of the bit stealed communication data 105, and the output data 107 is output from this data rate conversion circuit. 17
Is a timing control circuit, which outputs signals 108 to 112 for controlling the timings of the storage units 11 and 13 and the circuits 14, 15 and 16 based on the frame signal FS.

The operation of the synchronous word multiplexer of this configuration will be described with reference to the waveform diagram of FIG. The communication data 101 is read from the communication data storage unit 11 by the communication data read signal 108 from the timing control circuit 17, and the read communication data 101 is subjected to convolutional coding in the first punctured coding circuit 12. You get 103. Further, the specific pattern 102 is read from the specific pattern storage unit 13 by the specific pattern read signal 109.
Further, the multiplexed signal 110 from the timing control circuit 17
Thus, the specific pattern 102 and the wireless data 103 are multiplexed in the multiplexing circuit 14. Then, the second punctured coding circuit 15 bit steals the multiplexed output data 104 output from the multiplexing circuit 14 to obtain data 105, and then the data rate conversion circuit 16 determines the data rate. The output data 107 is obtained by conversion. The output data 107 is composed of a sync word pattern 102 'and punctured encoded normal communication data 103'.

That is, the specific pattern 102 stored in the specific pattern storage unit 13 is a specific pattern which becomes a sync word pattern 102 'when bit stealing is performed, as shown in FIG. In this example, the synchronization word pattern 1
Specific pattern 10 with dummy data DD inserted in 02 '
It is supposed to be 2. The specific pattern 102 and the communication data 103 convolutionally coded by the first punctured coding circuit 12 are multiplexed, and multiplexed output data 1 obtained
When the second punctured encoding circuit 15 performs bit stealing on 04, that is, by bit stealing on each of the specific pattern 102 and the communication data 103, the dummy data DD is stolen on the specific pattern 102. The original synchronization word pattern 102 ′ is obtained, and the communication data 103 is punctured encoded data 10
3 '.

Therefore, the punctured coded signal 111 and the data rate conversion clock 112 for operating the second punctured coding circuit 15 and the data rate conversion circuit 16, respectively, are constantly output from the timing control signal 17, and based on this. Even if bit stealing or data rate conversion is performed on the multiplexed output data 104,
Target output data 107 can be obtained. As a result, in the timing control circuit 17, the punctured coded signal 11 is generated based on the multiplexed signal as in the conventional case.
1 and the circuit for masking the data rate conversion clock 112 are not required, and the configuration of the timing control circuit 17 is simplified, which makes it possible to realize simplification and downsizing of the entire synchronization word multiplexer. .

It should be noted that although the above description shows an example of punctured coding, if the present invention is a sync word multiplexer for bit stealing data, the sync word pattern position corresponding to the data to be stolen is set. If a specific pattern in which dummy data is inserted in advance is prepared and bit stealing is performed after multiplexing this with communication data, the device can be similarly simplified and downsized.

[0011]

As described above, according to the present invention, a specific pattern in which dummy data is inserted in a sync word pattern is multiplexed with communication data, bit stealing is performed on the obtained multiplexed data, and at least dummy data is stored. Since it is configured to steal, all data after multiplexing the synchronization word and communication data can be bit-stealed, there is no need to limit bit stealing, control of bit-steal operation is simplified, and the device is simplified. It can be made smaller and smaller. In particular, punctured coding means for bit stealing multiplexed data, data rate conversion means for converting the data rate, and timing signals for controlling these punctured coding means and data rate conversion means are provided. In the synchronization word multiplexer including the timing control means for outputting, it is not necessary to mask the synchronization word insertion portion of the bit steal signal or the speed conversion clock as these timing signals, and the configuration of the timing control circuit is simplified, It is possible to realize simplification and downsizing of the synchronization word multiplexer.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a synchronization word multiplexer of the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation of the device of FIG.

FIG. 3 is a pattern diagram showing a specific pattern and a synchronization word pattern.

FIG. 4 is a block diagram of an example of a conventional synchronization word multiplexer.

5 is a signal waveform diagram for explaining the operation of the apparatus of FIG.

[Explanation of symbols]

 11 Communication Data Storage Unit 12 First Punctured Encoding Circuit 13 Specific Pattern Storage Unit 14 Multiplexing Circuit 15 Second Punctured Encoding Circuit 16 Data Rate Conversion Circuit 17 Timing Control Circuit

Claims (3)

[Claims] 1. A communication data storage means for storing communication data, a specific pattern storage means for storing a specific pattern in which dummy data is inserted in synchronization word data, and communication data and a specific pattern read from each storage means. And multiplexing means for multiplexing and outputting multiplexed data, and means for performing bit stealing on the multiplexed data and stealing at least the dummy data of the specific pattern. apparatus. 2. Communication data storage means for storing communication data, specific pattern storage means for storing a specific pattern that becomes a sync word pattern when bit stealing is performed, and communication data read from each storage means and specified. Multiplexing means for multiplexing the pattern and outputting the multiplexed data; punctured coding means for bit stealing the multiplexed data; data rate converting means for converting the data rate; and the communication data and Timing control means for outputting a read timing signal in a specific pattern, a multiplexing timing signal in a multiplexing means, a bit steal timing signal in a punctured coding means, and a conversion timing signal in a data rate conversion means And a synchronization word multiplexer including. 3. The synchronization word multiplexing according to claim 2, wherein the timing control means is configured to continuously output the timing signal supplied to the punctured coding means and the timing signal supplied to the data rate conversion means. apparatus.